DESIGN OF A SINGLE ENDED TWO contributes the most to the gain, while the

STAGE OPAMP USING 90nm CMOS gpdk second stage contributes the most to the swing.
TECHNOLOGY
Miller Capacitance, also called as the
compensation capacitance is used for stabilizing
Simrit Saroa, Student ID: 006338696 the op-amp but it also reduces the bandwidth.
Amninder Gill, Student ID: 006204328 In order to improve the bandwidth, we add a
series resistance with the capacitor. The value of
the resistance and the capacitor decide the phase
ABSTRACT: The Final Project has been margin and bandwidth of the op-amp. Both the
designed with the aim of accomplishing the phase margin and the bandwidth requirements
task of Design of a Single Ended Two Stage cannot be met simultaneously. Either the phase
Operational Amplifier using 90nm CMOS margin increases and the bandwidth decreases,
gpdk technology. 1.2V operating supply has or the vice-versa happens. Hence, there is a
been used in the design. The design has been trade-off between the two, which can be
optimized trying to meet the required resolved depending upon the type of application
specifications. The Cadence tools have been for which the op-amp has been designed.
used for the same. Also, simulations have been
performed using SpectreS. The optimized
performance has been carried out to maximize
gain, bandwidth, output voltage swing, slew II. SCHEMATIC
rate, phase margin, along with minimizing the
settling time, and power dissipation. The two stage single ended op-amp has been
implemented in CADENCE by using the
following schematic.
I. INTRODUCTION The first stage consists of a differential pair
input implemented using PMOS transistors PM0
Op-amp is an acronym for Operational
and PM1 driving the NMOS current mirror
Amplifier. It is a DC coupled high gain
loads NM0, NM1. The PMOS transistor PM2 is
electronic voltage amplifier with differential
used to provide the biasing current. Since the
inputs, and the output may be single ended or
input is fed to the gates of NM0 and NM1, the
fully differential. Differential inputs provide two
op-amp has an infinite input resistance which is
input signals the difference of which is
required for proper functioning of the circuit.
amplified and made available at the output. This
helps in eliminating noise at the input. Single The second stage consists of a common source
ended output is obtained from one of the amplifier with NMOS transistor NM2 as the
transistors (in the differential pair) with respect basic amplifier and PMOS PM3 as the load. The
to ground. Two stage op-amps are those which output resistance of the op-amp is the resistance
provide two stages of gain. Thus, the overall looking back into the second stage and is given
gain of the amplifier is the product of the gains by R0 = rdsNM2 || rdsPM3.
provided by the two stages. Though there may
be added another stage (the output stage), which C1 is the compensation capacitance which is
acts as a buffer (gain is approximately equal to used to compensate the decrease in gain with
1) that does not provide any gain, but, is used for increase in frequency. In other words, it assists
impedance matching for external circuitry that in increasing the bandwidth but, adversely
may be driven by the amplifier. affects the slew rate to a great extent. It also
helps in preventing the oscillations in the circuit
The first stage is formed by the differential
when connected in feedback loop.
amplifier pair, and the second stage is formed by
the common source amplifier. The first stage
The circuit is fully functional when all the
transistors are operating in the active region.
Hence, the first and second stage amplifiers have GAIN: Specification value is > 60dB.
an infinite resistance. Thus, we can find the
overall voltage gain of op-amp by separately Gain is one of the characteristic properties of the
considering the gain of individual stages (as has transistor which make it act as an amplifier. It is
been described in the section below). the ability due to which a small signal at the
input can be converted to a very large signal at
Compensation capacitor C1 also influences the the output. If Av1 is the gain of the first stage,
output resistance of the differential stage and Av2 is the gain of the second stage, then, the
especially at mid-band frequencies and thus overall gain of the amplifier is Av.
affects the overall gain of the amplifier.
Applying the Miller effect on capacitor C 1, we The gain of differential stage is given by
get the equivalent capacitance at input of PM2 Av1 = gmNM1 * (rdsNM1 || rdsPM1) (3)
as output impedance of first stage is
Ceq = C1 * (1 + Av2) or C1 * Av2 (1) And the gain of second stage is given by
given Av2 >> 1
Thereby, making the output impedance of first Av2 = - gmNM2 * (rdsNM2 || rdsPM3) (4)
stage as thereby giving the overall gain equal to
Zeq = rdsNM1 || rdsPM1 || 1/sCeq, or
Zeq = rdsNM1 || rdsPM1 || 1/s*C1*Av2 (2) Av = - gmNM1* (rdsNM1 || rdsPM1) * gmNM2* (rdsNM2 ||
And the gain A1 = gm1 || Zeq or gm1/s*C1*Av2 rdsPM3) (5)

Factors affecting Gain:

1) Gain is directly proportional to the (W/L)

ratio of the transistors.

(6)

2) Gain is inversely dependent upon the square

root of the drain current.
3) Smaller is the overdrive voltage, larger is the
gain. This smaller overdrive voltage is
further going to help in getting the output
voltage swing.

(7)

Fig. 1 Schematic of the project

III. DESIGN SPECIFICATIONS
 limit, as it will adversely affect the slew rate
(as will be observed in the coming sections).
2) The second pole is determined by the value
of the load capacitance. Smaller the value of
load capacitance, higher will be the second
pole value.
3) It further depends upon the
transconductance of the amplifier PM3.
Higher the transconductance value, larger is
the second pole value.
4) The value of the resistance R1 when
increased from 100 ohms to a very large
value of 1000 ohms, improved the
bandwidth and the phase margin. But, it
drastically affected the slew rate and the
settling time. Then, a value was so selected
such that it fairly meets all the desired
requirements.

NOTE: Gain and Bandwidth together determine

the Frequency Response of the amplifier. Also,
the Gain-Bandwidth product always remains
constant. This implies that as gain increases, the
bandwidth decreases, and vice-versa.
Fig. 2 Gain of the op-amp

BANDWIDTH: Specification is > 1GHz.

Bandwidth represents the band or range of

frequencies that the amplifier is most effective
in amplifying.
First Pole: It is due to the capacitive loading of
the first stage by the second.
Second Pole: It is due to the capacitance of the
output node of the second stage.
Compensation Capacitor: It depends upon the
transconductance of the differential pair and the
gain bandwidth product.

C1=(gM NM0,NM1/2*pi*Gain-BW product) (8)

Factors affecting Bandwidth:

1) Compensation Capacitance: This

capacitance helps in pole splitting, thereby
shifting the low frequency pole to the left
side and high frequency pole to the right
side, thereby, increasing the bandwidth.
Larger is this value, larger is the bandwidth.
But, it cannot be increased beyond a certain Fig. 3 Bandwidth of the op-amp
VOLTAGE SWING: Specification is > 1V Factors affecting Phase Margin:

Output Voltage Swing is defined as the range of 1) Compensation Capacitance: Phase Margin
output voltages for which all the transistors has an inverse relation with the
operate in the active region so that the gain compensation capacitance. Decreasing the
calculated is approximately constant. capacitance value increases the phase
margin.
VovNM2 < Vo < VDD – |VovPM3| (9) 2) Series Resistance used along with the
compensation capacitor: This resistor when
Factors affecting the Output Voltage Swing: used in conjunction with the compensation
capacitance tries to optimize both the phase
1) Both VovNM2 and VovPM3 should be small margin and the bandwidth of the operational
numbers, such that a lot of range is provided amplifier.
for the output voltage swing.
2) Also, VgsNM2 and VgsPM3 should be small so NOTE: Because both these components
that overdrive voltages are small in number. work together, they can either optimize
bandwidth or phase margin. Both these
specifications cannot be met simultaneously.
Hence, there is a trade-off between the two.

Fig. 4 Output Voltage swing of the op-amp

Fig. 5 Phase Margin of the op-amp

PHASE MARGIN: Specification is > 800

Phase Margin is the difference in degrees

between the phase of the amplifier output signal SLEW RATE: Specification is > 0.5 * 109V/sec
and -1800. The phase margin is measured at the
frequency at which open loop voltage gain and Slew rate represents the maximum rate of
the closed loop gain of the amplifier are equal. change of a signal at any point in a circuit. It
helps to identify the maximum input frequency
applicable to the amplifier such that the output is
not distorted. In general,
Slew rate = ISAT, NM1 / Av2 * C1 (10)

Where, ISAT, NM1 is the saturation output current

of the first stage, Av2 is the gain of the second
stage, C1 is the compensation capacitor.

There are two types of slew rate for a two stage

op-amp:

(a) Internal Slew Rate: The slew rate as

calculated on the output node of the
differential pair is called the internal slew
rate.
SR(int) = (2 * IdsNM1) / C1 (11)

(b) External Slew Rate: The slew rate as

calculated on the output node of the second
stage of the amplifier is called the external Fig. 6 Slew Rate of the Op-amp
slew rate.
SR(ext) = Ids NM2 – (2 * IDS NM1) / C0 (12)

Slew Rate performance depends both upon the POWER DISSIPATION: Specification is <
internal and external slew rates. In order to 3mW
satisfy the requirement, both the internal and
external slew rates should not be set lower than In case of MOSFETs, Power Dissipation is
the target Slew Rate value. basically comprised of Resistive Losses and
Switching Losses.

Factors affecting Slew Rate: Factors affecting Power Dissipation:

1) Compensation Capacitor: Smaller is the 1) Resistive Losses: These losses come into
value of the compensation capacitor, C 1, picture whenever the MOSFET is ON, i.e. in
larger is the slew rate. But, this value cannot the active/saturation region. The Source to
be decreased beyond a certain limit, as it Drain resistance is very high (almost
will affect our second pole, and hence, the infinite) in this case. Hence, to reduce the
bandwidth (as has been seen in the previous losses, current value flowing through the
section). transistor should be decreased.
2) Output Saturation Current: It depends upon 2) Switching Losses: Switching Loss is
the output saturation current of the first difficult because it depends upon many
stage. If we increase the current, that is difficult to quantify and typically
beneficial for the slew rate, but, not for the unspecified factors that influence both turn-
overdrive voltages, as the current increases on and turn-off.
the VGS. PD = (CRSS * VIN2 * fSW * ILOAD)/IGATE (13)

where, CRSS is the MOSFETs reverse

transfer capacitance, fSW is the switching
frequency, IGATE is the MOSFETs gate
 driver’s sink and source current at the 1) Compensation Capacitor: Settling Time has
MOSFET’s Turn on threshold. a direct relationship with the capacitor
value. By reducing the value of the
Calculation of Power Dissipation: capacitor, the settling time reduces and the
Current = 2.92701mA slew rate increases.
rms value of current = 2.92701 / 1.414 2) Small Series Resistance used along with the
= 2.07 mA compensation capacitor: This resistor has a
Power = V * I (14) very small value otherwise. But, when its
Power = 2.07 * 1.2 = 2.484mW value was increased to a larger value, then, it
The value so obtained meets the desired adversely affected the settling time and
specifications. hence the slew rate.

SETTLING TIME: Specification is < 2 nS

IV. TEST BENCHES
Settling time of an amplifier is the time elapsed
from the application of ideal instantaneous step Two Test benches have been used for this
input to the time at which the amplifier output project. One test bench is used to simulate all the
has entered and remained within a specified parameters such as Gain, Bandwidth, Phase
error band, usually symmetrical about the final margin, Power Dissipation, and Output Voltage
value. Swing.
Second test bench has been employed to
simulate the Slew Rate and Settling Time.

FIRST TEST BENCH

A common mode voltage has been applied to

both the inputs of the differential amplifier in
order to bias the two transistors in the
differential pair. Also, a differential voltage has
been applied between the two inputs. The final
output is obtained from the output of the second
stage, i.e. the common source amplifier stage.
DC analyses was performed to calculate the DC
operating points of all the transistors in the
circuit. With the help of these points, we could
have a fair estimate of which transistors were in
active / cut-off / linear region. And based upon
the information so obtained, we could start our
work from thereon. Then, the plots for gain,
bandwidth, and phase margin have been
obtained by performing the AC analyses, with
the variables to be plotted as VOUT (final output
voltage) and VIP. Also, the transient analyses
Fig. 7 Settling Time of the op-amp have been performed to get the output voltage
swing. In that case too, the parameters so
selected are VOUT and VIP.
Factors affecting Settling Time:
 Fig. 8 First Test bench used for simulation Fig. 9 Second Test bench used for simulation

SECOND TEST BENCH

V. VALUES OF VARIOUS
The output is connected back to the inverting PARAMETERS OF THE
input, in such a way so as to form the unity gain TRANSISTORS USED IN THE
configuration. This test bench has been designed DESIGN
in a way to observe the output response of an
instantaneous step signal. The time that is taken Gate- Drain- Trans-
by the signal to achieve about 99.99% of its final Source Source Condu-
value (which is 1V in this case), is called as the Voltage Voltage ctance
Settling Time, or more specifically, 0.1% (VGS) (VDS) (gM)
Settling Time. The time that is taken by the (in mV) (in mV) (in
output to rise from 10% of the final value to mA/V)
90% of the final value determines the slew rate. PM0 304.124 572.647 5.605
It determines how fast the signal rises. Hence, a PM1 304.124 572.462 5.605
large value of slew rate is desired. PM2 478.505 295.876 4.92565
PM3 498.505 779.39 8.359
PM4 498.509 498.509 5.9883
NM0 331.343 331.343 4.426
NM1 331.343 331.323 4.426
NM2 331.323 420.266 19.05
Table – 1
 Drain- Width Length much higher order. Also, the implementation
Source (W) (L) was tough because the values of parameters
Current ( in µm) (in nm) might reinforce one characteristic, but, they may
(IDS) degrade the other characteristic at the same time.
(in µA)
PM0 322.305 220 400 Finally, the Single Ended Two stage op-amp has
PM1 321.305 220 400 been designed for the given specifications. The
PM2 644.554 28 150 value of gain and bandwidth so achieved are
PM3 1439.8 90 380 fairly above the range thereby meeting the
PM4 779.394 25 120 requirements. Also, the output voltage swing
NM0 322.3 40 300 requirement was met. The slew rate and settling
NM1 331.3 40 300 time requirements have been met too. The phase
NM2 1439.8 190.015 350 margin requirement was a little difficult to meet
Table – 2 because improving the phase margin badly
affected the bandwidth requirement.

RBIAS = 900 ohms

R1 = 195 ohms VIII. REFERENCES

C1 = 900 fF [1] Analysis and Design of analog

Integrated Circuits, by P Gray, Hurst, Lewis,
C0 = 1pF Meyer, 4th Edition.
[2] Design of Analog CMOS Integrated
Circuits, by B. Razavi.
[3] Analog Integrated Circuit Design, by
VI. RESULTS Davis Johns and Ken Martin
[4] www.electronicdesign.com
[5] MOS OP AMP DESIGN: A Tutorial,
www.lyle.smu.edu
Gain 62.7 dB
[6] Design procedure of Two stage CMOS
Bandwidth 1.22 GHz
Transconductance Operational Amplifier: A
Voltage Swing 1.15 V
Tutorial, by G. Palmisano, G. palumbo, S.
Power Dissipation 2.484 mW
Pennisi
Slew Rate 0.515 * 109 V/sec
Settling Time 2.24 sec
Phase Margin 280

VII. CONCLUSION

The design of this project involved the

implementation of the entire knowledge that we
have accumulated during the study of this
course. The theoretical postulates sometimes
were not applicable during the practical
implementation, only because we have studied
the parameter behaviour up to first or maybe
second order, while CADENCE makes use of