Introduction To Embedded System Design: © Lothar Thiele ETH Zurich, Switzerland
Introduction To Embedded System Design: © Lothar Thiele ETH Zurich, Switzerland
© Lothar Thiele
ETH Zurich, Switzerland
3. Real-Time Scheduling
5. Performance Analysis
Examples:
external process
human interface
sensors, actuators
embedded system
ABS
motor control
climate control
Swiss Federal Computer Engineering
Institute of Technology 1-6 and Networks Laboratory
Examples of Embedded Systems
Consumer electronics, for example MP3 Audio, digital camera, home
electronics, … .
user interface
processor
sensors
actuators
Swiss Federal Computer Engineering
Institute of Technology 1-7 and Networks Laboratory
Examples of Embedded Systems
Production systems
Sensor
Actuator
this course
actuators
embedded system
Swiss Federal Computer Engineering
Institute of Technology 1 - 19 and Networks Laboratory
Typical Architecture
To Outside World
Peripheral Bus
DEBUG Port
Non-volatile memory Custom Devices
• EPROM, FLASH, DISK • ASIC
• Hybrid • FPGA
• PAL
Microprocessor
• 4, 8, 16, 32, 4 bit bus
• CISC, RISC, DSP
Standard Devices
• Integrated peripherals Volatile Memory
• Debug/Test Port • I/O Ports
• DRAM, SRAM • Peripheral Controllers
• Caches
• Hybrid
• Pipeline
• Multiprocessing Systems
Communication Devices
• Ethernet
• RS-232
• SCSI
• Centronics
System Clocks • Proprietary
• RTC circuitry
Software • System clocks
• Application Code • Integrated in uC
• Driver Code / BIOS • Imported/Exported Microprocessor Bus
• Real Time Operating System • Custom
• User Interface • PCI
• Communications Protocol Stacks • VME
• C, C++, Assembly Language, ADA • PC-102
• Legacy Code
General-purpose processors
Programmable hardware
• FPGA (field-programmable gate arrays)
(de)compressor
+
4 additions per instruction;
carry disabled at word
boundaries.
Swiss Federal Computer Engineering
Institute of Technology 1 - 27 and Networks Laboratory
Example: Heterogeneous registers
Example (ADSP 210x):
P
D
AX AY MX MY
Address- AF MF
registers
A0, A1, A2 ..
+,-,..
*
Address
AR
+,-
generation
unit (AGU) MR
AX AY MX MY
Address- AF MF
registers
A0, A1, A2 ..
+,-,..
*
Address
AR
+,-
generation
unit (AGU) MR
.. ..
n most x[t1-1] x[t1-1]
x[t1] x[t1]
recent x[t1-n+1] x[t1+1]
values x[t1-n+2] x[t1-n+2]
.. ..
I/O
signals
output
signals
output
signals
B f1 B f2 B f3 B
B: buffer
B f2
zero-overhead loop
(repeat next instruction N times)
LDF 0, R0
LDF 0, R1
RPTS N
MAC - Instruktion MPYF3 *(AR0)++, *(AR1)++, R0
|| ADDF3 R0, R1, R1
TMS320C3x Assembler
(Texas Instruments)
Key
Keyidea:
idea:detection
detectionof
ofpossible
possibleparallelism
parallelismto
tobebedone
doneby
by
compiler,
compiler,not
notby
byhardware
hardwareat
atrun-time
run-time(inefficient).
(inefficient).
VLIW:
VLIW:parallel
paralleloperations
operations(instructions)
(instructions)encoded
encodedininone
onelong
long
word
word(instruction
(instructionpacket),
packet),each
eachinstruction
instructioncontrolling
controllingone
one
functional
functionalunit.
unit.E.g.:
E.g.:
Main Memory
Interface
Huffman decoder
CCIR601/656 Slice-at-a-time
VLD
YUV 4:2:2 Video In MPEG-1 & 2
Coprocessor
38 MHz (19 Mpix/sec)
Communication network:
! Crossbar, hierarchical mesh, tree
Reconfiguration:
! fixed at production time, once at design time, dynamic during
run-time
[NTNU]