STP9NK50Z - STP9NK50ZFP

STB9NK50Z - STB9NK50Z-1
N-CHANNEL 500V - 0.72Ω - 7.2A TO-220/FP/D2PAK/I2PAK
Zener-Protected SuperMESH™ MOSFET

TYPE VDSS RDS(on) ID Pw

STP9NK50Z 500 V < 0.85 Ω 7.2 A 110 W
STP9NK50ZFP 500 V < 0.85 Ω 7.2 A 30 W
STB9NK50Z 500 V < 0.85 Ω 7.2 A 110 W
STB9NK50Z-1 500 V < 0.85 Ω 7.2 A 110 W
3
TYPICAL RDS(on) = 0.72 Ω
2
■ 1

■ EXTREMELY HIGH dv/dt CAPABILITY TO-220FP

TO-220
■ 100% AVALANCHE TESTED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
3
REPEATIBILITY 1 3
12
D2PAK I2PAK

DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established strip- INTERNAL SCHEMATIC DIAGRAM
based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is tak-
en to ensure a very good dv/dt capability for the
most demanding applications. Such series comple-
ments ST full range of high voltage MOSFETs in-
cluding revolutionary MDmesh™ products.

APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING

■ IDEAL FOR OFF-LINE POWER SUPPLIES,

ADAPTORS AND PFC

■ LIGHTING

ORDERING INFORMATION
SALES TYPE MARKING PACKAGE PACKAGING
STP9NK50Z P9NK50Z TO-220 TUBE
STP9NK50ZFP P9NK50ZFP TO-220FP TUBE

STB9NK50ZT4 B9NK50Z D2PAK TAPE & REEL

STB9NK50Z-1 B9NK50Z I2PAK TUBE

June 2004 1/13

STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
STP9NK50Z
STB9NK50Z STP9NK50ZFP
STB9NK50Z-1
VDS Drain-source Voltage (VGS = 0) 500 V
VDGR Drain-gate Voltage (RGS = 20 kΩ) 500 V
VGS Gate- source Voltage ± 30 V
ID Drain Current (continuous) at TC = 25°C 7.2 7.2 (*) A
ID Drain Current (continuous) at TC = 100°C 4.5 4.5 (*) A
IDM (
) Drain Current (pulsed) 28.8 28.8 (*) A
PTOT Total Dissipation at TC = 25°C 110 30 W
Derating Factor 0.88 0.24 W/°C
VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) 3500 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
VISO Insulation Withstand Voltage (DC) - 2500 V
Tj Operating Junction Temperature -55 to 150 °C
Tstg Storage Temperature -55 to 150 °C
(
) Pulse width limited by safe operating area
(1) ISD ≤7.2A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.
(*) Limited only by maximum temperature allowed

THERMAL DATA
TO-220 / D2PAK /
TO-220FP
I2PAK
Rthj-case Thermal Resistance Junction-case Max 1.14 4.2 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
Tl Maximum Lead Temperature For Soldering Purpose 300 °C

AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive 7.2 A
(pulse width limited by Tj max)
EAS Single Pulse Avalanche Energy 190 mJ
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

GATE-SOURCE ZENER DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit
BVGSO Gate-Source Breakdown Igs=± 1mA (Open Drain) 30 V
Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to souce. In this respect the Zener voltage is appropriate to achieve an efficient and cost-
effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage
of external components.

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ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

ON/OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source ID = 1 mA, VGS = 0 500 V
Breakdown Voltage
IDSS Zero Gate Voltage VDS = Max Rating 1 µA
Drain Current (VGS = 0) VDS = Max Rating, TC = 125 °C 50 µA
IGSS Gate-body Leakage VGS = ± 20V ±10 µA
Current (VDS = 0)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 100µA 3 3.75 4.5 V
RDS(on) Static Drain-source On VGS = 10V, ID = 3.6 A 0.72 0.85 Ω
Resistance

DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (1) Forward Transconductance VDS = 15 V, ID = 3.6 A 5.3 S
Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 910 pF
Coss Output Capacitance 125 pF
Crss Reverse Transfer 30 pF
Capacitance
Coss eq. (3) Equivalent Output VGS = 0V, VDS = 0V to 400V 75 pF
Capacitance
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) Turn-on Delay Time VDD = 250 V, ID = 3.6 A 17 ns
tr Rise Time RG = 4.7Ω VGS = 10 V 20 ns
(Resistive Load see, Figure 3)
Qg Total Gate Charge VDD = 400V, ID = 7.2 A, 32 nC
Qgs Gate-Source Charge VGS = 10V 6 nC
Qgd Gate-Drain Charge 18 nC

SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(off) Turn-off Delay Time VDD = 250 V, ID = 3.6 A 45 ns
tf Fall Time RG = 4.7Ω VGS = 10 V 22 ns
(Resistive Load see, Figure 3)
tr(Voff) Off-voltage Rise Time VDD = 400V, ID = 7.2 A, 15 ns
tf Fall Time RG = 4.7Ω, VGS = 10V 13 ns
tc Cross-over Time (Inductive Load see, Figure 5) 30 ns

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 7.2 A
ISDM (2) Source-drain Current (pulsed) 28.8 A
VSD (1) Forward On Voltage ISD = 7.2 A, VGS = 0 1.6 V
trr Reverse Recovery Time ISD = 7.2 A, di/dt = 100A/µs 238 ns
Qrr Reverse Recovery Charge VDD = 40 V, Tj = 150°C 1.5 µC
IRRM Reverse Recovery Current (see test circuit, Figure 5) 12.6 A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80%
VDSS.

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STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

Safe Operating Area For TO-220/D2PAK/I2PAK Thermal Impedance For TO-220/D2PAK/I2PAK

Safe Operating Area For TO-220FP Thermal Impedance For TO-220FP

Output Characteristics Transfer Characteristics

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 STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

Transconductance Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage Capacitance Variations

Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature

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STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature

Maximum Avalanche Energy vs Temperature

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 STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuit For Fig. 4: Gate Charge test Circuit
Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching

And Diode Recovery Times

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STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

TO-220 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
E
A

D
C

D1

L2
F1

G1

H2
G

Dia.
F
F2

L5
L9
L7
L6 L4
P011C

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 STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

TO-220FP MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.5 0.045 0.067
F2 1.15 1.5 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 .0385 0.417
L5 2.9 3.6 0.114 0.141
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126

E
A

D
B

L3
L6
L7
F1

G1

G
H

F2

1 2 3
L5
L2 L4

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STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

D2PAK MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.

A 4.4 4.6 0.173 0.181

A1 2.49 2.69 0.098 0.106

A2 0.03 0.23 0.001 0.009

B 0.7 0.93 0.027 0.036

B2 1.14 1.7 0.044 0.067

C 0.45 0.6 0.017 0.023

C2 1.23 1.36 0.048 0.053

D 8.95 9.35 0.352 0.368

D1 8 0.315

E 10 10.4 0.393

E1 8.5 0.334

G 4.88 5.28 0.192 0.208

L 15 15.85 0.590 0.625

L2 1.27 1.4 0.050 0.055

L3 1.4 1.75 0.055 0.068

M 2.4 3.2 0.094 0.126

R 0.4 0.015

V2 0º 8º
3

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1
 STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

TO-262 (I2PAK) MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.

A 4.40 4.60 0.173 0.181

A1 2.40 2.72 0.094 0.107

b 0.61 0.88 0.024 0.034

b1 1.14 1.70 0.044 0.066

c 0.49 0.70 0.019 0.027

c2 1.23 1.32 0.048 0.052

D 8.95 9.35 0.352 0.368

e 2.40 2.70 0.094 0.106

e1 4.95 5.15 0.194 0.202

E 10 10.40 0.393 0.410

L 13 14 0.511 0.551

L1 3.50 3.93 0.137 0.154

L2 1.27 1.40 0.050 0.055

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STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1
2
D PAK FOOTPRINT TUBE SHIPMENT (no suffix)*

TAPE AND REEL SHIPMENT (suffix ”T4”)*

REEL MECHANICAL DATA

mm inch
DIM.
MIN. MAX. MIN. MAX.
A 330 12.992
B 1.5 0.059
C 12.8 13.2 0.504 0.520
D 20.2 0795
G 24.4 26.4 0.960 1.039
N 100 3.937
T 30.4 1.197

BASE QTY BULK QTY

TAPE MECHANICAL DATA
1000 1000
mm inch
DIM.
MIN. MAX. MIN. MAX.
A0 10.5 10.7 0.413 0.421
B0 15.7 15.9 0.618 0.626
D 1.5 1.6 0.059 0.063
D1 1.59 1.61 0.062 0.063
E 1.65 1.85 0.065 0.073
F 11.4 11.6 0.449 0.456
K0 4.8 5.0 0.189 0.197
P0 3.9 4.1 0.153 0.161
P1 11.9 12.1 0.468 0.476
P2 1.9 2.1 0.075 0.082
R 50 1.574
T 0.25 0.35 0.0098 0.0137
W 23.7 24.3 0.933 0.956
* on sales type
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 STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners

© 2004 STMicroelectronics - All Rights Reserved

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