MBSD PDF .
2 NOTES
INTRODUCTION TO AMBA:
AMBA ( Advanced Microcontroller Bus Architecture ) is an architecture of buses for
microcontrollers. It includes different types of buses for different purposes.
The buses included in AMBA architecture are :
● AHB
● APB
Etc ( see names from slides )
We will discuss AHB in detail.
INTRODUCTION TO AHB
AHB ( Advanced High Performance Bus ) is a type of bus interface included in AMBA bus
architecture.
It is designed for connecting devices with high bandwidth. ( those devices which have high
speed of data transfer )
AHB mostly connects master ( processor ) with memory units.
FEATURES OF AHB5
AHB has following features:
● Burst Transfer :
It supports burst transfers ( descirebd below )
● Single Clock Edge Triggered:
It works on single clock edge i.e it is either positive edge triggered or negative edge
triggered.
( Some buses operate on both edges of a cycle , AHB doesn;t do this )
● Non Tristate Implementation:
It is follows on non-tristate implementation. I.e when some logic is required for
selecting any target device, a tristate buffer is not used. Instead a MUX is used.
● Wide Sizes For Databus :
It supports different wide sizes for data transfer . 64, 128, 256, 512, 1024 bits all
supported
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❏ WHAT IS TRISTATE BUFFER:
a Tri-state buffer is a device which gives an output (which is same as its input) only
when the input to the Enable, ( EN ) pin is HIGH. If EN is low, there is no output (
high impedance, no connection )
❏ WHAT ARE BURST OPERATIONS
● Burst transfer means that you provide address for one location only and you get
data for multiple consecutive locations instead of just one location
● Burst transfer is for data transfers from multiple contiguous/consecutive locations
● Burst transfer increases the speed of data transmission
● Individual transfers for multiple contiguous locations would take more time as
compared to burst transfers therefore burst transfers are helpful in reading/writing
caches because
● Burst transfers cannot occur between two 1KB blocks ( i.e all the data in a burst
transfer must be from teh same 1 KB block )
● Two types of burst transfers are :
○ Incremental bursts : Address for next transfer is simply calculated by
incrementing in previous address i.e all addresses are accessed
sequentially.
○ Wrap Bursts : Memory access is not sequential beacuse they wrap
around towards some previous address locations after crossing the
particular boundary. ( calculation of boundary address discussed later )
ARCHITECTURE OF AHB5
AHB5 architecture consists of three components:
1. Master
2. Slave
3. Interconnect
● Master:
Master is the one that initiates data transfer. There can be multiple masters as well.
● Slave
Slave means the target device i.e the device that responds to data transfer. There
can be multiple transfers as well.
● Interconnect
Interconnect is the connection between masters and slaves. It is designed for
connecting the correct master will the correct slave.
Interconnect consist of following 2 components:
1. Decoder : For selecting the target slave, and selecting the mux input line
2. Multiplexer master : For selecting that which slave’s output lines to be
connected to the master.( i.e which slave’s data and control signals to be
transferred to the master )
SIGNALS IN AHB5
Master, slave and interconnect, all three have their own signals for carrying out their task:
● Master
1. Data signals ( for slave )
2. addr signals( for slave and decoder )
3. control signals ( multiple targets, later discussed)
● Slave
1. Data signals ( for mux)
2. Transfer response signals ( for mux)
● Interconnect :
○ Decoder :
1. slave select signal
2. mux select signal
○ Mux :
1. data signals ( to master )
2. some transfer responses ( to master n slave )
SIGNALS FOR MASTER
SIGNAL DESCRIPTION
HADDR It is the address of memory location to access
HWRITE Control SIgnal : If low -> read operation If high -> write operation
HWDATA It is the data to be written in mem in case of write operation
HBURST Control signal : It tells the type of burst operation ( further discussed
below )
HSIZE It tells the size of data transfer. In case of burst operation, each data
transfer will be of this same HSIZE ( further discussed below )
HTRANS It tells the type of data transfer ( further discussed below )
HMASTLOCK It tells that the data transfer is a locked data access or not ( further
discussed below )
HPROT[3:0] These are the protection control signals for memory ( discussed later
in details )
HPROT[6:4] These are also the protection control signals for memory but applicable
only when Extended Memory Types feature for AHB5 is true
( discussed later in details )
HNONSEC Tells the current transfer is secure or non secure transfer.
Applicable when Secure Transfer feature of AHB5 is true
The following 2 master signals are supported when Exclusive Transfer feature of AHB5 is
true.This means that Exclusive Access / Transfer is allowed.
HEXCL Indicates that the transfer is part of an Exclusive access sequence.
HMASTER A master that has multiple Exclusive capable threads must generate
this signal to differentiate between the threads.
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❏ WHAT ARE EXCLUSIVE TRANSFERS/ACCESSES :
Exclusive accesses are a sequence of read transactions followed by write transactions to the
same address range. I.e first a read operation is performed and then a write operation is
performed at the same address.
❏ WHAT IS EXCLUSIVE ACCESS MONITOR :
An Exclusive Access Monitor is required to support Exclusive Access Sequence and this
monitor must determine if an Exclusive Write transfer succeeds or fails.
❏ HBURST SIGNAL
It tells whether the transfer is :
● A single transfer ( no burst )
● An incremental burst ( can be of defined
length or undefined length)
● A wrap burst ( defined length only)
Burst of defined length can be of 4, 8 or 16 beats.
( Beat specifies the number of transfers and the size of each transfer is described by HSIZE
)
❏ HSIZE SIGNAL
The transfer size set by HSIZE must be less than or
equal to the width of the data bus.
NOTE :
HSIZE and HBURST are used to calculate the
boundary address in wrap burst
❏ HTRANS SIGNAL
It defines the type of transfer which can be of 4 types:
1. IDLE :
In this type, no data transfer occurs. The bus remains idle.
2. BUSY :
In this type, no data transfer takes place, the bus is idle but the master doesn’t let go
of teh bus control.
It is used in between a burst operation when no transfer is taking place during any
cycle of the operation.
3. SEQ:
All except the first transfer in a burst operation are labelled as SEQ.
4. NONSEQ :
A single data transfer is termed as a SEQ type. Also the first transfer of every burst
operation is labelled as SEQ type
❏ HMASTLOC SIGNAL
This signal indicates to any slave that the current transfer sequence is a part of a locked
sequence. It is indivisible ( cannot be broken down ) and must therefore be processed
before any other transfers are processed.
It means that any other transfer should not start before this locked transfer is done.
More on exclusive transfers( extra ):
SIGNALS FOR SLAVE
SIGNAL DESCRIPTION
HDATA The data fetched from slave / memory
HREADYOUT Tells whether the data transfer has completed or in progress
Completed -> 1 Inprocess -> 0
When its low, then the data transfer is extended to more cycles.
HRESP Tells teh status of transfer.
When LOW, the transfer status is OKAY.
When HIGH, the transfer status is ERROR.
HEXOKAY Tells teh status of transfer for Exclusive Transfers / Access.
SIGNALS FOR DECODER
SIGNAL DESCRIPTION
HSELx This is the decoder output line which selects the target slave.
For example, consider there are 4 slaves and decoder output lines
are labelled as HSEL_s1, HSEL_s2, HSEL_s3 and HSEL_s4.
Now if HSEL_s2 gets high, it means 2nd slave is connected
( selected ).
SIGNALS FOR MULTIPLEXER
All the output lines of each slave is connected to the multiplexer. The mux decides that which
slaves output should be forwarded to the master.
It does this selection with the help of slave select signal provided by decoder
Hence signals for multiplexer are same as the output of slave.
SIGNAL DESCRIPTION
HRDATA Data from selected slave
HRESP Response signal from selected slave ( tells whether the transfer is
completed or in process )
HEXOKAY Exclusive okay signal from teh selected slave that tells about success
or failure of exclusive transfer
HREADY This signals is for master as well as for all the slaves. It tells them
whether the previous transfer is in process or completed.
This signal is basically the HREADYOUT of the selected slave.
DATA TRANSFERS EXPLANATION:
Pipelined Data Transfers:
Data transfers with AHB are pipelined. There are two stages:
1. Address Phase:
It is always of 1 cycle. It doesn’t require more than 1 cycle.
( however, it may get extended unnecessarily due to extension in data phase )
In this phase, the control signals and memory address are provided.
NOTE : The HWRITE control signal for a transfer must be stable during the address
phase of that transfer. During data phase, it is a don care for that transfer.
2. Data Phase:
It can be of 1 or more cycle i.e It may require multiple cycles.
In this phase, data read/ write occurs.
SIMPLE READ TRANSFER
● 1st cycle is address phase. The HADDR and HWRITE signals are provided in this
cycle.
These two signals are sampled at the end of address phase i.e on the positive edge of next
cycle.
To sample the signals means to read the value of signals. This is done only on the active
adge of the clock. Provided that HREADY is HIGH. If HREADY is low, then nothing is
sampled.
● 2nd cycle is the data cycle during which data transfer occurs. It is a read transfer (
HWRITE is low ). In this cycle data is fetched from the memory and it gets available
on the HRDATA line at the end of this cycle.
SIMPLE WRITE TRANSFER
● Memory address is made available by the end of address phase. Write signal
is also provided in this phase
● Data write starts to occur in data phase and is completed by the end of data
phase.
In both of the above transfers, the data phase for addressA is also the address
phase of addressB
WAIT STATE
When teh slave is unable to complete transfer in a cycle, then it requires more cycles
to complete the transfer. These extra cycles are called Wait States. During this, teh
HREADY signals is low which tells that
● Its a wait state
● Current data transfer is still in process
● Cannot sample any signal during this wait cycle;
● Current transfer is extended
In above transfer, the data phase is not completed in one cycle. Instead it inserts a
wait state and the data phase for A is extended to 2 cycles due to which , the
address phase of next transfer i.e B is also extended to 2 cycles which is not
required by B. ( But no other option )
MULTIPLE TRANSFER
The above fig shows data transfers for 3 locations A, B and C
T0 - T1 : address phase of A, for write operation
T1 - t2 : data phase of A, address phase of B, for read operation
T2 - t3: data phase for B with a wait state, address phase for C, write operation
T3 - t4 : another cycle for dataphase of B due to wait state in last cycle. Likewise,
address phase of C is also extended. Data phase for B completed in this cycle
T4 - t5 : data phase of C is completed in this cycle.
INCREMENT BURST OF UNDEFINED LENGTH
HBURST signal tells that it is a burst operation of undefined length ( INCR ) i.e no.of
beats is not defined.
HWRITE signal tells that it is a read operation for the complete burst transfer i.e
every data transfer in this burst operation is a read access
NOTE : HSIZE not mentioned here but it is equal to WORD here since difference in
address is 4 which means 4 bytes transferred in each transfer.
Since it is incremental burst, all addresses are sequential and calculated as follows:
Previous address + HSIZE ( bytes )
Addr 1 = 0x20 ( given )
Addr 2 = 0x20 + 4 = 0x24
Addr 3 = 0x24 + 4 = 0x28
WRAP 4 BURST
Since its a wrap4 hence it has 4 beats i.e 4 data transfers.
The first transfer is labelled as NON SEQ since frst transfer is always NONSEQ in
every burst transfer.
The HSIZE signal tells the size of each transfer i.e word = 4 bytes
Control signals of HWRITE, HSIZE, HBURST which define the transfer type, remain
constant through out the transfer.
There is only one wait state i.e t1 - t2 which is the data phase of 0x38. Due to this,
address phase of next transfer i.e 0x3C is also extended.
Here note that 1st address is 0x38 and 2nd address is 0x3C( 0x38 + 4 ) but after that
data transfer occurs from previous locations i.e it wraps around after 0x3C.
INCREMENT 4 BURST
This is a 3 beat incremental burst read transfer.
It includes 4 data transfers, each of 4 bytes ( a word ). All the addresses are
sequential i.e obtained by adding 4 to previous address.
Also, there is a wait state from t1 - t2 to extend the data phase of 0x38 which in
return also extends the address phase of 0x3C.
UNDEFINED LENGTH BURST
This is a incremental burst transfer of undefined length.
Basically this figure shows two different incremental burst transfers of undefined length;
1st Burst Transfer : t0 - t3
The HBURST signal tells that it an undefined length incr burst of write operation.
HSIZE tells that 2 bytes ( half word ) will be transferred in each transfer.
2nd Burst Transfer : t3 - t7
The HBURST signal tells that it an undefined length incr burst of read operation.
HSIZE tells that 4 bytes ( one word ) will be transferred in each transfer.
Also, there is a wait state during the data phase if address 0x5C which in return extends teh
address phase of 0x60.
