Scribd
Upload
426 views

Verilog 4 To 1 Multiplexer/Mux

A 4 to 1 multiplexer (or mux) allows one of four input signals (a, b, c, d) to pass to the output based on a 2-bit select signal (sel). It can be implemented in Verilog using either an assign statement or case statement. Both methods produce the same hardware - a mux circuit that connects the selected input to the output based on the value of sel. A testbench is used to simulate and verify the mux design by applying random input patterns and changing the sel value over time.

Uploaded by

Harun
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
426 views

Verilog 4 To 1 Multiplexer/Mux

A 4 to 1 multiplexer (or mux) allows one of four input signals (a, b, c, d) to pass to the output based on a 2-bit select signal (sel). It can be implemented in Verilog using either an assign statement or case statement. Both methods produce the same hardware - a mux circuit that connects the selected input to the output based on the value of sel. A testbench is used to simulate and verify the mux design by applying random input patterns and changing the sel value over time.

Uploaded by

Harun
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

(/)

Verilog 4 to 1 Multiplexer/Mux

What is a mux or multiplexer ?

A multiplexer or mux in short, is a digital element that


transfers data from one of the N inputs to the output based on
the select signal. The case shown below is when N equals 4.
For example, a 4 bit multiplexer would have N inputs each of
4 bits where each input can be transferred to the output by
the use of a select signal.

(/images/verilog/4x1_mux.png)
sel is a 2-bit input and can have four values. Each value on

the select line will allow one of the inputs to be sent to output
pin out .

sel a b c d out

0 3 7 1 9 3

1 3 7 1 9 7

2 3 7 1 9 1

3 3 7 1 9 9

A 4x1 multiplexer can be implemented in multiple ways and


here you'll see two of the most common ways:

Using an assign statement


Using a case statement

Using assign statement

1 module mux_4to1_assign ( input [3:0] a,


2 input [3:0] b,
3 input [3:0] c,
4 input [3:0] d,
5 input [1:0] sel,
6 output [3:0] out);
7

8 // When sel[1] is 0, (sel[0]? b:a) is selected


9 // When sel[0] is 0, a is sent to output, else
10 assign out = sel[1] ? (sel[0] ? d : c) : (sel[
11

12 endmodule

The module called mux_4x1_assign has four 4-bit data inputs,


one 2-bit select input and one 4-bit data output. The
multiplexer will select either a , b , c , or d based on the

select signal sel using the assign statement.


(/images/verilog/waves/4x1-mux-wave.PNG)

Using case statement

Note that the signal out is declared as a reg type because

it is used in a procedural block like always .

1 module mux_4to1_case ( input [3:0] a,


2 input [3:0] b,
3 input [3:0] c,
4 input [3:0] d,
5 input [1:0] sel,
6 output reg [3:0] out);
7

8 // This always block gets executed whenever a/


9 // When that happens, based on value in sel, o
10 always @ (a or b or c or d or sel) begin

11 case (sel)

12 2'b00 : out <= a;

13 2'b01 : out <= b;

14 2'b10 : out <= c;

15 2'b11 : out <= d;

16 endcase

17 end

18 endmodule

The module called mux_4x1_case has four 4-bit data inputs,


one 2-bit select input and one 4-bit data output. The
multiplexer will select either a , b , c , or d based on the

select signal sel using the case statement.

Hardware Schematic

Both types of multiplexer models get synthesized into the


same hardware as shown in the image below.
(/images/verilog/schematic/4x1_mux_schematic.png)

Testbench
1 module tb_4to1_mux;

3 // Declare internal reg variables to drive des


4 // Declare wire signals to collect design outp
5 // Declare other internal variables used in te
6 reg [3:0] a;

7 reg [3:0] b;

8 reg [3:0] c;

9 reg [3:0] d;

10 wire [3:0] out;

11 reg [1:0] sel;

12 integer i;

13

14 // Instantiate one of the designs, in this cas


15 // Connect testbench variables declared above
16 mux_4to1_case mux0 ( .a (a),

17 .b (b),

18 .c (c),

19 .d (d),

20 .sel (sel),

21 .out (out));

22

23 // This initial block is the stimulus

24 initial begin

25 // Launch a monitor in background to displa


26 $monitor ("[%0t] sel=0x%0h a=0x%0h b=0x%0h
27

28 // 1. At time 0, drive random values to a/b


29 sel <= 0;

30 a <= $random;

31 b <= $random;

32 c <= $random;

33 d <= $random;

34

35 // 2. Change the value of sel after every 5


36 for (i = 1; i < 4; i=i+1) begin

37 #5 sel <= i;

38 end

39

40 // 3. After Step2 is over, wait for 5ns and


41 #5 $finish;
42 end

43 endmodule

Simulation Log

You might also like