Serial Interfaces

I2C, SPI, I2S

http://www.youtube.com/watch?v=wGt2v54zqAk&feature=relmfu
http://www.youtube.com/watch?v=UJlgND6sWHk&feature=related
https://circuitdigest.com/article/introduction-to-bit-banging-spi-communication-in-arduino-via-bit-banging
 Introduction
I2C & SPI

• Serial communication protocols

• Meant for short distances “inside the box”
• Low complexity
• Low cost
• Low speed (a few Mbps at the fastest )
 What is I2C?

• Shorthand for an “Inter-integrated circuit” bus

• Developed by Philips Semiconductor for TV sets in the 1980’s
• I2C devices include EEPROMs, thermal sensors, real-time
clocks, ADC, I/O ports…
• Used as a control interface to signal processing devices that
have separate data interfaces, e.g. RF tuners, video decoders
and encoders and audio processors.
• I2C bus has three speeds:
– Slow (<100 Kbps)
– Fast (<400 Kbps)
– High-speed (3.4 Mbps) – I2C v.2.0 (Ultra fast – 5MHz)
• Limited to about 10 feet (3m) for moderate speeds
• device count limit: max. capacitance 400 pF
 I2C Bus main features

• 2-wire serial bus: Serial data (SDA) and

Serial clock (SCL)
• Half-duplex, synchronous, multi-master bus
• No chip select or arbitration logic required
• Lines pulled up via resistors or pulled down via open-drain
drivers (wired-AND)
 I2C Bus Configuration

Configurarea Bus-ului I2C

• Fundamentally, the use of pull-ups to set a logic one limits the maximum speed of the bus.
This may be a limiting factor for many applications. This is why the 3.4 Mbps high speed
mode was introduced. Prior to using this mode, the bus master must issue a specific
‘High Speed Master’ code at a lower speed mode.
I2C Protocol
 I2C Protocol

1. Master sends start condition (S) and controls the clock signal
2. Master sends a unique 7-bit slave device address
3. Master sends read/write bit (R/W) – 0 - slave receive,
1 - slave transmit
4. Receiver sends acknowledge bit (ACK)
5. Transmitter (slave or master) transmits 1 byte of data
 I2C Protocol (cont.)

6. Receiver issues an ACK bit for the byte received

7. Repeat 5 and 6 if more bytes need to be transmitted.
8.a) For write transaction (master transmitting), master issues stop
condition (P) after last byte of data.
8.b) For read transaction (master receiving), master does not
acknowledge final byte, just issues stop condition (P) to tell the slave
the transmission is done
 I2C Signals

• Idle state: Both SDA and SCL idle high.

• Start – high-to-low transition of the SDA line while SCL line is high
• Stop – low-to-high transition of the SDA line while SCL line is high
• Ack – receiver pulls SDA low while transmitter allows it to float high
• Data – transition takes place while SCL is low, valid data while SCL is high
 I2C Features
• “Clock stretching” – when the slave (receiver) needs more
time to process a bit, it can pull SCL low. The master waits
until the slave has released SCL before sending the next bit.
• “General call” broadcast – addresses every device on the
bus
• 10-bit extended addressing for new designed chips,
7-bit addresses all exhausted
1
 I2C Features
Advantages:
• Good for communication with on-board devices that are accessed
occasionally
• Easy to link multiple devices because of addressing scheme
• Cost and complexity do not scale up with the number of devices

Disadvantages:
• The complexity of supporting software components can be higher
than that of competing schemes ( for example, SPI ).
 Special Addresses
• general call 0000 000 0
• start byte 0000 000 1
• CBUS address 0000 001 * – used for
cooperation of I2C and CBUS
• High-speed mode master code 0000 1** *
• 10-bit slave addressing 1111 0** *
• In a 10-bit addressing system, two frames are required to transmit the slave
address.
• The first frame will consist of the code b11110xyz, where ‘x’ is the MSB (bit 9) of
the slave address, y is bit 8 of the slave address, and z is the read/write bit as
described above.
• The first frame’s ACK bit will be asserted by all slaves which match the first two bits
xy of the address. As with a normal 7-bit transfer, another transfer begins
immediately, and this transfer contains bits 7:0 of the address. At this point, the
addressed slave should respond with an ACK bit.
If it doesn’t, the failure mode is the same as a 7-bit system.
• Note that 10-bit address devices can coexist with 7-bit address devices, since the
leading ‘11110’ part of the address is not a part of any valid 7-bit addresses.
 Philips I2C Logic Devices

- I2C devices are divided in 10 different classes

- Philips offer > 63 different I2C devices

• Bus Controllers • Temperature Sensors

• I/O Expanders • LED Blinkers
• Serial EEPROMs • DIP Switches
• Multiplexers and Switches • Repeaters/Hubs/Extenders
• 7 Segment Drivers • Analog/Digital Converters
 What is SPI?

• Shorthand for “Serial Peripheral Interface”

• Defined by Motorola on the MC68HCxx line of microcontrollers
• Generally faster than I2C, capable of several Mbps

Applications:
• Like I2C, used in EEPROM, Flash, ADC, real time clocks, …
• Better suited for “data streams”, i.e. ADC converters
• Full duplex capability, i.e. communication between a codec and
digital signal processor (DSP)
 SPI Bus Configuration

• Synchronous serial data link operating, full duplex, single master

• Master/slave relationship
• 2 data signals:
– MOSI – master data output, slave data input
– MISO – master data input, slave data output
• 2 control signals: SCLK – clock
/SS – slave select (no addressing)
 SPI vs. I2C

• For point-to-point, SPI is simple and efficient

– Less overhead than I2C due to lack of addressing, plus SPI is
full duplex.
• For multiple slaves, each slave needs separate slave select signal
– More effort and more hardware than I2C
 SPI Protocol
•SPI interface defines only the communication lines and the clock edge
•There is no specified flow control!
•No acknowledgement mechanism to confirm receipt of data

• 2 parameters: Clock Polarity (CPOL) and Clock Phase (CPHA),

determine the active edge of the clock
• Master and slave must agree parameter pair values in order to
communicate
 SPI Protocol
CPOL CPHA Active edge

0 0 Rising

0 1 Falling

1 0 Falling

1 1 Rising
 SPI Protocol (cont.)

• Hardware implementation is usually done with a simple shift register

 SPI Overview
Advantages of SPI:
- Communication full-duplex
- Significantly higher throughput than I2C
- Flexibility to transfer bits (no limit to the 8-bit words, you can send
messages of any length)
- It interfaces easily
- More efficient in point-to-point communication

Disadvantages SPI:
- Use multiple threads;
- No support for Addressing devices;
- Need one Slave Select signal for each slave
- No flow control and acknowledgment slave (master can "empty
talk“ without knowing).
- Supports only one master
 I2C vs SPI
• Both standards are successfully used for communication with slow peripherals that
are accessed intermittently (EEPROM's and real-time clocks are examples of
devices such).
• SPI is more appropriate than I2C for applications that use data streams (as opposed
to where the read/write various locations in slave device). An example application
that uses data stream is communication between the microprocessor or DSPs (digital
signal processors).
• SPI can achieve significantly higher data rates than I2C (SPI interfaces can operate
at tens of MHz)
• SPI is especially effective in applications that use the ability to perform full duplex
connections, such as communication between a "codec" (coder-decoder) and a DSP,
which involves sending of samples in both directions.
• Because there is no built-in support for the devices addressing, SPI requires more
effort and more hardware resources than I2C when you have more slaves.
• SPI is simpler and more efficient in point-to-point applications (single master, single
slave) for the same reasons: lack of device addressing means less overhead.
 Summary
• Two-wire serial protocol with addressing capability – SCL, SDA
• Half-duplex, synchronous, multi-master bus, multi-slaves
• Speeds up to 3.4 Mbps (ultra-fast 5Mbps)
• Open collector bus driver, Pull-up resistors

• SPI – a 4-wire serial bus (but not official “standard”) - MOSI, MISO, SS/CS, and SCLK signals
• SCLK
• Full-duplex operation
• One master, Multiple slaves
• Best for point-to-point data transfers
• Easily supported, broadly used
I2C:
References
• http://www-us2.semiconductors.philips.com/acrobat/various/
I2C_BUS_SPECIFICATION_1995.pdf
• http://www.esacademy.com/faq/i2c/index.htm
• http://www.embedded.com/story/OEG20020528S0057
• http://www.esacademy.com/faq/i2c/
• http://www.i2cchip.com/
SPI:
• MC68HC11 manual
• http://www.mct.net/faq/spi.html
• http://links.epanorama.net/links/serialbus.html
• http://www.embedded.com/story/OEG20020124S0116

HW. 1. Compare the I²C Bus to the SM Bus.

• SMBus is the System Management Bus defined by Intel® Corporation in
1995. It is used in personal computers and servers for low-speed system
management communications.
2. Study the UNI/O® bus: a low-cost, easy-to-implement solution requiring only a
single I/O signal for communication. (Microchip)
I2S
 Pulse Density Modulation
–In a PDM signal, specific amplitude values are not encoded into pulses of
different size as they would be in PCM.
–Pulse-width modulation (PWM) is the special case of PDM where all the
pulses corresponding to one sample are contiguous in the digital signal.
–A PDM bitstream is encoded from an analog signal through the process of
delta-sigma modulation.
–The process of decoding a PDM signal into an analog one is simple: one only
has to pass the PDM signal through a low-pass filter. This works because the
function of a low-pass filter is essentially to average the signal.
 I2S
I²S designer is Philips Semiconductor/ NXP Semiconductors, (1986);
- Width: 1 data line (SD) + 2 clock lines (SCK, WS)
Protocol: Serial
• I²S (Inter-IC Sound), is an electrical serial bus interface standard used for
connecting digital audio devices together.
• It is used to communicate PCM audio data between integrated circuits
inside an electronic device.
• The I²S bus separates clock and serial data signals, resulting in simpler
receivers than those required for asynchronous communications systems
that need to recover the clock from the data stream.
 Digital Audio
• PCM
– It is the standard form of digital audio in computers, Compact
Discs, digital telephony and other digital audio applications. In a
PCM stream, the amplitude of the analog signal is sampled
regularly at uniform intervals, and each sample is quantized to the
nearest value within a range of digital steps.
– PCM streams have two basic properties that determine their
fidelity to the original analog signal: the sampling rate, the
number of times per second that samples are taken; and the bit
depth, which determines the number of possible digital values
that each sample can take.

http://shepherdingelectrons.blogspot.com/2
018/09/esp8266-minimum-i2s-code.html

https://www.arduino.cc/en/Tutorial/I2SSimpleTone
I2S is optimized for digital audio data transmission
– 3-line serial bus lines
• SD: Two time-multiplexed data channels
• WS: Word Select (0=left channel, 1 = right channel)
• SCK: Clock
– Bus master generates SCK and WS
– Bus master = transmitter or separate controller
– SCK synchronizes transmitter and receiver
• Serial data format
• Two’s complement, MSB sent first
– If system word > #transmitted bits, truncate after LSB
– If system word < #transmitted bits, add 0’s after LSB
I2S Config. / Timing
• A I2S data flow can transport 1 or 2 data channels with a typical bit
rate between 512 kHz for a sampling rate of 8 kHz and 12.288 MHz,
for a sampling rate of 192 kHz.
• The data word length may be of 16, 24 or 32 de bits