Digital Sound Processor With 64K SRAM: TE CH
Digital Sound Processor With 64K SRAM: TE CH
CH T62M0001A
Pin Configuration
VDD 1 24 VCC
XIN 2 23 LPF1 IN
D2/SCK 5 20 OP1 IN
D3/DATA 6 19 REF
D4/IDSW 7 18 CC1
TEST 8 17 CC2
EASY/u-COM 9 16 OP2 IN
D-GND 11 14 LPF2 IN
24 PINS DIP/SOP
Pin Description
Symbol I/O Function Pin no.
VDD P Digital supply voltage 1
XIN I Oscillator input 2
XOUT O Oscillator output 3
Easy mode : inputs D1 data
D1/REQ I 4
u-COM mode :inputs request data
Easy mode : inputs D2 data
D2/SCK I 5
u-COM mode : inputs shift clock
Easy mode : inputs D3 data
D3/DATA I 6
u-COM mode : inputs serial data
Easy mode : inputs D4 data
D4/IDSW I 7
u-COM mode : controls ID code
TEST I L = normal mode 8
H = easy mode
EASY/u-COM I 9
L = u-COM mode
SLEEP I H = sleep mode 10
L = normal mode
D-GND G Digital ground 11
A-GND G Analog ground 12
LPF2 OUT O Low pass filter 2 output 13
LPF2 IN I Low pass filter 2 input 14
OP2 OUT O Integrator 2 output 15
OP2 IN I Integrator 2 input 16
CC2 - Current control 2 17
CC1 - Current control 1 18
REF - Analog reference voltage ( = 1/2 VCC ) 19
OP1 IN I Integrator 1 input 20
OP1 OUT I Integrator 1 output 21
LPF1 OUT - Low pass filter 1 output 22
LPF1 IN O Low pass filter 1 input 23
VCC P Analog supply voltage 24
P : supply voltage,G : ground,I : input pin, O : output pin
Function description
1.Easy mode (parallel data input)
When the pin EASY/ µ − COM = “High”, then in the easy mode.
D4 D3 D2 D1 fs Td
L L L L Fck/3 12.3
L L L H Fck/3 24.6
L L H L Fck/3 36.9
L L H H Fck/3 49.2
L H L L Fck/3 61.4
L H L H Fck/3 73.7
L H H L Fck/3 86.0
L H H H Fck/3 98.3
H L L L Fck/6 110.6
H L L H Fck/6 122.9
H L H L Fck/6 135.2
H L H H Fck/6 147.5
H H L L Fck/6 159.7
H H L H Fck/6 172.0
H H H L Fck/6 184.3
H H H H Fck/6 196.6
When the pin EASY/ u − COM = “Low” , then in the u-COM mode.
The timing is shown as the diagram below:
This timing chart shows that delay time is set by serial data from u-COM.
DATA signal is latched at the falling edge of SCK signal, the last ten datas are set at the rising edge
of REQ signal when ID codes are satisfied.
Power on
(c) Upon power on
4.SLEEP mode
SLEEP data is :
H=clock and RAM stop to reduce circuit current (SLEEP mode)
L=normal operation
5.System reset
Automatically reset power-on. The reset time is about 120 m second.
Delay time is set at 147.5 m second.
Electrical characteristics
(Vcc=5.0V,fin=1KHz,Vi=100mVrms,fck=2MHz,Ta=25ºC, unless otherwise noted)
DC electrical characteristics
limits
symbol parameter unit
Min. Typ. Max.
Application circuit
VCC
100UF/10v C1 EASY MODE
C2
0.1UF U1
C3 Y1 1 24 C4 4700PF
100PF VDD VCC C5 IN
2 23 R1 R2
C6 XIN LPF1_IN C7 1
2MHZ 3 22 560PF 10K 20K 1UF
100PF XOUT LPF1_OUT R3
4 21 18K
D1 OP1_OUT C8 C9
5 20 0.1UF
D2 OP1_IN 1UF
SETING
6 19 47UF/10V
DELAY D3 REF C10 R4
TIMES 7 18 C11 20K
D4 CC1 0.33UF
VCC 8 17
TEST CC2 C12
9 16 0.33UF R5
SW1 EASY/u-COM OP2_IN C13 30K
1 2 10 15 0.1UF
SLEEP OP2_OUT
11 14
DGND LPF2_IN C15
12 13 560PF
AGND LPF2_OUT R6 R7 R8
10K 18K 3K C14
C16
T62M0001A 0.01UF
4700PF
AGND R9
C17 20K
DGND
0.01UF
R10 C18
1 1UF
OUT 2.7K
VCC
100UF/10v C1
u-COM MODE
C2
0.1UF U1
C4
C3 Y1 1 24 4700PF IN
100PF VDD VCC C5
R1 R2
2 23
C6 XIN LPF1_IN C7 1
10K 20K
2MHZ 3 22 560PF 1UF
100PF XOUT LPF1_OUT R3
4 21 18K
REQ OP1_OUT C8 C9
5 20 0.1UF
SCK OP1_IN 1UF
u-COM
6 19 47UF/10V
DATA REF C10 R4
7 18 20K
IDSW CC1 C11
VCC 8 17 0.33UF
TEST CC2 C12
9 16 0.33UF R5
SW1 EASY/u-COM OP2_IN 30K
1 2 10 15 C13
SLEEP OP2_OUT 0.1UF
11 14
DGND LPF2_IN C15 R7
12 13 560PF 18K
AGND LPF2_OUT R6 R8
10K 3K C14
C16 0.01UF
T62M0001A
4700PF
AGND R9
C17 20K
DGND
0.01UF C18
R10
1UF
1
OUT 2.7K
IC package
T62M0001A(24-DIP)
A1
B2
B
B3 A1
B1
D2
C1 C D1
T62M0001A(24-SOP)
D
24 13
.....
E1
E A
.....
1 12 C
SC A LE:"A "
..... A2 A
A1
Z e b
Y
£ c
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