Chapter 3

Memory Interface, I/O Interface

LEARNING OBJECTIVES

 Memory interface  Handshaking

 RAM  Data transfer mode
 ROM  Design techniques for interrupts
 Memory interfacing  Direct memory access
 Input–output interfacing  Input–output processor

MeMorY Interface The memory responds by placing the data from the addressed loca-
tion onto the data lines and confirms the actions. Upon confirma-
Basic Concepts tion, the processor loads the data onto the data lines, into MDR
Computer memory is used to store programs and data. The maxi- register. The processor writes the data into the memory location by
mum size of a memory that can be used in any computer is deter- loading the address of this location into MAR and loading the data
mined by the addressing scheme. into MDR sets the R /W line to 0.
Example: If the memory address has 16-bits, then the size of • Memory Access Time: It is the time that elapses between
memory will be 216 Bytes. the initiation of an operation and the completion of that
operation.
Memory CPU
• Memory Cycle Time: It is the minimum time delay that
k -bit address required between the initiations of two successive memory
Upto 2k bus operations.
addressable MAR
lines n-bit data
Word length bus
= n bits
MBR RAM (Random Access Memory)
Control lines In RAM, if any location that can be accessed for a read/write oper-
ation in fixed amount of time, it is independent of the location’s
address:
If MAR is k-bits long and MDR is n-bits long, then the memory
may contain up to 2k addressable locations and the n-bits of data • Memory cells are usually organized in the form of array, in
are transferred between the processor and memory. This transfer which each cell is capable of storing one bit of information.
takes place over processor bus. The processor bus has • Each row of cells constitutes a memory word and all cells of a
1. Address line row are connected to a common line called as word line.
2. Data line • The cells in each column are connected to sense/write circuit by
3. Control line two bit lines.
Control line is used for coordinating data transfer. The data input and data output of each sense/write circuit are con-
Processor reads the data from the memory by loading the nected to a single bidirectional data line that can be connected to
address of the required memory location into MAR and setting the a data bus.
R /W line to 1.
2.34 | Unit 2  •  Computer O
­ rganization and Architecture

b7 b 7′ b1 b 1′ b0 b 0′
W0

W1

A0 W2
A1 Address
A2 Decoder Memory cells
A3

Sense/Write Sense/Write Sense/Write R /W

circuit circuit circuit CS

Data i/o lines b7 b1 b0

Figure 1  Organization of bit cells in a memory chip

Word line
•• R /W : Specifies the required operation.
•• CS: Chip select input selects a given chip in the ­multi-chip
memory system.
T
C
Static memories
Memories that consist of circuits capable of retaining their
state as long as power is applied are known as static memories. Bit line
If charge on capacitor > threshold value, then bit line will
SRAM (static RAM)  SRAM consists of two inverters, two have ‘1’. If charge on capacitor < threshold value, then bit
transistors. In order to read the state of the SRAM cell, the line will have ‘0’.
word line is activated to close switches T1 and T2.
DRAM SRAM
b b′ 1. Volatile 1. Volatile
l1 2. Simple to build and slower 2.  Faster than DRAM
T1 T2 than SRAM
3.  Need refresh circuitry 3.  More expensive to build
l2
4. Favoured for large ­memory 4.  Favoured for cache memory
Word line units
Bit lines
Latency  It is the amount of time it takes to transfer a word
Advantages of SRAM: of data to or from the memory.
1. It has low power consumption, because the current •• For the transfer of a single word, the latency provides the
flows in the cell only when the cell is being activated complete indication of memory performance.
or accessed. •• For a block transfer, the latency denotes the time it takes
2. SRAM can be accessed quickly. to transfer the first word of data.
Disadvantages of SRAM: SRAMs are said to be volatile Bandwidth  It is defined as the number of bits or bytes that
memories, because their contents are lost when the power can be transferred in one second.
is interrupted.
Note: All dynamic memories have to be refreshed.
DRAM (Dynamic RAM) Less expensive RAMs can be
implemented if simplex cells are used, such cells cannot CS1
CS1
retain their state indefinitely. Hence they are called dynamic CS2
CS2
RAMs. Read
8-bit
RD 128 × 8
The information stored in a dynamic memory cell in the RAM
bidirectional
Write data bas
form of a charge on a capacitor and this charge can be main- WR
tained only for tens of milliseconds. 7-bit address
AD1 − AD 7
The contents must be periodically refreshed by restoring
the capacitor charge to its full value.
Example: Single-transistor dynamic memory cell: Figure 2  RAM chip block diagram
 Chapter 3  •  Memory Interface, I/O Interface  |  2.35

Read-only Memory (ROM) register of a memory chip. To perform this, the micropro-
Both SRAM and DRAM chips are volatile, which means cessor should be
that they lose the stored information if power is turned off. 1. able to select the chip.
If the normal operation involves only reading of stored data, 2. identify the register.
use ROM memory. 3. enable the appropriate buffer.

Word line
Input–output Interfacing
T
Basic Concepts of I/O Module
Connected to store 0. I/O module contains logic for performing a communication
P
Not connected to store 1. function between the peripherals and the bus. The peripher-
als are not connected to the system bus directly. The reasons
for this are
Figure 3  ROM cell
1. Peripherals are electromechanical and electromag­
netic devices and their manner of operation is
Types of ROM different from the operation of the CPU and memory,
Different types of non-volatile ROM are: which are electronicdevices. So a conversion of signal
values may be required.
1. PROM (Programmable ROM): 2. The data transfer rate of peripherals is usually
•• Allows the data to be loaded by the user. slower than the transfer rate of the CPU and hence a
•• Less expensive, faster, flexible. synchronization mechanism may be needed.
2. EPROM (Erasable PROM): 3. Data codes and formats in peripherals differ from the
•• Allows the stored data to be erased and new data word format in the CPU and memory.
to be loaded. 4. The operating modes of peripherals are different from
•• Flexible, retain information for a long time. each other and each must be controlled so as not to
•• Contents erased by UV light. disturb the operation of other peripherals connected
to the CPU.
3. EEPROM (Electrically Erasable PROM):
•• Programmed and erased electrically. To resolve these differences, computer systems include spe-
•• Allows the erasing of all cell contents selectively. cial hardware components between the CPU and peripherals
•• Requires different voltage for erasing, writing and to supervise and synchronize all input and output transfers.
reading of stored data. These components are called ‘interface’ units.
4. Flash memory: Allows to read the contents of a By using this interfacing,
single cell but it is only possible to write the entire
contents of a block. 1. interface to the processor and memory via the system
bus or central switch.
2. interface to one or more peripheral devices by tailored
data links.
Chip select 1 CS1
512 × 8
ROM 8-bit
Chip select 2 CS2 unidirectional
Input–output devices
data bas •• Input and Output devices provide a means for people to
make use of a computer.
9-bit address AD 1 − AD 9 •• Some I/O devices function as an interface between a
computer system and other physical system.
Figure 4  Block diagram of ROM chip

Input–output interface
Input/output Interface provides a method for transferring
Memory Interfacing information between internal storage (such as memory
The interfacing circuit enables the access of processor to and CPU Register) and external I/O devices. It resolves
memory. The function of memory interfacing is that the the difference between the computer and peripheral
processor should be able to read from and write into a given devices.
2.36 | Unit 2  •  Computer O
­ rganization and Architecture

Input–output bus and interface modules In asynchronous transmission, binary information is sent
Each peripheral has an interface module associated with it. only when it is available and the line remains idle when
The interface module decodes the device address (device there is no information to be transmitted.
code), decodes signals for the peripheral controller, syn- In serial asynchronous transmission technique, each
chronizes the data flow and supervises the transfer rate character consists of three parts:
between peripheral and CPU or memory. 1. start bits
2. character bits
3. stop bits
Data
Processor Address Example:
Control

1 1 0 0 0 1 0 1
Interface Interface Interface Star bit Character bits Stop bits

A transmitted character can be detected by the receiver from

Keyboard the knowledge of the transmission rules:
and Magnetic
Printer
display disk 1. When a character is not being sent, the line is kept in
terminal the 1-state.
2. The initiation of a character transmission is detected
from the start bit, which is always 0.
Function of buses 3. The character bits always follow the start bit.
1. Memory bus: It is used for information transfer 4. After the last bit of the character is transmitted, a stop
between CPU and main memory. bit is detected when the line returns to the 1-state for
2. I/O bus: It is used for information transfers at least one bit time.
between CPU and I/O devices through their I/O •• The baud rate is defined as the rate at which serial
interface. information is transmitted and is equivalent to the
data transfer in bits per second.
Isolated versus memory mapped I/O Strobe control  Employs a single control line to time each
1. Isolated I/O: transfer. Strobe may be activated by either the source or the
•• Separate I/O read/write control lines in addition to destination units.
memory read/write control lines. (a) Source initiated transfer:
•• Separate (isolated) memory and I/O address space
Data bus
•• Distinct input and output instructions. Source unit Destination
Strobe unit
2. Memory-mapped I/O:
•• A single set of Read/write control lines (i.e., no dis- Data Valid data
tinction between memory and I/O transfer).
•• Memory and I/O address share the common Strobe
address space (reduces memory address range
available). Figure 5  Source initiated strobe for data transfer
•• No specific input or output instruction.
•• The same memory reference instructions can be •• The data bus carries the binary information from
used for I/O transfer. source unit to the destination unit.
•• Considerable flexibility in handling I/O operations. •• The strobe is a single line that informs the destination
unit when a valid data word is available in the bus.
(b) Destination initiated strobe for data transfer:
Asynchronous serial transfer
Data bus
In serial data transmission, each bit in the message is sent in Destination
Source unit Strobe
sequence one at a time. Serial transmission can be synchro- unit
nous or asynchronous.
In synchronous transmission, the two units share a com- Data Valid data
mon clock frequency and bits are transmitted continuously
Strobe
at the rate dictated by the clock pulses.
 Chapter 3  •  Memory Interface, I/O Interface  |  2.37

•• The destination unit activates the strobe pulse, Modes of transfer

informing the source to provide the data. The There are three different data transfer modes between the
source unit responds by placing the requested central computer (CPU or Memory) and peripherals:
binary information on the data bus.
1. Program-controlled I/O
•• The data must be valid and remain in the bus long
enough for the destination unit to accept it. 2. Interrupt-initiated I/O
•• The falling edge of the strobe pulse can be used 3. Direct memory access
again to trigger a destination register. The destina-
Program-controlled input–output  With programmed I/O,
tion unit then disables the strobe.
the I/O module will perform the requested action and
then set the appropriate bits in the I/O status register. The
Handshaking I/O module takes no further action to alert the CPU. In
Disadvantage of strobe method: Source unit which initi- particular it does not interrupt the CPU. Thus, it is the
ated the transfer has no way of knowing whether the des- responsibility of the CPU to periodically check the sta-
tination unit has actually received the data item that was tus of the I/O module until it finds that the operation is
placed in the bus. complete.
The handshake method solves this problem by introduc-
ing a second control signal that provides a reply to the unit
that initiates the transfer.
Principle of two-wire handshaking: One control line is Issue read
in the same direction as the data flow in the bus from the command to CPU I/O
source to the destination. It is used by the source unit to I/O module
inform the destination unit whether there are valid data in
the bus.
Read status
The other control line is in the other direction from the of I/O module
I/O CPU
destination to the source. It is used by the destination unit to
inform the source whether it can accept data. Not ready
The sequence of control during the transfer depends on
the unit that initiates the transfer.
Check status Error condition

Data bus Ready

Data valid Destination
Source unit Read word
Data accepted unit
from I/O I/O CPU
module

Data bus Write word

Valid data CPU Memory
into memory

Data valid No
Done?

Data Yes
accepted
Next instruction

Figure 6  Source initiated transfer using hand shaking

Interrupt initiated input–output  The problem with pro-

Similarly a destination unit may also initiate the
grammed I/O is that the CPU has to wait a long time for
transfer.
the I/O module of concern to be ready for either recep-
Advantage: Handshaking scheme provides a high degree tion or transmission of data. The CPU, while waiting must
of flexibility and reliability because the successful com- repeatedly interrogate the status of the I/O module. As a
pletion of a data transfer relies on active participation by result, the level of the performance of the entire system is
both units. severely degraded.
2.38 | Unit 2  •  Computer O
­ rganization and Architecture

An alternation is for the CPU to issue an I/O command to Hardware

a module and then go on to do some other useful work. The
I/O module will then interrupt the CPU to request service
when it is ready to exchange data with the CPU. The CPU Device controller or
Save remainder
then executes the data transfer, as before and then resumes other system hardware
of process state
issues an interrupt
its former processing. information

Issue read CPU I/O Processor finishes Process

command to execution of current interrupt
Do something
I/O module instruction
else

Interrupt
Read status
Restore
of I/O module Processor signals
I/O CPU Process State
acknowledgement Information
of interrupt

Check status Error condition

Restore old
Processor pushes PSW and PC
Ready PSW and PC onto
control stack
Read word
from I/O I/O CPU Software
module

Processor loads
new PC value
Write word
CPU Memory based on interrupt
into memory

No Figure 7  Interrupt Processing Flowchart

Done?
Consider the following figures, which show the ­contents of
Yes memory and registers before and after interrupt i­nstruction
processing.
Next instruction
Y
Control
Interrupt Processing:  In all computers, there is a mecha- stack
T −m
nism by which the normal processing of the processor is N +1
interrupted by other modules like I/O, memory. The inter- T PC
rupts may be of the following class:
1. Program: Generated by some condition that occurs as Y Start
a result of an instruction execution. Interrupt
Y +L Return
Examples:  Arithmetic overflow, division by zero, service Registers
etc. routine
T
2. Timer: Generated by timer within the processor.
SP
3. I/O: Generated by an I/O controller, to signal normal N User’s
Processor
completion of an operation or to signal a variety of N +1 program T −m
error conditions.
4. Hardware failure: Generated by a failure such as
power failure or memory parity error.
Interrupts are provided primarily as a way to improve pro- Main memory
cessing efficiency. Figure 8  Interrupt occurs after instruction at location N
 Chapter 3  •  Memory Interface, I/O Interface  |  2.39

Control to poll each I/O module to determine which module

stack generated the interrupt. The poll could be in the form
T−m of a separate command line. The CPU receives the
N+1 Y+L
command and places the address of a particular I/O
PC module on the address lines. The I/O module responds
T
positively if it set the interrupt. Alternatively, each I/O
module could contain an addressable status register.
The CPU then read the status register of each I/O
Y Start module to identify the interrupting module. Once the
correct module is identified, the CPU branches to a
Return Interrupt
Y+L device service routine specified to that device. It is
service Registers
routine time consuming.
(c) Daisy chain: Daisy chain in effect provides a
T−m hardware poll. For interrupts all I/O modules share
SP a common interrupt request line. The interrupt
N acknowledge line is daisy chained through the
User’s Processor
program T
modules. When the CPU is interrupted, it sends
N+1
out an interrupt acknowledgement. This signal
propagates through a series of I/O modules until it
gets to a requesting module. The requesting module
typically responds by placing a word on the data
lines. This word is referred to as a vector and is either
Main memory the address of the I/O module or some other unique
identifier. In either case, the CPU uses the vector as
Figure 9  Return from interrupt a pointer to the appropriate device-service routine.
This avoids the need to execute a general interrupt-
service routine first. This technique is referred to as a
Interrupt priority: Priority determines which interrupt vectored Interrupt.
is to be served first when two or more requests are made
simultaneously. Priority also determines which interrupts (d) Bus arbitration: Bus arbitration is also another
are permitted to interrupt the computer while another is technique which makes use of vectored Interrupts.
being serviced. Higher priority interrupts can make requests With bus arbitration, an I/O module must first gain
while servicing a lower priority interrupt. control of the bus before it can raise the interrupt
request line. Thus only one module can raise the
Design techniques for interrupts: Two design issues arise line at a time. When the CPU detects the interrupt,
in implementing interrupt I/O: it responds on the interrupt acknowledge line. The
requesting module then places its vector on the data
1. Since there will almost invariably be multiple I/O lines.
module, how does the CPU determine which device
issued the interrupt.
Direct Memory Access (DMA)
2. If multiple interrupts have occurred, how does the
CPU decide which one to process. Drawbacks of programmed and interrupt-driven I/O:
Four general categories of techniques are there which are 1. The I/O transfer rate is limited by the speed with
common in use: which the processor can test and service a device.
2. The processor is tied up in managing I/O transfer; a
(a) Multiple interrupt lines: In this technique, multiple number of instructions must be executed for each I/O
interrupt lines are provided between the CPU and the transfer.
I/O modules. However, it is impractical to dedicate
more than a few bus lines or CPU pins to interrupt Both methods have an adverse impact on both processor
lines. Consequently, even if multiple lines are used, it activity and I/O transfer rate.
is likely that each line will have multiple I/O modules When large volume of data is to be moved, a more
attached to it. Thus, one of the other three techniques efficient technique is required: Direct Memory Access
must be used one each line. (DMA).
(b) Software poll: When the CPU detects an interrupt, it DMA function: DMA involves an additional module on the
braches to an interrupt-service routine whose job is system bus.
2.40 | Unit 2  •  Computer O
­ rganization and Architecture

System bus

Data count

Processor DMA Memory

Data
Data lines
register
I/O bus

Address
Address line register
I/O I/O I/O

DMA request With DMA, when the CPU wishes to read or write a block
DMA acknowledgement of data, it issues a command to the DMA module, by send-
Control ing the following information to the DMA module.
Interrupt logic
Read 1. Whether a read or write is requested.
Write 2. The address of the I/O device involved.
3. The starting location in memory to read from or write to.
4. The number of words to be read or written.
Figure 10  DMA Block Diagram
The CPU then continues with other work. It has delegates
The DMA module is capable of mimicking the processor this I/O operation to the DMA module, and that module will
and indeed, of taking over control of the system from the take care of it. The DMA module transfers the entire block
processor. It needs to do this to transfer data to and from of data, one word at a time, directly to or from memory,
memory over the system bus. For this purpose, the DMA without going through the CPU. When the transfer is com-
module must use the bus only when the processor does not plete, the DMA module sends an interrupt signal to the
need it or it must force the processor to suspend operation CPU. Thus, the CPU is involved only at the beginning and
temporarily. The latter technique is more common and is end of the transfer.
referred as cycle stealing.
DMA configurations
1. Single bus, detached DMA Issue read CPU DMA
block
•• Inexpensive, inefficient command to Do something
•• Each transfer of a word consumes two bus cycles. DMA module else

Read status Interrupt

Processor DMA I/O I/O of DMA
Memory DMA CPU
module

2. Single bus, integrated DMA I/O There is a path

between the DMA module and one or more I/O Next instruction
modules that does not include system bus.
DMA transfer can either happen as:
1. Burst transfer
•• A block sequence consisting of a number of mem-
ory words is transferred in continuous burst.
Processor DMA DMA Memory •• DMA controller is master of memory Buses.
I/O •• This mode of transfer is needed for fast devices
such as Magnetic Disks, where transmission can-
not be stopped or slowed down.
I/O I/O
2. Cycle stealing
•• CPU is usually much faster than I/O (DMA), thus
3. I/O bus
CPU uses the most of the memory cycles.
•• Reduces the number of I/O interfaces in the DMA •• DMA controller steals the memory cycles from
module to one. CPU.
•• Easily expandable configuration. •• For those stolen cycles, CPU remains idle.
 Chapter 3  •  Memory Interface, I/O Interface  |  2.41

•• For those slow CPU, DMA Controller may steal •• Unlike DMA, the IOP can fetch and execute its own
most of the memory. instructions.
•• Cycle stealing, which may cause CPU remain idle
The following figure shows a computer with two
long time.
processors:

Input–Output Processor (IOP) CPU

An IOP is a processor, having a direct memory access capa-
bility, used to communicate with I/O devices. Memory
unit Peripherals
In this configuration, the computer system can be divided
into a memory unit and a number of processors comprised PD PD PD PD
of the CPU and one or more IOPs.
Each IOP takes care of input and output tasks, reliev- IOP
ing the CPU from the house keeping chores involved in I/O I/O bus
transfers.
Memory
•• IOP is similar to a CPU except that it is designed to han- bus
dle the details of I/O processing.

Exercises
Practice Problems 1 of the device. If the device is not ready, the processor
Directions for questions 1 to 20:  Select the correct alterna- can jump to other tasks. After some timed interval, the
tive from the given choices. processor comes back to check status again. Let us
assume that above scheme is used for outputting data
1. Consider a DRAM that must be given a refresh cycle one character at a time to a printer that operates at 10
64 times per ms. Each refresh operation requires characters per second (CPS). Which of the following
150 ns, a memory cycle requires 250 ns. What is the statement is true if its status is scanned every 200 ms?
approximate percentage of the memory’s total operat- (A) The printing speed is increased by 5 CPS
ing time must be given to refreshes? (B) The printing rate is slowed to 5 CPS
(A) 1% (B) 2% (C) The printing rate is at 10 CPS only
(C) 9% (D) 60% (D) The printing rate is at 20 CPS
2. A DMA controller transfers 16-bit words to memory
5. Consider a system employing interrupt-driven I/O for
using cycle stealing. The words are assembled from a
a particular device that transfers data at an average of 8
device that transmits characters at a rate of 2400 char-
KB/s on a continuous basis. The interrupt processing
acters per second. The CPU is fetching and executing
takes about 100 ms and the I/O device interrupts processor
instructions at an average rate of 1 million instructions
for every byte. Let assume that the device has two 16-byte
per second. By how much time will the CPU be slowed
buffers and interrupts the processor when one of the buffer
down because of the DMA transfer?
is full. While executing the ISR, the processor takes about
(A) 0.6% (B) 0.1%
8 ms for the transfer of each byte. Then what is the fraction
(C) 0.12% (D) 0.24%
of processor time is consumed by this I/O device?
3. A system is based on a 16-bit microprocessor and has
(A) 8% (B) 11%
two I/O devices. The I/O controllers for this system use
(C) 50% (D) 65%
separate control and status registers. Both devices han-
dle data on a one-byte-at-a time basis. The first device 6. A 32-bit computer has two selector channels one mul-
has two status lines and three control lines. The sec- tiplexor channel. Each selector channel supports two
ond device has three status lines and four control lines. magnetic disks and three magnetic tape units. The mul-
How many 16-bit I/O control module registers do we tiplexor channel has two line printers, two card readers
need for status reading and control of each device? and 10 VDT terminals connected to it. Assume the fol-
(A) 1, 2 (B) 2, 1 lowing transfer rates:
(C) 2, 2 (D) 1, 1 Disk drive: 1000 KB/sec
4. In a programmed I/O technique, the processor is stuck Magnetic tape drive: 300 KB/sec
in a wait loop doing status checking of an I/O device. Line printer: 6.2 KB/sec
To increase efficiency, the I/O software could be writ- Card reader: 2.4 KB/sec
ten so that the processor periodically checks the status VDT: 1 KB/sec
2.42 | Unit 2  •  Computer O
­ rganization and Architecture

What is the maximum aggregate I/O transfer rate of (A) Interrupt vectoring (B) Cycle stealing
this system? (C) DMA (D) Daisy chain
(A) 1625.6 KB/s (B) 1327.2 KB/s
(C) 2027.2 KN/s (D) 2327.2 KB/s 15. What will be the response of the CPU, on receiving an
interrupt from an input/output device?
7. Consider a disk drive with 16 surfaces, 512 tracks per (A) It hands over the control of address bus and data
surface and 512 sectors per track, 1 kilo bytes per sector bus to the interrupting device.
and a Rotation speed of 3000 RPM. The disk is oper- (B) It branches off to the interrupt service routine after
ated in cycle stealing mode where by whenever one 4 completion of the current instruction.
byte word is ready it is sent to memory; similarly, for (C) It halts for a predetermined time.
writing, the disk interface read a 4 byte word from the (D) It branches off to the interrupt service routine im-
memory in each DMA cycle. The memory cycle time mediately.
is 40 nsec. Find the maximum percentage of time that
16. What is the bandwidth of memory system that has a
the CPU gets blocked during DMA operation?
latency of 50ns, a pre charge time of 10ns and transfers
(A) 2.62% (B) 26.21%
2 bytes of data per access?
(C) 0.26% (D) 0.52%
(A) 60 B/sec (B) 1.67 B/sec
8. How many RAM chips of size (256 K × 1-bit) are (C) 1.67 × 107 B/sec (D) 3.33 × 107 B/sec
needed to build a 1 M Byte memory? 17. A hard disk is connected to a 50MHz processor through
(A) 16 (B) 8 a DMA controller. Assume that the initial set-up of a
(C) 32 (D) 24 DMA transfer takes 2000 clock cycles for the proces-
9. Four memory chips of 16 × 4 size have their address sor and also assume that the handling of the interrupt
bases connected together. The whole system will have at DMA completion requires 1000 clock cycles for the
a size of processor. The hard disk has a transfer rate of 4000
(A) 16 × 8 (B) 64 × 64 K bytes/sec and average block size transferred is 8 K
(C) 16 × 16 (D) 256 × 1 bytes. What fraction of the processor time is consumed
by the disk, if the disk is actively transferring 100% of
10. In which of following I/O techniques, there will be no the time?
interrupt? (A) 1% (B) 1.5%
(A) Programmed I/O (B) Interrupt-driven I/O (C) 2% (D) 3%
(C) DMA (D) Both (B) and (C)
18. A device with transfer rate of 20KB/sec is connected
11. The capacity of a memory unit is defined by the num- to a CPU. Data is transferred byte wise. Let the inter-
ber of words multiplied by the number of bits/word. rupt overhead is 6 micro seconds. The byte transfer
How many separate address and data lines are needed time between the device interface register and CPU or
for a memory 16K × 16? memory is negligible. What is minimum performance
(A) 10 address, 4 data lines gain of operating the device under interrupt mode over
(B) 14, 4 operating it under program-controlled mode?
(C) 14, 16 (A) 6 (B) 8
(D) 14, 14 (C) 10 (D) 12
12. The main problem of strobe asynchronous data transfer is 19. A DMA module is transferring characters to main
(A) it employs a single control line memory from an external device at 76800 bits per
(B) it is controlled by clock pulses in the CPU. second. The processor can fetch instructions at a rate
(C) the falling edge again used to trigger of 2 million instructions per second. How much will
(D) no way of knowing whether the destination has re- the processor be slowed down due to DMA activity?
ceived the data item. (Express this as a percent of the time from when there
13. Which of the following DMA transfer modes and is a conflict between DMA and the CPU)
interrupt handling mechanisms will enable the highest (A) 0.24% (B) 0.48%
I/O bandwidth? (C) 0.96% (D) 0.50%
(A) Block transfer and polling interrupt 20. Let us suppose that we want to read 2048 bytes in pro-
(B) Cycle stealing and polling interrupt grammed I/O mode of CPU. The bus width is 32-bits.
(C) Block transfer and vectored interrupt Each time an interrupt occurs from Hard disk drive and
(D) Transparent DMA and vectored interrupt it taken 4 msec to service it. How much CPU time is
14. Which of the following enables peripherals to pass a required to read 2048 bytes?
signal down the bus to the next device on the bus dur- (A) 512 msec (B) 768 msec
ing polling of the device? (C) 1024 msec (D) 2048 msec
 Chapter 3  •  Memory Interface, I/O Interface  |  2.43

Practice Problems 2 (A) 512 × 1000 (B) 512 × 100

Directions for questions 1 to 21:  Select the correct alterna- (C) 512 × 1024 (D) 512 × 1028
tive from the given choices. 10. The number of address lines required in a microproces-
1. Memory which is ultraviolet erasable is sor which has to access 1 K bytes of memory is
(A) RAM (B) EPROM (A) 6 (B) 4
(C) PROM (D) EEPROM (C) 10 (D) 8
2. Memory which is electrically erasable is 11. Software interrupt is
(A) EPROM (B) EEPROM (A) used to stimulate an external device
(C) ROM (D) PROM (B) generated by an external device
(C) Both (A) and (B)
3. The minimum time delay that is required between
(D) None of these
the initiation of two successive memory operations is
called 12. The bus that is used to transfer data from main memory
(A) Memory access time (B) Transmission time to peripheral devices and vice-versa is
(C) Seek Time (D) Memory cycle (A) Control bus (B) input bus
(C) output bus (D) DMA bus
4. The memory that is programmed at the time of manu-
facture is 13. The bus which is connected between the CPU and the
(A) RAM (B) PROM main memory that permits transfer of information
(C) ROM (D) EEPROM between the CPU and main memory is called
(A) memory bus (B) address bus
5. The disadvantage of dynamic RAM over static RAM is
(C) control bus (D) DMA bus
(A) High power consumption
(B) Higher bit density 14. An interrupt in which the external device supplies the
(C) Need to refresh the capacitor charge every once in interrupt requests as well as its address is called
two milliseconds. (A) maskable interrupt
(D) Variable speed (B) vectored interrupt
(C) designated interrupt
6. If an error is detected, a part of the memory can be
(D) non-maskable interrupt
erased in
(A) PROM (B) EPROM 15. A temporarily ignored interrupt is called
(C) EAROM (D) EROM (A) designated interrupt
(B) maskable interrupt
7. What are sequences of events in source initiated hand
(C) non-maskable interrupt
shaking transfer?
(D) low priority interrupt
(A) Source enable data valid, destination enable data
accepted, source disable data valid, destination 16. Which of the following device is used to connect a
disable data accepted peripheral to a bus?
(B) Source disable data valid, destination enable data ac- (A) control register
cepted, source disable data valid, destination enable (B) interface
data accepted (C) communication protocol
(C) Source disable data valid, destination Disable data (D) None of these
valid, source enable data valid, destination enable 17. Which of the following is true for the daisy scheme of
data accepted. connecting input/output devices?
(D) Source disable data valid, destination enable data (A) It gives non-uniform priority to various devices.
valid, source enable data valid, destination disable (B) It gives uniform priority to all devices.
data ­accepted. (C) It is only useful for connecting slow devices to a
8. Processor needs software interrupt to processor device.
(A) return from subroutine (D) It requires a separate interrupt pin on the processor
(B) implement co-routines for each device.
(C) test the interrupt system of the processor 18. In direct memory access data are directly transferred
(D) obtain system services which need execution of (A) from CPU to input/output device and memory
privileged instructions (B) from an input/output device to memory only.
9. A microcomputer has primary memory of 512 KB. (C) from memory to an input/output device only.
what is the exact number of bytes contained in this (D) from an input/output device to the memory or vice
memory? versa
2.44 | Unit 2  •  Computer O
­ rganization and Architecture

19. Which one of the following is true for a CPU having a 20. In which of the following I/O, there is a single address
single interrupt request line and a single interrupt grant space for memory locations and I/O devices
line? (A) Isolated I/O
(A) Vectored interrupt multiple interrupting devices (B) Memory mapped I/O
are always possible. (C) DMA
(B) Vectored interrupts are not possible but multiple (D) Both (A) and (B)
interrupting devices are possible
(C) Vectored interrupts and multiple interrupting de- 21. ____ signal used to interrupt processor and to execute
vices are sometimes possible service routine that takes an error recovery action.
(D) Vectored interrupt is possible but multiple inter- (A) Strobe (B) Handshaking
rupting devices are not possible (C) Polling (D) Time out

Previous Years’ Questions

1. A device with data transfer rate 10 KB/sec is con- 3. Consider that the memory is byte addressable with
nected to a CPU. Data is transferred byte-wise. Let size 32 bits, and the program has been loaded starting
the interrupt overhead be 4 msec. The byte transfer from memory location 1000 (decimal). If an interrupt
time between the device interface register and CPU occurs while the CPU has been halted after executing
or memory is negligible. What is the minimum per- the HALT instruction, the return address (in decimal)
formance gain of operating the device under inter- saved in the stack will be [2004]
rupt mode over operating it under program-controlled (A) 1007 (B) 1020
mode?[2005] (C) 1024 (D) 1028
(A) 15 (B) 25 4. Let the clock cycles required for various operations
(C) 35 (D) 45 be as follows:
2. A computer handles several interrupt sources of Register to/from memory transfer: 3 clock cycles
which the following are relevant for this question. ADD with both operands in register: 1 clock cycle
•• Interrupt from CPU temperature sensor (raises Instruction fetch and decode: 2 clock cycles per word
interrupt if CPU temperature is too high) The total number of clock cycles required to execute
•• Interrupt from Mouse (raises interrupt if the mouse the program is [2004]
is moved or a button is pressed) (A) 29 (B) 24
•• Interrupt from Keyboard (raises interrupt when a (C) 23 (D) 20
key is pressed or released) 5. A CPU generally handles an interrupt by executing an
•• Interrupt from Hard Disk (raises interrupt when a ­interrupt service routine[2009]
disk read is completed) (A) As soon as an interrupt is raised.
Which one of these will be handled at the HIGHEST (B) By checking the interrupt register at the end of
­priority? [2011] fetch cycle.
(A) Interrupt from Hard Disk (C) By checking the interrupt register after finishing
(B) Interrupt from Mouse the execution of the current instruction.
(C) Interrupt from Keyboard (D) By checking the interrupt register at fixed time
(D) Interrupt from CPU temperature sensor ­intervals.
The following information pertains to 3 and 4: Consider 6. A hard disk with a transfer rate of 10 Mbytes/sec-
the following program segment for a hypothetical CPU ond is constantly transferring data to memory using
having three user registers R1, R2 and R3. DMA. The processor runs at 6000 MHz, and takes
300 and 900 clock cycles to initiate and complete
Instruction Size DMA transfer respectively. If the size of the transfer
Instruction Operation (in words) is 20 Kbytes, what is the percentage of processor
MOV R1, 5000; R1 ← Memory [5000] 2 time consumed for the transfer operation?
(A) 5.0% (B) 1.0%
MOV R2 (R1); R2 ← Memory [(R1)] 1
(C) 0.5% (D) 0.1%
ADD R2, R3; R2 ← R2 + R3 1
7. On a non-pipelined sequential processor, a program
MOV 6000, R2; Memory [6000] ← R2 2 segment, which is a part of the interrupt service rou-
HALT; Machine halts 1 tine, is given to transfer 500 bytes from an I/O device
to memory.
 Chapter 3  •  Memory Interface, I/O Interface  |  2.45

Initialize the address register. nanoseconds. The time required to perform one
Initialize the count to 500 refresh operation on all the cells in the memory unit
LOOP: Load a byte from device is [2010]
(A) 100 nanoseconds
Store in memory at address given by address register.
(B) 100 * 210 nanoseconds
Increment the address register
(C) 100 * 220 nanoseconds
Decrement the count
(D) 3200 * 220 nanoseconds
If count! = 0 go to LOOP
10. A processor can support a maximum memory of 4GB,
Assume that each statement in this program is equiva-
where the memory is word - addressable (a word con-
lent to a machine instruction which takes one clock sists of two bytes). The size of the address bus of the
cycle to execute if it is a non-load/store instruction.
processor is atleast ___ bits. [2016]
The load-store instructions take two clock cycles to
execute. 11. The size of the data count register of a DMA control-
ler is 16 bits. The processor needs to transfer a file
The designer of the system also has an alternate
of 29,154 kilobytes from disk to main memory. The
approach of using the DMA controller to implement
memory is byte addressable. The minimum number
the same transfer. The DMA controller requires 20 of times the DMA controller needs to get the control
clock cycles for initialization and other overheads. of the system bus from the processor to transfer the
Each DMA transfer cycle takes two clock cycles file from the disk to main memory is _____. [2016]
to transfer one byte of data from the device to the
memory. 12. The following are some events that occur after a
device controller issues an interrupt while process L
What is the approximate speedup when the DMA is under execution.
controller based design is used in place of the inter-
(P) The processor pushes the process status of L onto
rupt driven program based input-output? [2011]
the control stack.
(A) 3.4 (B) 4.4
(Q) The processor finishes the execution of the cur-
(C) 5.1 (D) 6.7
rent instruction.
8. Which of the following statements about synchronous (R) The processor executes the interrupt service rou-
and asynchronous I/O is NOT true? [2008] tine.
(A) An ISR is invoked on completion of I/O in syn- (S) The processor pops the process status of L from
chronous I/O but not in asynchronous I/O the control stack.
(B) In both synchronous and asynchronous I/O, an (T) The processor loads the new PC value based on
ISR (Interrupt Service Routine) is invoked after the interrupt.
completion of the I/O Which one of the following is the correct order in
(C) A process making a synchronous I/O call waits which the events above occur? [2018]
until I/O is complete, but a process making an (A) QPTRS (B) PTRSQ
asynchronous I/O call does not wait for comple- (C) TRPQS (D) QTPRS
tion of the I/O 13. A 32-bit wide main memory unit with a capacity of
(D) In the case of synchronous I/O, the process wait- 1 GB is built using 256 M × 4-bit DRAM chips. The
ing for the completion of I/O is woken up by the number of rows of memory cells in the DRAM chip
ISR that is invoked after the completion of I/O is 214. The time taken to perform one refresh operation
is 50 nanoseconds. The refresh period is 2 millisec-
9. A main memory unit with a capacity of 4 megabytes
onds. The percentage (rounded to the closest integer)
is built using 1M × 1-bit DRAM chips. Each DRAM
of the time available for performing the memory read
chip has 1K rows of cells with 1K cells in each row.
write operations in the main memory unit is ______.
The time taken for a single refresh operation is 100
 [2018]
2.46 | Unit 2  •  Computer O
­ rganization and Architecture

Answer Keys
Exercises
Practice Problems 1
1. A 2.  C 3. D 4. B 5. B 6. C 7. B 8. C 9. C 10. A
11. C 12. D 13. A 14. D 15. B 16. D 17. D 18. B 19. B 20. D

Practice Problems 2
1. B 2. B 3. A 4. C 5. A 6. C 7. B 8. D 9. C 10. C
11. A 12. D 13. A 14. B 15. B 16. B 17. A 18. D 19. B 20. B
21. D

Previous Years’ Questions

1. B 2. D 3. D 4. B 5. C 6. D 7. A 8. A 9. D 10. 31
11. 456 12. A 13.  59 to 60