`PANIMALAR ENGINEERING

COLLEGE
(A CHRISTIAN MINORITY INSTITUTION)
JAISAKTHI EDUCATIONAL TRUST
ACCREDITED BY NATIONAL BOARD OF ACCREDITATION (NBA)
LORE TRUNK ROAD, VARADHARAJAPURAM, NASARATHPET, POONAMALLEE, CHENNAI –

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC8462- LINEAR INTEGRATED CIRCUITS LAB

II ECE - IV SEMESTER

(2020 – 2021 EVEN SEMESTER)

 DEPARTMENT OF ECE

BONAFIDE CERTIFICATE
REGISTER NO:

Certified to be the bonafide work done by “ NAME ”

Department of ELECTRONICS AND COMMUNICATION ENGINEERING semester IV in
the Subject of EC8462- LINEAR INTEGRATED CIRCUITS LABORATORY during the year
2020-2021.

HOD SIGNATURE STAFF IN CHARGE

Dr. P. KANNAN, M.E., Ph.D. N. NITHYA, M.E.,
PROFESSOR AND HEAD ASSISTANT PROFESSOR
Department of ECE, Department of ECE,
Panimalar Engineering College, Panimalar Engineering
College,
Chennai - 600 123. Chennai - 600 123.

Submitted to the Practical Examination held in ___________ 2021.

INTERNAL EXAMINER EXTERNAL EXAMINER

 INDEX

S.No Date Of Expt. Name Of the Experiment Page No.

Inverting, Non-Inverting and Differential Amplifiers

1. 04
using Op-amp IC 741

2. Integrator and Differentiator using Op-amp IC 741 14

3. Instrumentation Amplifier (IA) using Op-amp IC 741 24

Active low pass, High pass and Band pass filter using
4. 28
Op-amp IC 741
Astable, Monostable multivibrator and Schmitt
5. 40
trigger using Op-amp IC 741
RC Phase Shift and Wien Bridge Oscillator using
6. 51
Op-amp IC 741
Astable and Monostable Multivibrator using IC 555
7. 57
Timer
PLL Characteristics and Frequency Multiplier using
8. 65
PLL IC 565

9. R-2R Ladder type DAC using Op-amp 741 69

10. DC Power Supply using LM 317 and LM 723 72

11. Simulation Experiments using P-Spice 76

CIRCUIT DIAGRAM:
INVERTING AMPLIFIER
 Rf=2
K
+15v

R1=1 2 7
K -
IC 741
Signal + 6
Generator + 3 4 +
~
Vi CRO
n -15v
- -

NON-INVERTING AMPLIFIER

Rf=33K

+15v

R1=10 2 7
K
-
IC 741
+ 6
+ 3 4 +

Signal Vi
~ CRO
Generator
n - -15v
-

DIFFERENTIAL AMPLIFIER
Rf=R3=100
K

+15v

R1=10 2 7
k -
IC 741
+ + 6
+ R2=10 3 4 +
K R3=100
Vin 1 V
Vin 2 K -15v
- -
-

INVERTING, NON-INVERTING AND

0
DIFFERENTIAL AMPLIFIERS USING
OP-AMP
EXP.No: 01 DATE:

AIM:-
To design the Inverting, Non-Inverting and Differential Amplifiers using

Op-amp IC741 and test their performance.

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 01
1KΩ, 33KΩ EACH 01
2. RESISTORS
10KΩ, 100 KΩ. EACH 02
4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

THEORY:-
Op-amp in open-loop configuration has a very few application because of its enormous open-loop
gain. Controlled gain can be can be achieved by taking a part of output signal to the input with the help of
feedback. This is called as Closed-Loop Configuration. The three basic types of closed-loop amplifier
configuration are:
1. Inverting amplifier.
2. Non-inverting amplifier.
3. Differential amplifier.
The entire configuration can be operated with either AC or DC input.

INVERTING AMPLIFIER:-
If the input signal is applied to the inverting terminal through an input resistance, a part of
output is feedback to the inverting terminal through feedback resistance R f and the non-inverting terminal
grounded, then the configuration is said to be Inverting Amplifier. It provides 1800 phase shift or polarity

−Rf
Avcl=
reversal for the given input. The circuit closed-loop voltage gain is R1 .

NON-INVERTING AMPLIFIER:-
If the input signal is given to non inverting terminal & the feedback from output is
connected to inverting terminal of an op-amp through a potential divider network, then it is called as Non-
Inverting Amplifier Configuration. It operates in a same way as a voltage follower (unity gain buffer), except
that the output voltage is potentially divided before it is feedback to the inverting input terminal. No phase

Rf
Avcl=1+
shift or change in the circuit closed loop polarity occurs voltage gain is R1

DIFFERENTIAL AMPLIFIER:
A configuration which combines inverting & non-inverting configuration with both input
terminals are supplied with Vin1 & Vin2, then it is called as Differential Amplifier configuration. This circuit
amplifies the difference between the two inputs. Differential amplifier with a single op-amp has the exact
gain of an inverting amplifier and it is given as

Vo −R
= AVCL= =| f |
(V in −V in2 ) R 1
AD (Using One Op-Amp) 1

A differential amplifier with two op-amps has the exact gain of a non-inverting amplifier and it is given as:

Vo Rf
= AVCL = =1+
(V in −V in2 ) R1
AD (Using Two Op-Amps) 1 .

MODEL GRAPH:
INVERTING AMPLIFIER
 Vin

INPUT

Time (ms)

Vout

OUTPUT Time (ms)

NON-INVERTING AMPLIFIER

Vin

INPUT

Time (ms)

Vout

OUTPUT Time (ms)

DIFFERENTIAL AMPLIFIER
PROCEDURE-
(INVERTING & NON-INVERTING AMPLIFIER)
1. Select R1 as a constant value and choose a value of R f.
2. Connect the circuit as per as the circuit diagram.
3. Apply the constant amplitude input voltage to the circuit.
4. Measure the output voltage amplitude for different value of R f from CRO.
5. Calculate the practical gain for different value of R f & compare it with theoretical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.

(DIFFERENTIAL AMPLIFIER)
1. Select the value of R1, R2, R3 & Rf such that R1=R2 and R3=Rf.
2. Connect the circuit as per as the circuit diagram.
3. Provide constant input voltage V in1 to Non-inverting terminal of op-amp through R 1 &
constant input voltage Vin2 to inverting terminal of op-amp through R 2.
4. Measure the output voltage using CRO.
5. Calculate the theoretical gain and compare it with practical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.

TABULATION:
INVERTING AMPLIFIER
 Theoretical Gain

S.No Rf (KΩ) R1 (KΩ) Vin V0 Rf Practical Gain

(Volts) (Volts) |− ¿| A=V0 /Vin
A=
Ralignl¿1 ¿¿
2K 1K
1. 0 0 2 2

NON-INVERTING AMPLIFIER

R1(KΩ) Vin Vout Theoretical Gain Practical Gain

S.No Rf (KΩ)
(Volts) (Volts) A = 1+(Rf / R1) A = V0 / Vin
10K
1. 33K 0 0 4.3 4.3

DIFFERENTIAL AMPLIFIER

RF (KΩ) R1 (KΩ) R2 (KΩ) Theoretical Practical

Gain Gain
S.No
Vin1
(Volts)
Vin2
(Volts)
Vin2 - Vin1
(Volts)
Rf A=V0 / (Vin2 -
|− ¿| Vin1)
A=
Ralignl¿ 1 ¿¿
100K 10K 10K
1. 0 0 0 10 10

SNAPSHOTS:
 Inverting Amplifier

NON-INVERTING AMPLIFIER
DIFFERENTIAL AMPLIFIER
RESULT:
Thus the Inverting, Non-Inverting and Differential Amplifiers are designed and their
performance was successfully tested using op-amp IC 741.

CIRCUIT DIAGRAM:
 INTEGRATOR

DIFFERENTIATOR

INTEGRATOR AND DIFFERENTIATOR USING OP-AMP.

EXP.No: 02 DATE:
AIM:-
To design an Integrator and Differentiator using op-amp IC 741 and show the relation
between their Input –Output Characteristics.

APPARATUS REQUIRED:-

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 --- 01
100 Ω, 1.5KΩ Each 02
2. RESISTORS
10KΩ, 15KΩ Each 01
0.1μf, 0.01μf Each 01
4. CAPACITOR
0.001μf, 05
6. DIGITAL TRAINER KIT --- 01
7. SIGNAL GENERATOR (0-3)MHz 01
8. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
9. CONNECTING WIRES --- FEW

THEORY :
INTEGRATOR
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator or integration amplifier; such a circuit is obtained by using basic
inverting amplifier configuration, if the feed back resistor R f is replaced by a capacitor C f. The
t
1
V O =− ∫ V dt +C
Output voltage expression is given as R1 C f o in .
1
=
The frequency of input at which the gain is 0 db is given as f 2 πR1 C f
b
The point up to which the gain is constant & maximum is called as gain limiting frequency & given
1
=
as f 2 πR f C f Where R is the feedback resistor used to correct the stability & roll-off
a f
problems. Between fa & fb the circuit acts as an integrator and it is similar to a LPF. Integrator is
most commonly used in analog computers, A/D converter & signal wave shaping circuits.

Integrator as Wave shaping circuit

Design of integrator with a lower frequency (Break Frequency) limit of integration at
fa = 1 KHz & the frequency at which 0dB results fb = 10 KHz. Observe the Input-Output
characteristics.

DIFFERENTIATOR
 A differentiator or differentiation amplifier is a circuit which performs the mathematical
operation of differentiation; that is, the output waveform is the derivative of the input waveform. The
differentiator may be constructed from the basic inverting amplifier if an input resistor R 1 is replaced by
capacitor C1. The differentiation is very useful to find the rate at which a signal varies with time. For
maintaining the stability of differentiator, a series resistor R 1 is connected with input capacitor C 1. The circuit
will provide differentiation function but only over a limited frequency range & over this range differentiator

dVin
Vo=−R f C1
tend to oscillate (or) poor stability results. The expression for output voltage is dt

MODAL GRAPH:
INTEGRATOR

DIFFRENTIATOR

(i) FOR SQUARE WAVE INPUT

 (i) FOR SINE WAVE INPUT

PROCEDURE:-
INTEGRATOR

1. From the given frequency fa & fb, the values of Rf, Cf, R1 & Rcomp are calculated as given
in the design procedure. Connect the circuit as shown in the circuit diagram.
2. Apply the sinusoidal and square wave input and tabulate the output parameters and plot the
graph showing the shape of input and output signal.

DIFFRENTIATOR

1. Select fa equal to the highest frequency of the input signal to be differentiated. Calculate
the component values of C1 & Rf.
2. Choose fb = 20fa & calculate the values of R1 & Cf, so that R1C1=Rf Cf.
3. Connect the components as shown in the circuit diagram.
4. Apply a sinusoidal & square wave input to the inverting terminal of op-amp through R 1 C1.
5. Observe the shape of the output signal for the given input in CRO.

DESIGN:

INTEGRATOR
Design of integrator to integrate at cut-off frequency 1 KHz. Apply sine and square wave and observe the
output.
1
Take fa =
2 πRf C f
= 1 KHz.
Always take Cf < 1 μf and

Let Cf = 0.01μf

1
Rf =
2 πC f f a
Rf = 15.9KΩ

Rf = 15 KΩ

1
Take fb =
2 πR1 C f = 10 KHz.
1
R1 =
2 πf b C f = 1.59 KΩ.

R 1 ≈ 1.5KΩ

R1 R f
Rcomp = R1 // Rf =
R 1 +Rf ≈ R1, Assume RL = 10KΩ

R comp = 1.5KΩ

DIFFERENTIATOR
Design a differentiator to differentiate an input signal that varies in frequency from 10Hz to 1KHz. Apply a
sine wave & square wave of 2Vp-p & 1 KHz frequency & observe the output.
To find Rf & C1
Given: fa = 1 KHz.
1
fa =
2 πRf C 1
fa = 1KHz.

Assume C1 = 0.1μf

R f = 1.59KΩ ≈ 1.5KΩ

To find R1 & Cf
Select fb = 20fa with R1C1 = Rf Cf
1
fb = 20KHz =
2 πR1 C 1

R1 = 79.5Ω ≈ 100Ω

R 1C 1 82 X 0.1 X 10−6
Cf = Rf = 1. 5 K Ω

C f = 0.005μf.

R OM ≈ R1 // Rf = 100Ω

SINE WAVE INPUT:-

Vp-p = 2V f=1KHz
Vp = 1V,
Vin = Vp sin ω t
= sin (2 π )(103)t
dVin
Vo = - RfC1 dt
d
= -(1.5KΩ) (0.1μf) dt [sin [(2 π )(103)t]

= -(1.5KΩ) (0.1μf) (2 π ) (103) cos [(2 π )(103)t]

= - 0.94 cos [(2 π )(103)t]

TABULATION:
INTEGRATOR
 1K 1K

0.2 V 1V

1 ms 1 ms

1.3 V 5V

1.2 ms 1 ms

DIFFRENTIATOR

Sine Wave Square

Wave
1. Frequency (Input) 1K 1K
Input Voltage (Vin
2. 1.9 V 0.1 V
peak)
Input Time Period
3. 1 ms 2 ms
(tVin)
Output Voltage (Vout
4. 2V 1.4 V
peak)
Output Time Period
5. 1 ms 2 ms
(tVo)

SNAPSHOTS:
INTEGRATOR(SINE WAVE )
INTEGRATOR(SQUARE WAVE)
DIFFRENTIAROR(SINE WAVE)
DIFFRENTIAROR (SQUARE WAVE)
RESULT:-
Thus an Integrator and Differentiator using op-amp are designed and their Input-Output
relationship was successfully tested using op-amp IC 741.

CIRCUIT DIAGRAM:-
INSTRUMENTATION AMPLIFIER
 INSTRUMENTATION AMPLIFIER

EXP.No: 03 DATE:

AIM:-
To construct, test and prove the output voltage dependence on single gain variable resistor of a 3
op-amp instrumentation amplifier using op-amp IC741.

APPARATUS REQUIRED:-

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 03
10KΩ. 05
2. RESISTORS
2KΩ 02
4. DRB --- 01
5. DIGITAL TRAINER KIT --- 01
6. SIGNAL GENERATOR (0-3)MHz 02
7. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
8. CONNECTING WIRES --- FEW

THEORY:-

An instrumentation amplifier is the intermediate stage of an instrumentation system. The signal

source of the instrumentation amplifier is the output of the transducer. Many transducers output do not
have the ability or sufficient strength to drive the next following stages. Therefore, instrumentation
amplifiers are used to amplify the low-level output signal of the transducer so that it can drive the following
stages such as indicator or displays.
The major requirements of an instrumentation amplifier are precise, low-level signal
amplification where low-noise, low thermal and time drifts, high input resistance & accurate closed-loop
gain, low power consumption, high CMRR & high slew rate for superior performance.
MODEL GRAPH:-

PROCEDURE:

1. Select the entire resistor with same value of resistance R. Let R G be the gain varying
resistor with different values of resistance.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & V2 to the non-inverting terminals of first & second
Op-amp respectively.
4. By varying the value of RG, measure the output voltage Vo. Then Use the theoretical

formula Vo= (R2/R1)(1+(2Ra /RGain)) (V2 - V1)

5. Plot the graph between the various values of R G and Vo.

TABULATION:-

V0 IN VOLTS
RGain
S.No
(KΩ)
Practical
1. 10k 1.4
2. 20k 1.2
3. 30k 1
4. 40k 0.8
5. 50k 0.6
SNAPSHOTS:

RESULT:-
Thus the construction and testing of a 3 op-amp instrumentation amplifier using op-amp IC741 is
carried out. And also proved that the output voltage is dependent on the single gain variable resistor.
CIRCUIT DIAGRAM:
LOWPASS FILTER

HIGHPASS FILTER

BANDPASS FILTER
ACTIVE LOW PASS, HIGH PASS AND BAND PASS FILTER USING OP-AMP.

EXP.No: 04 DATE:
AIM:-
To design an Active Low Pass, High Pass and Band Pass Filter using op-amp and
test their performance

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 --- 02
1.5 KΩ 02
2. RESISTORS 10KΩ 01
22KΩ 04
5. CAPACITORS 0.1μf, 0.01μf 01
6. DIGITAL TRAINER KIT --- 01
7. SIGNAL GENERATOR (0-3)MHz 01
8. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
9. CONNECTING WIRES --- FEW

THEORY :
LPF

A filter circuit which allows only low frequency range up to a higher cut-off frequency f H is
called as Low Pass Filter. An active filter uses transistor and components such as resistor & capacitor for its
design. An active filter offers the following advantages over a passive filter.
1. Gain & frequency adjustment flexibility.
2. No loading problem because of high input impedance & low output impedance.
3. More economical because of variety of op-amps and absence of inductors.

From the frequency response, when f < f H; the gain is maximum │A│. When f = f H; the gain is 70.7%

|A|
of the maximum gain √2 and when f ¿ fH; the gain drops or rolls off. The frequency range from 0 to fH
is called as Passband & fH to ∞ is called as Stopband. Out of Butterworth, Chebyshev & Cauer filters,
Butterworth filter is preferred because it has flat pass band as well as flat stop band (flat-flat) filter.

HPF
An active high pass filter is simply formed by interchanging the frequency determining resistor and capacitor
in lowpass filter. A filter circuit which allows only high frequency range greater then a lower cut-off
frequency fL is called as HIGH PASS FILTER. From the frequency response, when f < f L; the gain gradually

|A|
increases from the lowest value. When f = f L; the gain reaches 70.7% of the maximum gain √2 and when
f > fL, the gain is maximum │A│. The frequency range from 0 to f L is called as Stopband & fL to ∞ is called
as Passband. (This is exactly opposite to active LPF)The order of the filter tells the roll-off rate at stop band.
Order n = 1 indicates -20dB / dec (-6db / octave); Order n = 2 indicates -40dB / dec & so on. Higher the order
of the filter, better the quality will be & complex the circuit will be.
BPF
A filter which has a pass band between two cut-off frequencies f H & fL is called as Bandpass filter. Where fH >
fL BPF is basically of two types
(i) Wide band pass filter. (ii) Narrow band pass filter.
Based on figure of merit or quality factor Q, the types are classified as follows. If Q < 10, selectivity is poor &
allows higher bandwidth & such BPF is called as wide BPF.
If Q > 10, selectivity is more and allows only narrow bandwidth & such BPF is called as
Narrow BPF. Relationship between Q & center frequency f C is given as
fc fc
Q= =
BW f H −f L &
f c= √ f H f L
When frequency fL < f < fH then gain is maximum. At f < f L the gain is gradually increasing
(Positive roll-off) from lower value & at f > f H the gain is gradually decreasing (Negative roll-off) & exactly

|A|
when f = fL & f = fH the gain is 70.7% of maximum gain √2 .
LPF
MODEL GRAPH:
HPF

BPF
PROCEDURE:
LPF & HPF

1. Connect the circuit as shown in the circuit diagram.

2. Select the corresponding cut-off frequency (higher or lower) and determine the value of C
& R. select the value of R1 & Rf depending on desired passband gain Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of op-amp.
4. Tabulate the output voltage Vo with respect to different values of input frequency.
5. Calculate passband gain and plot the graph of frequency versus voltage gain.
BPF
1. Select the lower and higher cut-off frequency and calculate the value of R & C for the
given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing the HPF
followed by a LPF (i.e.) HPF in series with LPF.
3. Connect the circuit as shown in the circuit diagram.
4. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of op-amp.
5. Tabulate the output voltage Vo with respect to different values of input frequency.
6. Calculate passband gain and plot the graph of frequency versus voltage gain & check the
graph to get approximately the same characteristic as shown in the model graph.

DESIGN:
LPF
Design a LPF at cutoff frequency fH of 1KHz with a passband gain of 2.
1. Choose the given value of fH = 1KHz.

2. Select the value of C < 1μf

1
3. Assume C = 0.1μf. Calculate R from fH = 2 π RC
1
R=
2 πf H C

1
3
R = 2 πX 1 X 10 X 0. 1μf = 1.5KΩ
R = 1.5KΩ C = 0.1μf

4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 + R 1 = 2.
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22KΩ & Assume RL = 10KΩ

5. Calculate the practical gain in dB using Gain (dB)=20log (Vo/Vin);

Vo Af
| |
Theoretical gain is given as Vin = √1+( f / f H )2
Af – P.B gain.
f – Input frequency.
fH – Higher cut-off frequency of LPF.
HPF
Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same procedure as LPF & interchange
the R & C position with capacitor first & resistor in parallel to capacitor where the other end connected to
ground.

Vo Af ( f / f L)
| |
In high pass filter Theoretical gain is given as Vin = √1+( f / f H )2
BPF
Design a BPF to pass a band of 1 KHz to 10 KHz with a passband gain of 4.
1. Select the highest cut-off frequency of LPF as f H = 10 KHz and the lowest cut-off frequency of HPF as
fL = 1 KHz.
2. Design the HPF first by taking fL = 1KHz. Assume the value of C < 1μf.
Let C = 0.1μf.
3. Calculate R from the expression.
1 1
fL = 2 π RC ; Therefore R1 =
2 πf L C
1
−6
R = 2 π (1KHz )(0.1 X 10 ) ;
R = 1.59K Ω ≈ R=1.5KΩ
4. Then design the LPF by taking fH = 10KHz. Assume the value of C < 1μf. Let C = 0.01μf.

1 1
5. Calculate R from the expression f H = 2 π RC ; Therefore R =
2 πf H C

1
−6
R = 2 π (10 KHz)(0.01 X 10 ) ;
R = 1.59KΩ ≈ R=1.5KΩ
6. Calculate the values of Rf & R1 with the use of pass band gain.

Overall P.B gain of BPF = 4 = 2 (HPF) X 2 (LPF)

Therefore for both HPF & LPF the value of R f = R1 to obtain a individual P.B gain of 2. Af = (1+

Rf
)
R 1 = 2 (for HPF)
Rf
)
Af = (1+ R 1 = 2 (for LPF)
Let Rf = R1 = 22KΩ.

fc fc
7. Q of the filters is calculated as B .W = f H −f L

Where fC = √f H f L is the center frequency.

8. Cascade HPF & then LPF to form BPF.
Calculate the practical gain dB using 20 log (Vo/Vin)
f
Af T ( )
fL
Vo f 2 f
And Theoretical gain is
| |
Vin = √ [ 1+(
fH
) ][ 1+ ( )2 ]
fL

TABULATION:
LPF
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1. 100 4 6
2. 200 3.9 5.8
3. 300 3.8 5.5
4. 500 3.6 5.1
5. 800 3.5 4.8
6. 1K 2.9 3.2
7. 2K 2 0
8. 3K 1.4 -3.0
9. 7K 0.7 -9.1
10. 10K 0.5 -12.0
 HPF
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1. 100 0.5 -12.0
2. 200 0.7 -9.1
3. 300 1.4 -3.0
4. 500 2 0
5. 800 2.9 3.2
6. 1K 3.5 4.8
7. 2K 3.6 5.1
8. 3K 3.8 5.5
9. 7K 3.9 5.8
10. 10K 4 6

BPF
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1. 100 0.6 -10.4
2. 200 1 -6.0
3. 300 2 0
4. 500 3 3.5
5. 1K 4 6.0
6. 3K 2.5 1.9
7. 10K 1.5 -2.4
8. 30K 0.8 -7.9
9. 70K 0.3 -16.4
10. 10K 0.1 -26.0
SNAPSHOTS:
LPF
HPF
 BPF

RESULT:

Thus an Active Lowpass, High pass and Band Pass Filters are designed and tested using op-amp IC
741.
CIRCUIT DIAGRAM:
ASTABLE MULTIVIBRATOR

MONOSTABLE MULTIVIBRATOR

SCHMITT TRIGGER
+15v

ROM=R1//R 2 7
2 -
IC 741
6
10KΩ 3 + 4
+
-15V RL=10 +
Vi
n
~ K CRO
R2=100
-
R K
1 10K
 ASTABLE, MONOSTABLE MULTIVIBRATOR AND
SCHMITT TRIGGER USING OP-AMP.

EXP.No: 05 DATE:

AIM:-
To design an Astable, Monostable multivibrator and Schmitt trigger using op-amp IC 741
and to test their characteristics.

APPARATUS REQUIRED:-

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 --- 01
100Ω, 100KΩ,
EACH 01
2. RESISTORS 22 KΩ
10KΩ, 47KΩ, EACH 03
4. CAPACITORS 0.01μf, 0.1μf 01
5. DIODE 1N4007 02
6. DIGITAL TRAINER KIT --- 01
7. SIGNAL GENERATOR (0-3)MHz 01
8. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
9. CONNECTING WIRES --- FEW

THEORY
ASTABLE MULTIVIBRATOR

An op-amp Astable multivibrator is also called as free running oscillator. The basic principle
of generation of square wave is to force an op-amp to operate in the saturation region (±Vsat). A fraction β

R2
= R 1+R 2 of the output is feedback to the positive input terminal of op-amp. The charge in the
capacitor increases & decreases upto a threshold value called ±βVsat. This charge in the capacitor triggers
the op-amp to stay either at +Vsat or –Vsat. Asymmetrical square wave can also be generated with the help
of zener diodes. Astable multivibrator do not require a external trigger pulse for its operation & output
toggles from one state to another and does not contain a stable state. Astable multivibrators are mainly
used in timing applications & waveforms generators.
 MONOSTABLE MULTIVIBRATOR
A multivibrator which has only one stable and the other is quasi-stable state is called as Monostable
multivibrator or one-short multivibrator. This circuit is useful for generating single output pulse of
adjustable time duration in response to a triggering signal. The width of the output pulse depends only on
the external components connected to the op-amp. Usually a negative trigger pulse is given to make the
output switch to other state. But, it then returns to its stable state after a time interval determined by
circuit components. The pulse width T can be given as T = 0.69RC. For Monostable operation the triggering
pulse width Tp should be less then T, the pulse width of Monostable multivibrator. This circuit is also called
as time delay circuit or gating circuit.
SCHMITT TRIGGER
A circuit which converts a irregular shaped waveform to a square wave or pulse is called a Schmitt trigger or
squaring circuit. The input voltage V in triggers the output Vo every time it exceeds certain voltage levels
called upper threshold voltage VUT and lower threshold voltage VLT. The threshold voltages are obtained by
using the voltage divider. A comparator with positive feedback is said to exhibit hysteresis, a dead band
condition. The hysteresis voltage is the difference between V UT & VLT.
There are two types of Schmitt trigger based on where the irregular wave is given. They are,
Inverting & non-inverting Schmitt trigger. Schmitt trigger finds application in wave shaping circuits. The
other name given to Schmitt trigger is regenerative comparator.
MODEL GRAPH:
ASTABLE MULTIVIBRATOR
MONOSTABLE MULTIVIBRATOR

SCHMITT TRIGGER
PROCEDURE:
ASTABLE MULTIVIBRATOR
1.Calculate the value of components using the design procedure given.
2. Connect the circuit as per as the circuit diagram.
3. As there is no specific input signal for this circuit switch ON the power supply.
4. Note down the reading for output square wave (i.e.) time & amplitude and tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
MONOSTABLE MULTIVIBRATOR
1.Calculate the value of components using the design procedure given.
2. Connect the circuit as per as the circuit diagram.
3. Apply the negative trigger voltage to the non-inverting terminal.
4. Note down the reading for output voltage Vo & ON & OFF time period & tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
SCHMITT TRIGGER
1.Design the value of circuit components and select V UT & VLT as given in the design
procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the input signal to the input terminal of op-amp & set V UT & VLT values.
4. Note down the readings from the output waveform.
5. Plot the graph & show the relationship between Input sine wave & Output square wave.

DESIGN:
ASTABLE MULTIVIBRATOR
Design of square wave generator at f0 = 1 KHz.

1. The expression of fo is obtained from the charging period t 1 & t2 of capacitor as fo =

1
2 RC ln [1+(2 R1 / R2 )]
2. To simplify the above expression, the value of R1 & R2 should be taken as
1
R2 = 1.16R1, such that fo simplifies to fo = 2 RC
 3. Assume the value of R1 = 10KΩ and find R2.
R2 = 1.16KΩ (10K) = 11.6KΩ ( Use a DRB)
Adjust the value of R2 till 22 KΩ for getting better output.
1
4. Assume the value of C & Determine R from f o = 2 RC
Let C = 0.01μf
1 1
R=
2 f oC 3 −6
= 2 X (1 X 10 )(0.01 X 10 )

R = 50KΩ ≈ 47KΩ

5. Calculate the threshold point from

R1
│VT│or│βVSAT│ = R 1+R 2 │βVSAT│ where β is the feedback ratio.
MONOSTABLE MULTIVIBRATOR

1. Assume R1 = R2 = 10KΩ & calculate β from expression

R1 10 K
β= R 1+R 2 = 20 K = 0.5.
2. Find the value of R & C from the pulse width time expression.
(1+V D /V sat )
T = RC ln 1−β
(1+V D /V sat )
T = RC ln 0.5
T ≡0.69RC.

3. Assume C = 0.01μf and R = 50KΩ ≈ 47KΩ. Find T where Rf = R & R3=10K

T = 0.69 (50X10 3) (0.01X10-6)
T = 0.345ms.
4. Triggering pulse width Tp must be much smaller than T. Tp < T.
5. Assume a HPF in the input session with C 1=0.1μf (Assumption) & R4 = 100Ω.
 SCHMITT TRIGGER
1. Select the desire value of Vut & Vlt with same magnitude & opposite polarity. Let V ut = 1V & Vlt = -1V.

2. For Op-amp 741C ± Vsat ≡ ±13V to ± 14V. And assume Vref = 0, Since the another end of R 1 is
grounded.

3. If Vo = +Vsat the voltage at the positive terminal will be (voltage from potential divider R 1 & R2).
R1
Vut = Vref + R 1 + R2 (Vsat - Vref)
Therefore Vref = 0.

R1+R2 ¿
R1 ¿ ¿
Vut = ¿ (+ Vsat).
R1
4. Similarly Vlt will be Vlt = ( R 1 + R2 ) – Vsat.
5. Sub Vut & assume R1 or R2 & find the other component value.
R1
1V = R 1 + R2 (13)

R1 + R2 = 13R1
R2 = 12R1 if R1 = 10K then R2 = 120K ≡100K.
6. Calculate ROM by
R1 R2 (10 K Ω)(100 K Ω)
ROM = R1 // R2 = R 1 + R2 110 K Ω .
1000 K Ω
ROM = 110 K Ω ≡ 10KΩ. & select RL = 10KΩ (Assumption)
7. Calculate hystersis voltage
Vhy = Vut – Vlt
R1
= R 1 + R2 [+Vsat – (-Vsat)]

10 K
= 110 K [26V] Since |Vsat| = 13V
= 0.0909 [26V]
Vhy = 2.363V
TABULATION:
ASTABLE MULTIVIBRATOR

DESIGN VALUE OBSERVED VALUE

Amplitude
Waveforms tH tL t f tH tL t f
(volts)
(ms) (ms) (ms) (Hz) (ms) (ms) (ms) (Hz)
Output
Square
waveform Vo 1.2 0.2 0.6 0.8 1.25 0.2 0.6 0.8 1.25
(CRO
Channel 1)
Capacitive
waveform
Vc 0.4 0.2 0.6 0.8 1.25 0.2 0.6 0.8 1.25
(CRO
Channel 2)

MONOSTABLE
Amplitude Time period
S.No Waveforms
(volts) (ms)
1. Input waveform -1.2 1

2. Output waveform 1.2 1

SCHMITT TRIGGER

I/P Voltage I/P Time VUT (UTP) VLT (LTP) O/P Voltage O/P Time
(Volts) (ms) (Volts) (Volts) (ms) (ms)

0.2 1 0.1 -0.1 1.2 1.19

SNAPSHOTS:
ASTABLE MULTIVIBRATOR
MONOSTABLE MULTIVIBRATOR
 SCHMITT TRIGGER

RESULT:-
Thus an Astable, Monostable multivibrator and Schmitt trigger are designed and tested using op-
amp IC 741.
CIRCUIT DIAGRAM:

RC PHASE SHIFT OSICILLATOR

WEIN BRIDGE OSICILLATOR

R1=10 Rf=22
K K
+15v

2 - 7
IC 741
3 + 4
6
R=1.5K C=0.1uf
-15v +
CRO
R=1.5K -
C=0.1uf
 RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR
USING OP-AMP

EXP.No: 06 DATE:
AIM:-
To design RC Phase Shift and Wien Bridge Oscillator using Op-amp IC 741 and to test its
performance.
APPARATUS REQUIRED:-

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 --- 01
1.5KΩ 3.3KΩ, 33KΩ, EACH 03
2. RESISTORS
10 KΩ 22 KΩ, 1.5MΩ, EACH 01

4. CAPACITORS 0.1μf 03
5. DIGITAL TRAINER KIT --- 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

THEORY:-
RC PHASE SHIFT OSCILLATOR
RC phase shift oscillator produces 360° of phase shift in two parts. Firstly, each and every RC pair in
the feedback network produces 60° phase shift and totally there were three pairs, thus producing 180°
Phase shift and secondly, the feedback input is given to the inverting terminal of op-amp to produce
another 180° phase shift and a total phase shift of 360°. It is used to produce low frequency output.
1
The frequency of oscillation is given by f 0 = 2 π √ 6 RC ; If an inverting amplifier is used, the gain must be

atleast equal to 29 to ensure the oscillations with constant amplitude that is, V |A β|
< 1. Otherwise the
oscillation will die out.
WEIN BRIDGE OSCILLATOR
A bridge circuit with two components connected in series and parallel combination is used to archived the
required of phase shift of 00. When the bridge is balanced the phase shift of 0 0 is achieved and the feedback
signal is connected to the positive terminal of Op-amp. So the Op-amp is acting as a non-inverting amplifier
and the feedback network do not provide any phase shift. The frequency of oscillation is given as f 0 =

1
2 π RC
MODEL GRAPH:
RC PHASE SHIFT OSCILLATOR

Vout

OUTPUT Time (ms)

WEIN BRIDGE OSCILLATOR

Vout

OUTPUT Time (ms)

PROCEDURE:
Common for RC PHASE SHIFT & WIEN BRIDGE OSCILLATOR
1.Select the given frequency of oscillation f 0 for the respective oscillator

2.Assume either R or C to find out the other using formula f 0

3.The gain is selected such that Rf/ R1= 29 for RC Phase shift and Rf/ R1=2 for wien bride oscillator. Assume Rf
or R1 to find the value of other component.

4.Connect the circuit as per as the circuit diagram. Measure the amplitude and frequency of the output
signal and finally plot the graph.
 DESIGN:
RC PHASE SHIFT OSCILLATOR

Design a RC phase shift oscillator to oscillate at 200Hz.

1.Select fo = 200Hz. Assume C = 0.1μf & determine R from f o.
1 1
fo = 2 π √ 6 RC = R = 2 π √ 6 f oc = 3.3K.
2.To prevent the loading of amp because it is necessary that R 1>>10R.
Therefore R1=10R=33K.
3.At this frequency the gain must be atleast 29 (i.e.) R f / R1 =29. Therefore Rf = 29R1.
Rf = 29 (33K) = 957KΩ. Therefore use Rf = 1MΩ
WEIN BRIDGE OSCILLATOR
(i) Select frequency f0 = 1 KHz.
1
(ii) Use f0 = 2 π RC , A = 1+ (Rf / R1) = 3. To find R & Rf.
(iii) Therefore Rf = 2R1 & assume C = 0.1μf & find R from
1
R=
2 πf o C = 1.59KΩ.
(iv) Assume R1 = 10K & find Rf from Rf = 2R1
Therefore Rf = 20K ≡ 22KΩ

TABULATION:
RC PHASE SHIFT OSCILLATOR

OBSERVED OUTPUT WAVEFORM

Amplitude Time period Frequency Design Frequency

(volts) (ms) (Hz) (Hz)

1.2 5 200 200

WEIN BRIDGE OSCILLATOR

OBSERVED OUTPUT WAVEFORM

Amplitude Design Frequency
Time period Frequency (Hz)
(volts)
(ms) (Hz)
 1.2 1 1K 1K

SNAPSHOTS:
RC PHASE SHIFT OSCILLATOR
 WEIN BRIDGE OSCILLATOR

RESULT:-

Thus RC Phase Shift and Wien Bridge Oscillator were designed and tested using op-amp IC
741.
CIRCUIT DIAGRAM:
ASTABLE MULTIVIBRATOR USING 555 TIMER

MONOSTABLE MULTIVIBRATOR USING 555 TIMER

 ASTABLE & MONOSTABLE MULTIVIBRATOR
USING IC 555 TIMER.

EXP.No: 07 DATE:
AIM:-
To Design and test Astable and Monostable multivibrator using 555 timer IC.

APPARATUS REQUIRED:-

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 555 --- 01

2. RESISTORS 3.3KΩ, 6.8KΩ, 10KΩ. EACH 01

3. CAPACITORS 0.1μf, 0.01μf. EACH01

4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

THEORY:-
ASTABLE MULTIVIBRATOR USING 555 TIMER
When the power supply V CC is connected, the external timing capacitor ‘C” charges towards V CC with
a time constant (RA+RB) C. During this time, pin 3 is high (≈V CC) as Reset R=0, Set S=1 and this combination

makes Q = 0 which has unclamped the timing capacitor ‘C’.

When the capacitor voltage equals 2/3 V CC, the upper comparator triggers the control flip flop on

that Q =1. It makes Q1 ON and capacitor ‘C’ starts discharging towards ground through R B and transistor
Q1 with a time constant RBC. Current also flows into Q1 through R A. Resistors RA and RB must be large
enough to limit this current and prevent damage to the discharge transistor Q1. The minimum value of R A is
approximately equal to VCC/0.2 where 0.2A is the maximum current through the ON transistor Q1.
During the discharge of the timing capacitor C, as it reaches V CC/3, the lower comparator is triggered

and at this stage S=1, R=0 which turns Q =0. Now Q =0 unclamps the external timing capacitor C. The
capacitor C is thus periodically charged and discharged between 2/3 V CC and 1/3 VCC respectively. The length
of time that the output remains HIGH is the time for the capacitor to charge from 1/3 V CC to 2/3 VCC.
The capacitor voltage for a low pass RC circuit subjected to a step input of V CC volts is given by VC = VCC
[1- exp (-t/RC)]
Total time period T = 0.69 (RA + 2 RB) C
f = 1/T = 1.44/ (RA + 2RB) C
 MONOSTABLE MULTIVIBRATOR USING 555 TIMER
A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-generating circuit in
which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In
a stable or stand by mode the output of the circuit is approximately Zero or at logic-low level. When an
external trigger pulse is given, the output is forced to go high ( ¿ VCC). The time for which the output
remains high is determined by the external RC network connected to the timer. At the end of the timing
interval, the output automatically reverts back to its logic-low stable state. The output stays low until the
trigger pulse is again applied. Then the cycle repeats. The Monostable circuit has only one stable state
(output low), hence the name Monostable. Normally the output of the Monostable Multivibrator is low.

MODEL GRAPH:
ASTABLE MULTIVIBRATOR USING 555 TIMER
 MONOSTABLE MULTIVIBRATOR USING 555 TIMER

PROCEDURE:
ASTABLE MULTIVIBRATOR USING 555 TIMER

1.Calculate the component values using the design procedure.

2.Connect the circuit as shown in the circuit diagram.
3.Observe and note down the output waveform.
4. Measure the frequency of oscillation and duty cycle and then compare with the given values.
5.Plot both the waveforms to the same time scale in a graph.

MONOSTABLE MULTIVIBRATOR USING 555 TIMER

1. Calculate the value of R & C using design procedure.

2. Connect the circuit as shown in the circuit diagram.
3. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
4. Observe the output waveform and measure the pulse duration.
5. Theoretically calculate the pulse duration as T high=1.1 RAC
DESIGN:
ASTABLE MULTIVIBRATOR USING 555 TIMER

Design of Astable multivibrator of operation frequency = 1 KHz & duty cycle of 30% using 555 timer IC.
Given Frequency=1000Hz
Duty cycle=30%

D= T low/T high = RB/(RA+2RB)*100 ----------------------------------- (1)

T high =0.69(RA+RB) C
T low = 0.69 RBC
From equation 1
0.30 T high = T low
0.30 * 0.69(RA+RB)C = 0.69 RBC
0.207(RA+RB)C = 0.69 RBC

-
0.483 RB 0.207 RA= 0 ------------------------------------------------- (2)

Given f=1 kHz we know that T=1/f

T=1ms
T= T high + T low
0.69(RA+RB) C +0.69 RBC= 1ms.
0.69(RA+RB) +0.69 RB = 1ms/C
Let C=0.1μF
0.69RA+0.69RB +0.69 RB = 1ms./0.1*10-6
0.69RA+1.38RB = 10 4 ------------------------------------------------ (3)
Solving equation 2 & 3 we get
RA=6.8K
RB= 2.674K≡3.3KΩ
MONOSTABLE MULTIVIBRATOR USING 555 TIMER

Let, RA = 10K

Out put pulse width tp = 10μs

tp = 1.1RAC
C= 0.909μF
C=0.1μF
TABULATION:
ASTABLE MULTIVIBRATOR USING 555 TIMER

DESIGN VALUE OBSERVED VALUE

Amplitude
Waveforms
(volts) tH tL t f tH tL t f
(ms) (ms) (ms) (Hz) (ms) (ms) (ms) (Hz)

Output
waveform 5 0.7 0.15 0.85 1.2K 0.7 0.15 0.85 1.2K
Vo

Capacitor
waveform
3 0.6 0.3 0.9 1.1K 0.6 0.3 0.9 1.1K
(Capacitor
voltage Vc)

MONOSTABLE MULTIVIBRATOR USING 555 TIMER

Amplitude Time period

S.No Waveforms
(volts) (ms)

1. Input waveform 4 3

2. Output waveform 5 2

Capacitive waveform
3. 3 2
(Capacitor voltage Vc)
SNAPSHOTS:
ASTABLE MULTIVIBRATOR USING 555 TIMER
 MONOSTABLE MULTIVIBRATOR USING 555 TIMER

RESULT:

Thus the Astable and Monostable multivibrator is designed and tested using 555 timer IC.
CIRCUIT DIAGRAM:

PLL CHARACTERISTICS:
 PLL CHARACTERISTICS AND FREQUENCY
MULTIPLIER USING PLL

EXP.No: 08 DATE:
AIM:-
To test the characteristics of PLL and design Frequency Multiplier using PLL IC565.

APPARATUS REQUIRED:-

S.NO COMPONENTS / EQUIPMENT VALUE QUANTITY

1 IC 565, IC 7490, BC107 / 2N 2222 --- 01
20 K, 2k, 6.8K,
3 RESISTORS Each one
4.7k, 10k

0.001μF, 0.01 μF Each one

CAPACITORS
4
1 μf ,10μf Each one

5 DIGITAL TRAINER KIT --- 01

6 DUAL POWER SUPPLY (0 -30V), 1A 1
7 CATHODE RAY OSCILLOSCOPE (0 – 30MHz) 1
8 CONNECTING WIRES --- FEW

THEORY:-
The frequency divider is inserted between the VCO and the phase comparator of PLL. Since the
output of the divider is locked to the input frequency f IN, the VCO is actually running at a multiple of the
input frequency .The desired amount of multiplication can be obtained by selecting a proper divide– by – N
network ,where N is an integer. To obtain the output frequency f OUT = 2fIN, N = 2 is chosen. One must
determine the input frequency range and then adjust the free running frequency f OUT of the VCO by means
of R1 and C1 so that the output frequency of the divider is midway within the predetermined input frequency
range. The output of the VCO now should be 2f IN . The output of the VCO should be adjusted by varying
potentiometer R1. A small capacitor is connected between pin7 and pin8 to eliminate possible oscillations.
Also, capacitor C2 should be large enough to stabilize the VCO frequency.
PLL AS FREQUENCY MULTIPLIER:-

MODEL GRAPH:-
PROCEDURE:-
a) PLL Characteristics
1. The connections are given as per the circuit diagram. Now measure the free running frequency of VCO at
pin 4, with the input signal Vin set equal to zero. Compare it with the calculated value = 0.25/(R T CT).
2. Now apply the input signal of 1 V PP Square wave at 1 KHz to pin 2. Connect one channel of the CRO to pin
2 and display this signal.
4. Gradually increase the input frequency till the PLL is locked to the input frequency. This frequency f1
gives the lower end of the capture range. Keep increasing the input frequency, till PLL tracks the input
signal, say to a frequency f2.This frequency f2 gives the upper end of the lock range. If input frequency is
increased further, the loop will get unlocked.
5. Now gradually decrease the input frequency till the PLL is again locked. This is the frequency f3, the upper
end of the capture range. Keep on decreasing the input frequency until the loop is unlocked. This frequency
f4 gives the lower end of the lock range.
6. The lock range ∆fL = (f2 – f4).Compare it with the calculated value of ± 7.8 fo / 12 . Also the capture range
is ∆fc = (f3 – f1).Compare it with the calculated value of capture range. ∆fc = ± (∆fL / (2π)(3.6)(10 3 ) C)1/2

b) PLL as frequency multiplier

1. The circuit is connected as per the circuit diagram.
2. use a 4 bit binary counter 7490 as a diver circuit ( divide by 5)
3. Measure the free running frequency of VCO at pin 4, when Vi = 0. Compare it with the
calculated value, fo = 0.25/(R TC T).
4. Vary the frequency of VCO by adjusting the 20KΩ potentiometer till the PLL is locked.
Measure the output frequency. It should be five times the input frequency. Tabulate the
input - output readings.

RESULT:-
Thus the PLL characteristics is tested and Frequency multiplier is designed successfully using PLL IC 565 .
CIRCUIT DIAGRAM:

Rf=2R

R = 10K +15v

R R R 7
2
-
IC 741
3 + 4
6

-15v
2R 2R 2R 2R 2R
-
V (0-10)V

+
b0 b1 b2 b3
INPUT - SWITCH
(ON-1 & OFF-0)
 R-2R LADDER TYPE DAC USING OP-AMP 741

EXP.No:- 09 DATE:

AIM:-
To design and test the operation of a 4 bit R – 2R ladder type digital to analog converter using op-
amp IC 741.

APPARATUS REQUIRED:-

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 --- 01
10 KΩ 03
2. RESISTORS
22KΩ 06
4. DIGITAL TRAINER KIT --- 01
5. VOLTMETER (0-10)V 01
6. CONNECTING WIRES --- Few

THEORY:-

Most DACs architectures are based on the popular R-2R ladder. Starting from the left hand side of
the circuit to the right hand side, one can easily prove that the equivalent resistance to the right of each
labeled node equals 2R. Consequently, the current flowing downward, away from each node equal to the
current flowing toward the right; twice this current enters the node from the left. The currents and, hence,
the node voltages are binary weighted.
With a resistance spread of only 2-to-1, R-2R ladders can be fabricated monolithically to a high
degree of accuracy and stability. Depending on how ladders are used, there were many DAC architectures
available. There were two common types of R-2R DACs available based on current or voltage.
They are Current mode DAC and Voltage mode DAC based on whether the circuit operated on
current or voltage respectively. The major advantage of R-2R ladder architecture when compared with the
binary weighted type is the use of only two value resistors. These two values R and 2R make the design
simple for any resolution and thus easily realizable as an integrated circuit.
MODEL GRAPH:-
0 1 0 1 1 0 1
0 0 1 1 0 1 1
0 0 0 0 1 1 1
0 0 0 0 1 1 1 Binary I/P

O/P VOLTAGE
(V)

PROCEDURE:
1. Select the given resolution as 24 = 16.
2. Assume the value of Resistor R and thus select another resistor with twice a value
of the first resistor (2R).
3. Connect the circuit as shown in the circuit diagram. Connect the series resistances
R finally to the inverting terminal of the op-amp.
4. Connect the other end of the parallel arm resistors 2R to the digital switch to
represent binary logic conditions.
5. Calculate the output voltage from the voltmeter. Since negative output results from
Op-amp, Connect the output of op-amp to the negative terminal of the voltmeter, to
get Positive deflections.
6. Plot the graph for output voltage versus input binary combinations and compare
the theoretical and practical output voltage to understand the deviation.
RESULT:-
Thus the R – 2R ladder type digital to analog converter is designed & tested using
op-amp IC 741.
CIRCUIT DIAGRAM - (LM723):-
 DC POWER SUPPLY USING LM317 AND LM723.

EXP.No: 10 DATE:

AIM:-
To design and test the power supply voltage regulator using LM317 and LM723 ICs.

APPARATUS REQUIRED:-

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. LM317 and LM723 --- EACH 01

30Ω, 100Ω, 1KΩ,

2. RESISTORS EACH 01
3.3KΩ, 220Ω,

3. DIGITAL TRAINER KIT --- 01

4. ANALOG VOLTMETER (0-10)V 01
5. DUAL POWER SUPPLY (0-30)V 01

THEORY:-
A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load current
and input voltage variations. Using IC 723, we can design both low voltage and high voltage regulators with
adjustable voltages.
For a low voltage regulator, the output VO can be varied in the range of voltages Vo < Vref, where as
for high voltage regulator, it is V o > Vref. The voltage Vref is generally about 7.5V. Although voltage regulators
can be designed using Op-amps, it is quicker and easier to use IC voltage Regulators.
IC 723 is a general purpose regulator and is a 14-pin IC with internal short circuit current limiting,
thermal shutdown, current/voltage boosting etc. Furthermore it is an adjustable voltage regulator which
can be varied over both positive and negative voltage ranges. By simply varying the connections made
externally, we can operate the IC in the required mode of operation. Typical performance parameters are
line and load regulations which determine the precise characteristics of a regulator.
C=220pf
MODEL GRAPH:-
CHARACTERISTICS OF THE LM317HVK:-

The LM317HVK will provide a regulated output current of upto 1.5A,Provided that if is not subjected
to a power dissipation of more than about 15W.This means it should be electrically isolated from, and
fastened to, a large heat sink such as the metal chassis of the power supply.
The LM317 requires a minimum “dropout” voltage of 3v across its input and output terminals or it
will drop out of regulation. Thus the upper limit of Vo is 3V below the minimum input voltage from the
unregulated supply.
It is good practice to connect bypass capacitors .This reduces the ripple voltage from the rectifier.
The LM317HVK protects itself against over heating, too much internal power dissipation and too
much current. When the chip temperature reaches 175 degrees, the 317 shuts down. If the product of
output current and input-to-output voltage exceeds 15 to 20W, or if currents greater than about 1.5A are
required the LM317 also shuts down. When the overload condition is removed the Operation is resumed. All
these features are made possible by the remarkable internal circuitry of LM317.
Along with the simple 3 pin fixed regulators; a number of adjustable or programmable devices are
available. Some devices also include features such as programmable current limiting. It is also possible to
configure multiple regulators so that they track or follow each other.

DESIGN PROCEDURE (IC723):-

Given :
Vref = 5v
Vo = 4v
We know that
Vo = Vref (R2/ (R1+R2))
4R1+4R2=5R2
R2=4R1
Let R1=1k
R2=4K ≈ 3.3KΩ
PIN DIAGRAM:-

CIRCUIT DIAGRAM - (LM317):-

3 2

MODEL GRAPH:-
PROCEDURE:-
1) Connections are made as per the circuit diagram.
2) The reference voltage of 5v is set and the input voltage is varied between (0-30) v
3) The corresponding output is taken using voltmeter.
4) The readings are tabulated and the graph is plotted.
DESIGN EXERCISE:-
1. Design an IC 723 based voltage regulator to get a regulated output of 3V for varying input.

2. Design an IC 723 based voltage regulator to get a regulated output of 5V for varying input.

3. Design an IC 317 based voltage regulator to get a regulated output of 6V for varying input.

4 Design an IC 723 based voltage regulator to get a regulated output of 5.5V for varying
input.

RESULT:
The 723 & 317 IC voltage regulators are designed and the regulation of supply voltage was
tested.
 SIMULATION EXPERIMENTS USING PSPICE

EX N0:11 DATE:
1.INVERTING AMPLIFIER

CIRCUIT DIAGRAM
CODE:

*INVERTING AMPLIFIER
IN 1 0 SIN(0V 2VPEAK 10KHZ)
R1 1 2 10K
RF 2 4 10K
XOA2 0 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.ENDS
.TRAN 5US 0.2MS
.PRINT TRAN V(1) V(4)
.PLOT TRAN V(1) V(4)
.PROBE
.END
SNAPSHOTS:
 2.NON-INVERTING AMPLIFIER
CIRCUIT DIAGRAM
CODE:

*NONINVERTING AMPLIFIER
VIN 3 0 SIN(0V 2VPEAK 10KHZ)
R1 2 0 10K
RF 2 4 10K
XOA2 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.ENDS
.TRAN 5US 0.2MS
.PLOT TRAN V(3) V(4)
.PROBE
.END
SNAPSHOTS:
 3.DIFFERENTIAL AMPLIFIER

CIRCUIT DIAGRAM

R11=10Ω
CODE:

*DIFFERENTIAL AMPLIFIER
VIN1 1 0 SIN(0V 1VPEAK 10KHZ)
VIN2 5 0 SIN(0V 2VPEAK 10KHZ)
R1 1 2 10k
RF 2 4 100K
R2 3 0 100K
R11 3 5 10K
XOA2 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.ENDS
.TRAN 5US 0.2MS
.PLOT TRAN V(1) V(5) V(4)
.PROBE
.END
SNAPSHOTS:
 4.INTEGRATOR

CIRCUIT DIAGRAM:

RL=10K
CODE:

*OPAMP AS INTEGRATOR
VIN 1 0 SIN(0V 1VPEAK 200HZ)
R1 1 2 1.5K
RF 2 4 15K
CF 2 4 0.01UF
RCOMP 3 0 1.5K
RL 4 0 10K
XOA2 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
D1 4 7 DZ0
D2 0 7 DZ0
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.MODEL DZ0 D(IS=0.05U RS=0.1 BV=4.3 IBV=0.05U)
.ENDS
.TRAN 0.1MS 34MS
.PRINT TRAN V(1) V(4)
.PLOT TRAN VM(1) VP(4)
.PROBE
.END
SNAPSHOTS:
 5.DIFFERENTIATOR

CIRCUIT DIAGRAM

RCOM=100Ω
CODE:

*OPAMP AS DIFFERENTIATOR
VIN 9 0 AC 1 SIN(0 1 2KHZ)
R1 9 1 100
C1 1 2 0.1UF
CF 2 4 0.005PF
RF 2 4 1.5K
RCOM 3 0 100
R3 4 0 10K
XOA2 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
D1 4 7 DZ0
D2 0 7 DZ0
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.MODEL DZ0 D(IS=0.05U RS=0.1 BV=4.3 IBV=0.05U)
.ENDS
.TRAN 5US 500US
.PRINT TRAN V(1) V(4)
.PLOT TRAN V(1) V(4)
.PROBE
.END
SNAPSHOTS:
 6.INSTRUMENTATION AMPLIFIER
CIRCUIT DIAGRAM:
CODE:
*OPAMP AS INSTRUMENTATION AMPLIFIER
VDC 2 0 DC 1
VDC1 6 0 DC 1
R1 3 5 10K
R2 3 4 2.2K
R3 5 7 2.2K
R4 4 9 10K
R5 7 8 10K
Rf 9 10 10K
R6 8 0 10K
R7 10 0 10K
XOA1 2 3 4 OPAMP1
XOA2 6 5 7 OPAMP1
XOA3 9 8 10 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
D1 4 7 DZ0
D2 0 7 DZ0
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.MODEL DZ0 D(IS=0.05U RS=0.1 BV=4.3 IBV=0.05U)
.ENDS
.DC VDC 0.25 1.0 0.25
.PLOT DC V(10)
.PROBE
.END
SNAPSHOTS:
 7.LOW PASS FILTER
CIRCUIT DIAGRAM:
Code:

*OPAMP AS LPF
VIN 1 0 AC 1 SIN(0 1 2KHZ)
R1 2 0 27K
RF 2 4 20K
C1 3 0 0.1UF
R2 1 3 1.5K
RL 4 0 10K
XOA2 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
D1 4 7 DZ0
D2 0 7 DZ0
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.MODEL DZ0 D(IS=0.05U RS=0.1 BV=4.3 IBV=0.05U)
.ENDS
.AC DEC 20 1HZ 10KHZ
.PLOT AC V(4)
.PROBE
.END
Snapshots:
 8.HIGH PASS FILTER
CIRCUIT DIAGRAM:

R2=1.5K

CODE:
*OPAMP AS HPF
VIN 1 0 AC 1 SIN(0 1 2KHZ)
R1 2 0 27K
R2 3 0 1.5K
C1 1 3 0.1UF
RF 2 4 22K
RL 4 0 10K
XOA2 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
D1 4 7 DZ0
D2 0 7 DZ0
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.MODEL DZ0 D(IS=0.05U RS=0.1 BV=4.3 IBV=0.05U)
.ENDS
.AC DEC 20 1HZ 100KHZ
.PLOT AC V(4)
.PROBE
.END

SNAPSHOTS:
9.BAND PASS FLITER
CIRCUIT DIAGRAM:

CODE:
*OPAMP AS BPF
VIN 1 0 AC 1 SIN(0 1 1KHZ)
R1 2 0 27K
R2 3 0 1.5K
C1 1 3 0.1UF
RF 2 4 20K
RL1 4 9 1.5K
XOA1 3 2 4 OPAMP1
R11 10 0 27K
RF1 10 11 20K
C11 9 0 0.01UF
RL2 11 0 1.5K
X0A2 9 10 11 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
D1 4 7 DZ0
D2 0 7 DZ0
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.MODEL DZ0 D(IS=0.05U RS=0.1 BV=4.3 IBV=0.05U)
.ENDS
.AC DEC 10 1HZ 10MEG
.PLOT AC V(11)
.PROBE
.END

SNAPSHOTS:
10.ASTABLE MULTIVIBRATOR
CIRCUIT DIAGRAM:

C1=0.01µF

CODE:
*ASTABLE MULTIVIBRATOR
C1 2 0 0.01UF
RF 2 4 47K
R2 4 3 10MEG
R1 3 0 10K
XOA2 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
D1 4 7 DZ0
D2 0 7 DZ0
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.MODEL DZ0 D(IS=0.05U RS=0.1 BV=4.3 IBV=0.05U)
.ENDS
.TRAN 500NS 100US UIC
.IC V(3)=5V V(2)=0V
IS 0 3 PWL(0US 0MA 10US 0.1MA 40US 0.1MA 50US 0MA 10MS 0MA)
.PRINT TRAN V(4) V(2) V(3)
.PLOT TRAN V(4) V(2) V(3)
.PROBE
.END

SNAPSHOTS:
11.SCHMITT TRIGGER
CIRCUIT DIAGRAM:

CODE:
*SCHMITT TRIGGER
VIN 1 0 SIN(0V 3VPEAK 100HZ)
R1 3 0 10K
R2 4 3 100K
R3 1 2 10K
RL 4 0 10K
XOA2 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 100K
CP1 4 0 0.0159UF
D1 4 7 DZ0
D2 0 7 DZ0
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.MODEL DZ0 D(IS=0.05U RS=0.1 BV=4.3 IBV=0.05U)
.ENDS
.TRAN 0.1MS 34MS
.PRINT TRAN V(1) V(4)
.PLOT TRAN V(1) V(4)
.PROBE
.END

SNAPSHOTS:
12.RC PHASE SHIFT OSCILLATOR
CIRCUIT DIAGRAM:

CODE:
*RC PHASE SHIFT OSCILLATOR
IS 0 3 PWL(0US 0MA 5US 0.1UA 10US 0.1UA 50US 0MA 1MS 0MA)
R1 1 2 33K
R2 1 0 3.3K
R3 5 0 3.3K
R4 8 0 3.3K
RF 3 0 33K
RFR1 2 4 1MEG
C1 1 5 0.1UF
C2 5 8 0.1UF
C3 8 4 0.1UF
XOP 3 2 4 OPAMP1
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 1K
CP1 4 0 1.5915UF
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.ENDS
.TRAN 0.5MS 10MS
.PRINT TRAN V(4)
.PLOT TRAN V(4)
.PROBE
.END

SNAPSHOTS:
 13.WEIN-BRIDGE OSCILLATOR
CIRCUIT DIAGRAM:
CODE:

*WIEN BRIDGE OSCILLATOR

IS 0 3 PWL(0US 0MA 10US 0.1MA 40US 0.1MA 50US 0MA 10MS 0MA)
R2 4 6 10K
C2 6 3 16NF
R1 3 0 10K
C1 3 0 16NF
R3 0 2 10K
R5 2 5 18K
XOP 3 2 4 OPAMP1
R6 5 4 5K
D1 5 4 DIN914
D2 5 4 DIN914
.model DIN914 D(Is=0.1p Rs=16 CJO=2p Tt=12n Bv=100 Ibv=0.1p)
.SUBCKT OPAMP1 1 2 6
RIN 1 2 10MEG
EGAIN 3 0 1 2 100K
RP1 3 4 1K
CP1 4 0 1.5915UF
EBUFFER 5 0 4 0 1
ROUT 5 6 10
.ENDS
.TRAN 0.05MS 10MS
.PRINT TRAN V(4)
.PLOT TRAN V(4)
.PROBE
.END
SNAPSHOTS: