YASH PATEL 190110116050
Assignment 01
1. What is a micro operation? List and explain its categories.
Solution:-
The operations executed on data stored in registers are called micro-operations. A micro-
operation is an elementary operation performed on the information stored in one or more
registers.
Types of Micro-Operations
The micro-operations in digital computers are of 4 types:
1. Register transfer micro-operations transfer binary information from one register to
another.
2. Arithmetic micro-operations perform arithmetic operations on numeric data stored in
registers.
Some of the basic micro-operations are addition, subtraction, increment and decrement.
Add Micro-Operation
It is defined by the following statement:
R3 → R1 + R2
The above statement instructs the data or contents of register R1 to be added to data or
content of register R2 and the sum should be transferred to register R3.
Subtract Micro-Operation
Let us again take an example:
R3 → R1 + R2' + 1
In subtract micro-operation, instead of using minus operator we take 1's compliment and add 1
to the register which gets subtracted, i.e R1 - R2 is equivalent to R3 → R1 + R2' + 1
Increment/Decrement Micro-Operation
YASH PATEL 190110116050
Increment and decrement micro-operations are generally performed by adding and subtracting
1 to and from the register respectively.
R1 → R1 + 1
R1 → R1 – 1
Symbolic Designation Description
R3 ← R1 + R2 Contents of R1+R2 transferred to R3.
R3 ← R1 - R2 Contents of R1-R2 transferred to R3.
R2 ← (R2)' Compliment the contents of R2.
R2 ← (R2)' + 1 2's compliment the contents of R2.
R3 ← R1 + (R2)' + 1 R1 + the 2's compliment of R2 (subtraction).
R1 ← R1 + 1 Increment the contents of R1 by 1.
R1 ← R1 - 1 Decrement the contents of R1 by 1.
3. Logic micro-operations perform bit manipulation operation on non-numeric data stored
in registers.
These are binary micro-operations performed on the bits stored in the registers. These
operations consider each bit separately and treat them as binary variables.
Let us consider the X-OR micro-operation with the contents of two registers R1 and R2.
P: R1 ← R1 X-OR R2
In the above statement we have also included a Control Function.
4. Shift micro-operations perform shift micro-operations performed on data.
These are used for serial transfer of data. That means we can shift the contents of the register
to the left or right. In the shift left operation the serial input transfers a bit to the right most
position and in shift right operation the serial input transfers a bit to the left most position.
There are three types of shifts as follows:
a) Logical Shift
YASH PATEL 190110116050
It transfers 0 through the serial input. The symbol "shl" is used for logical shift left and "shr" is
used for logical shift right.
R1 ← she R1
R1 ← she R1
The register symbol must be same on both sides of arrows.
b) Circular Shift
This circulates or rotates the bits of register around the two ends without any loss of data or
contents. In this, the serial output of the shift register is connected to its serial input. "cil" and
"cir" is used for circular shift left and right respectively.
c) Arithmetic Shift
This shifts a signed binary number to left or right. An arithmetic shift left multiplies a signed
binary number by 2 and shift left divides the number by 2. Arithmetic shift micro-operation
leaves the sign bit unchanged because the signed number remains same when it is multiplied
or divided by 2.
2. Define RTL. What do you mean by register transfer? Explain in
detail. Also discuss three state bus buffer.
Solution:-
Definition: The symbolic notation used to describe the microoperation transfers among registers
is called a register transfer language.
The term "register transfer" implies the availability of hardware logic circuits that can perform a
stated microoperation and transfer the result of the operation to the same or another
register.
The word "language" is borrowed from programmers, who apply this term to programming
languages.
A register transfer language is a system for expressing in symbolic form the microoperation
sequences among the registers of a digital module.
It is a convenient tool for describing the internal organization of digital computers in concise
and precise manner.
It can also be used to facilitate the design process of digital systems.
Information transfer from one register to another is designated in symbolic form by means
of a replacement operator.
The statement below denotes a transfer of the content of register R1 into register R2.
R2 ← R1
A statement that specifies a register transfer implies that circuits are available from the outputs
of the destination register has a parallel load capability.
Every statement written in a register transfer notation implies a hardware construction for
YASH PATEL 190110116050
implementing the transfer.
Three state bus buffer Definition:
A three state bus buffer is an integrated circuit that connects multiple data sources to a single
bus. The open drivers can be selected to be either a logical high, a logical low, or high
impedance which allows other buffers to drive the bus.
Now, let’s see the more detailed analysis of a 3-state bus buffer in points:
1. As in a conventional gate, 1 and 0 are two states.
2. Third state is a high impedance state.
3. The third state behaves like an open circuit.
4. If the output is not connected, than there is no logical significance.
5. It may perform ant type of conventional logic operations such as AND, OR, NAND, etc.
Difference between normal buffer and three-state buffer:
It contains both normal input and control input. Here, the output state is determined by the
control input.
When the control input is 1, the output is enabled and the gate will behave like conventional
buffer.
When the control input is 0, the output is disabled and the gate will be in high impedance
state.
To form a single bus line, all the outputs of the 4 buffers are connected together.
The control input will now decide which of the 4 normal inputs will communicate with the bus
line.
The decoder is used to ensure that only one control input is active at a time.
The diagram of a 3-state buffer can be seen as below.
Figure – Bus Line with three-state –buffers
YASH PATEL 190110116050
3. A digital computer has a common bus system for 16 registers of 32
bits each. The bus is constructed with multiplexers.
a) How many selection inputs are there in each multiplexer ?
b) What size of multiplexers are needed ?
c) How many multiplexers are there in the bus ?
Solution:-
a) How many selection input are there in each multiplexer?
2n=No. of Registers; n=selection input of multiplexer 2 n=16;
here n=4
Therefore 4 selection input lines should be there in each multiplexer.
b) What size of multiplexers is needed?
size of multiplexers= Total number of register X 1
= 16 X 1
Multiplexer of 16 x 1 size is needed to design the above defined common bus.
c) How many multiplexers are there in a bus? No.
of multiplexers = bits of register
= 32
32 multiplexers are needed in a bus.
4. Draw and explain flowchart for interrupt cycle
Solution:-
YASH PATEL 190110116050
The way that the interrupt is handled by the computer can be explained by means of the
flowchart shown in figure 2.13.
An interrupt flip-flop R is included in the computer.
When R = 0, the computer goes through an instruction cycle.
During the execute phase of the instruction cycle IEN is checked by the control.
If it is 0, it indicates that the programmer does not want to use the interrupt, so control
continues with the next instruction cycle.
If IEN is 1, control checks the flag bits.
If both flags are 0, it indicates that neither the input nor the output registers are ready for
transfer of information.
In this case, control continues with the next instruction cycle. If either flag is set to 1 while
IEN = 1, flip-flop R is set to 1.
At the end of the execute phase, control checks the value of R, and if it is equal to 1, it goes
to an interrupt cycle instead of an instruction cycle.
5. Draw the block diagram of control unit.
Solution:-
The Control Unit is classified into two major categories:
1. Hardwired Control
YASH PATEL 190110116050
2. Microprogrammed Control
Hardwired Control
The Hardwired Control organization involves the control logic to be implemented with gates,
flip-flops, decoders, and other digital circuits.
The following image shows the block diagram of a Hardwired Control organization.
Micro-programmed Control
The Microprogrammed Control organization is implemented by using the programming
approach.
In Microprogrammed Control, the micro-operations are performed by executing a program
consisting of micro-instructions.
The following image shows the block diagram of a Microprogrammed Control organization.
YASH PATEL 190110116050
YASH PATEL 190110116050
Assignment 02
1. Explain pipelining technique. Draw the general structure of four segment
pipeline.
Solution:-
Pipeline is a technique of decomposing a sequential process into sub operations, with each
sub process being executed in a special dedicated segment that operates concurrently with
all other segments.
A pipeline can be visualized as a collection of processing segments through which binary
information flows.
Each segment performs partial processing dictated by the way the task is partitioned.
The result obtained from the computation in each segment is transferred to the next segment
in the pipeline.
It is characteristic of pipelines that several computations can be in progress in distinct
segments at the same time.
The overlapping of computation is made possible by associating a register with each
segment in the pipeline.
The registers provide isolation between each segment so that each can operate on distinct
data simultaneously.
Any operation that can be decomposed into a sequence of sub operations of about the same
complexity can be implemented by a pipeline processor.
The technique is efficient for those applications that need to repeat the same task many
times with different sets of data.
The general structure of a four-segment pipeline is illustrated in Figure 1.
The operands pass through all four segments in a fixed sequence.
Each segment consists of a combinational circuit S, which performs a sub operation over the data
stream flowing through the pipe.
The segments are separated by registers R, which hold the intermediate results between the
stages.
Information flows between adjacent stages under the control of a common clock applied to all the
registers simultaneously.
We define a task as the total operation performed going through all the segments in the
pipeline.
YASH PATEL 190110116050
Figure 1: General Structure of Four-Segment Pipeline
2. Elaborate Flynn’s classification for computers.
Solution:-
M.J. Flynn proposed a classification for the organization of a computer system by the number of
instructions and data items that are manipulated simultaneously.
The sequence of instructions read from memory constitutes an instruction stream.
The operations performed on the data in the processor constitute a data stream.
Parallel processing may occur in the instruction stream, in the data stream, or both.
1. Single instruction stream, single data stream (SISD)
An SISD computing system is a uniprocessor machine which is capable of executing a single
instruction, operating on a single data stream. In SISD, machine instructions are processed in
a sequential manner and computers adopting this model are popularly called sequential
computers. Most conventional computers have SISD architecture. All the instructions and
data to be processed have to be stored in primary memory.
2. Single instruction stream, multiple data stream (SIMD)
An SIMD system is a multiprocessor machine capable of executing the same instruction on
all the CPUs but operating on different data streams. Machines based on an SIMD model are
well suited to scientific computing since they involve lots of vector and matrix operations. So
that the information can be passed to all the processing elements (PEs) organized data
elements of vectors can be divided into multiple sets(N-sets for N PE systems) and each PE
can process one data set.
YASH PATEL 190110116050
3. Multiple instruction stream, single data stream (MISD)
An MISD computing system is a multiprocessor machine capable of executing different
instructions on different PEs but all of them operating on the same dataset .Example Z =
sin(x)+cos(x)+tan(x)
The system performs different operations on the same data set. Machines built using the
MISD model are not useful in most of the application, a few machines are built, but none of
them are available commercially.
4. Multiple instruction stream, multiple data stream (MIMD)
An MIMD system is a multiprocessor machine which is capable of executing multiple
instructions on multiple data sets. Each PE in the MIMD model has separate instruction and
data streams; therefore machines built using this model are capable to any kind of
application. Unlike SIMD and MISD machines, PEs in MIMD machines work asynchronously.
3. Explain RISC. List its characteristics.
Solution:-
Reduced Instruction Set Architecture (RISC) –
The main idea behind is to make hardware simpler by using an instruction set composed of a few
basic steps for loading, evaluating, and storing operations just like a load command will load data,
store command will store the data. RISC: Reduce the cycles per instruction at the cost of the
number of instructions per program.
Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction comes undersize of one word.
3. Instruction takes a single clock cycle to get executed.
4. More number of general-purpose registers.
5. Simple Addressing Modes.
YASH PATEL 190110116050
6. Less Data types.
7. Pipeline can be achieved.
4.Write a detailed note on Direct Memory Access (DMA).
Solution:-
Direct Memory Access (DMA) transfers the block of data between the memory and peripheral
devices of the system, without the participation of the processor. The unit that controls the activity
of accessing memory directly is called a DMA controller.
The processor relinquishes the system bus for a few clock cycles. So, the DMA controller can
accomplish the task of data transfer via the system bus. In this section, we will study in brief about
DMA, DMA controller, registers, advantages and disadvantages.
In programmed I/O, the processor keeps on scanning whether any device is ready for data transfer.
If an I/O device is ready, the processor fully dedicates itself in transferring the data between I/O and
memory. It transfers data at a high rate, but it can’t get involved in any other activity during data
transfer. This is the major drawback of programmed I/O.
In Interrupt driven I/O, whenever the device is ready for data transfer, then it raises an interrupt to
processor. Processor completes executing its ongoing instruction and saves its current state. It then
switches to data transfer which causes a delay. Here, the processor doesn’t keep scanning for
peripherals ready for data transfer. But, it is fully involved in the data transfer process. So, it is also
not an effective way of data transfer.
The above two modes of data transfer are not useful for transferring a large block of data. But, the
DMA controller completes this task at a faster rate and is also effective for transfer of large data block.
Direct Memory Access Advantages and Disadvantages
Advantages:
1. Transferring the data without the involvement of the processor will speed up the read-write
task.
2. DMA reduces the clock cycle requires to read or write a block of data.
3. Implementing DMA also reduces the overhead of the processor.
Disadvantages
1. As it is a hardware unit, it would cost to implement a DMA controller in the system.
YASH PATEL 190110116050
2. Cache coherence problem can occur while using DMA controller.
5.Describe cache coherence problem and its solutions in detail.
Solution:-
For higher performance in a multiprocessor system, each processor will usually have its own cache.
Cache coherence refers to the problem of keeping the data in these caches consistent. The main
problem is dealing with writes by a processor.
There are two general strategies for dealing with writes to a cache:
Write-through - all data written to the cache is also written to memory at the same time.
Write-back - when data is written to a cache, a dirty bit is set for the affected block. The modified
block is written to memory only when the block is replaced.
Software solution:
In software approach, the detecting of potential cache coherence problem is transferred from
run time to compile time, and the design complexity is transferred from hardware to software.
On the other hand, compile time; software approaches generally make conservative decisions.
Leading to inefficient cache utilization.
Compiler-based cache coherence mechanism perform an analysis on the code to determine
which data items may become unsafe for caching, and they mark those items accordingly. So,
there are some more cacheable items, and the operating system or hardware does not cache
those items.
The simplest approach is to prevent any shared data variables from being cached. This is too
conservative, because a shared data structure may be exclusively used during some periods
and may be effectively read-only during other periods.
It is only during periods when at least one process may update the variable and at least one
other process may access the variable then cache coherence is an issue More efficient
approaches analyze the code to determine safe periods for shared variables. The compiler
then inserts instructions into the generated code to enforce cache coherence during the critical
periods.
Hardware solutions:
Hardware solution provide dynamic recognition at run time of potential inconsistency
conditions. Because the problem is only dealt with when it actually arises, there is more
effective use of caches, leading to improved performances over a software approach.
YASH PATEL 190110116050
Hardware schemes can be divided into two categories: directory protocol and snoopy
protocols.
Directory protocols:
Directory protocols collect and maintain information about where copies of lines reside.
Typically, there is centralized controller that is part of the main memory controller, and a
directory that is stored in main memory.
The directory contains global state information about the contents of the various local caches.
When an individual cache controller makes a request, the centralized controller checks and
issues necessary commands for data transfer between memory and caches or between
caches themselves.
It is also responsible for keeping the state information up to date, therefore, every local action
that can effect the global state of a line must be reported to the central controller.
The controller maintains information about which processors have a copy of which lines.
Before a processor can write to a local copy of a line, it must request exclusive access to the
line from the controller.
Before granting thus exclusive access, the controller sends a message to all processors with a
cached copy of this time, forcing each processors to invalidate its copy.
After receiving acknowledgement back from each such processor, the controller grants
exclusive access to the requesting processor.
When another processor tries to read a line that is exclusively granted to another processors, it
will send a miss notification to the controller.
The controller then issues a command to the processor holding that line that requires the
processors to do a write back to main memory.
Directory schemes suffer from the drawbacks of a central bottleneck and the overhead of
communication between the various cache controllers and the central controller.
Snoopy Protocols:
Snoopy protocols distribute the responsibility for maintaining cache coherence among all of the
cache controllers in a multiprocessor system.
A cache must recognize when a line that it holds is shared with other caches.
When an update action is performed on a shared cache line, it must be announced to all other
caches by a broadcast mechanism.
Each cache controller is able to “snoop” on the network to observed these broadcasted
notification and react accordingly.
Snoopy protocols are ideally suited to a bus-based multiprocessor, because the shared bus
provides a simple means for broadcasting and snooping.
YASH PATEL 190110116050
Two basic approaches to the snoopy protocol have been explored: Write invalidates or write-
update (write-broadcast)
With a write-invalidate protocol, there can be multiple readers but only one write at a time.
Initially, a line may be shared among several caches for reading purposes.
When one of the caches wants to perform a write to the line it first issues a notice that
invalidates that tine in the other caches, making the line exclusive to the writing cache. Once
the line is exclusive, the owning processor can make local writes until some other processor
requires the same line.
With a write update protocol, there can be multiple writers as well as multiple readers. When a
processors wishes to update a shared line, the word to be updated is distributed to all others,
and caches containing that line can update it.
