Session 7
Test Points
Internal Reset
ASIC_TEST D Q D Q
F2 F3
SE SE
...
Reset
Synchronizer
D Q D Q
0
SE SE
F0 F1
1
Internal Reset Line
RSTn Inactive During Scan
Now all the flip-flops can be included in scan chains
This is the default implementation used when
AutoFix is enabled
2nd solution
ASIC_TEST D Q D Q
F2 F3
SE SE
...
Reset
Synchronizer
D
SE
Q D
SE
Q
1-Injector
F0 F1
Internal Reset Line
Inactive During Scan
RSTn
Now all the flip-flops can be included in scan chains
SA1 fault on internal reset line is still untestable
Another Internal-Reset Solution
Network N 9
TEST_SE
ASIC_TEST D Q D Q
F2 F3
SE SE
...
Reset
Reset Line gated
Synchronizer
with a ScanEnable
signal (TEST_SE)
D Q D Q
SE SE
F0 F1 Internal Reset Line
Inactive During Shift
RSTn
All the flip-flops can be included in scan chains
Full test coverage on the internal reset line
Internal reset line is controlled by the Reset
Synchronizer output during scan capture
Autofix
The AutoFix feature can automatically fix DFT rule
violations associated with:
Uncontrollable clocks
Uncontrollable asynchronous set/reset signals
Three-state signals
Bidirectional signals
Logic Added by AutoFix
Data
In 0
Data
Out
Test 1
Data
Test- Pt
Enable
Test
Test Mode Mode
Test Point
Gate View
AutoFix adds a configurable test-point architecture
Exact implementation can vary during optimization
Examples of AutoFix Test Points
DIV_CLK 0 AutoFix MUXing
INT_CLK for Divided Clock
ATE_CLK 1 or Asynch
ASIC_TEST
INT_RSTn 0
AutoFix Reset MUX SYNC_RSTn
1
for Uncontrolled Reset PI_RSTn
(default option)
ASIC_TEST
INT_RSTn
AutoFix Reset Gate
ScanEnable
INT_RST_GATED -method gate
General Test Point Insertion
The AutoFix client can be used for specific types of
logic fixing
Other logic fixing requirements can be handled by
User Defined Test Points
User Defined Test Points (UDTP)
User Defined Test Points
UDTPs direct DFTC to insert control and observe
points at user specified locations in the design
Why use UDTP?
Fix uncontrollable clocks and/or asynch pins
Increase the test coverage of the design
Reduce the pattern count
Types of User Defined Test Points
The following types of user defined test points are
supported in DFT Compiler
Force
force_0, force_1, force_01, force_z0,
force_z1, force_z01
Control
control_0, control_1, control_01,
control_z0, control_z1, control_z01
Observe
observe
Specifying a Test Point Element
Use the command:
set_test_point_element
This command allows the users to specify the
location and the type of test points along with a set
of options in order to achieve their test point
requirements
Test Point Types
The type of test point to be inserted can be
specified as follows:
set_test_point_element [pin list]
–type <test_point_type>
Pin list specifies the location at which UDTP will be
inserted. It is a required argument
The type of test points can be force, control or
observe
Remember: Only one “type” of test point
can be specified with each invocation of
the set_test_point_element command
UDTP Types
Force_0 or Force_1 Force_01
Din
Din Dout
Dout 0 D Q
0 or 1 scan_in SI
scan_enable scan_out
test_mode test_point_clock
CTR
test_mode
Control_0 or Control_1 Control_01
Din
Din Dout
Dout 0 D Q
0 or 1
scan_in SI
test_mode scan_enable
0 D CTR
Q
scan_in SI scan_out
scan_enable
TPE test_mode
test_point_clock
0 D Q
SI scan_out
test_point_clock TPE
Observe
Din
D Q scan_out
scan_in SI
scan_enable
test_point_clock OBS
How to specify Control and Clock signals
Control Signal:
Must have been previously defined as a TestMode or ScanEnable
set_test_point_element pin_list –type control_01 \
–control_signal port_name|pin_name
Clock Signal:
Must have been previously defined as a ScanClock
set_test_point_element pin_list –type control_01 \
–clock_signal port_name|pin_name
Control_01
Din
Dout
0 D Q
scan_in SI
scan_enable
CTR
test_mode
port_name
pin_name 0 D Q
SI scan_out
test_point_clock TPE
port_name
pin_name
Enabling Control or Observe Registers
Enables or disables the insertion of
control, force, or observe scan registers
set_test_point_element
[-scan_source_or_sink enable | disable]
Default is “enable”
Din
Din
Dout D scan_out
0 D Q Q
scan_in SI scan_in SI
scan_out scan_enable
scan_enable OBS
CTR test_point_clock
test_mode
Control/Observe
Register
Specifying a Control Source or Observe Sink
The user can specify the name of the source signal
(for control or force points) or sink signal (for
observe points)
set_test_point_element
[-source_or_sink existing_pin_or_port]
This option is valid only for control or observe test
point types, when register insertion is disabled
Din
Din
Dout
source_pin
sink_pin
test_mode
Control Source Pin or Port Observe Sink Pin or Port
Enabling Scan Register Test Point Enables
Command option –scan_test_point_enable enables or
disables the insertion of test point enable scan registers
set_test_point_element pin_list –type test_point_type
[-scan_test_point_enable enable|disable]
Default is “enable”
This option is valid only for control test points
Din
Dout
0 D Q
scan_in SI
scan_enable
CTR
Test Point Enable test_mode
0 D Q
Register SI scan_out
test_point_clock TPE
Specifying a Test Point Enable
User can optionally specify a test point enable pin or port for
control points with the –test_point_enable option
set_test_point_element pin_list –type test_point_type
[-test_point_enable existing_pin_or_port]
If the name of the enable point is not supplied then DFTC
creates a new port called test_point_enable
This option is valid only for control test points
Must supply an unconnected pin Din
Dout
0 D Q
scan_in SI
scan_enable
CTR
scan_out
test_mode
test_point_enable
test_point_clock
Test Point Register Sharing
Sharing Control or Observe scan registers
set_test_point_element pin_list –type test_point_type \
–test_points_per_scan_source_or_sink 2 (default: 8)
Control_01
Din1
D Q
Dout1 Observe
0
scan_in SI Din1
scan_enable
CTR
test_mode
0 D Q scan_out
SI D Q
Din2 scan_in SI
test_point_clock TPE scan_enable
test_point_clock OBS
Din2
Dout2
0 D Q
SI scan_out
TPE
Test Point Enable Register Sharing
Sharing Control Test Point Enable Registers
This option is valid only for the control test point types
set_test_point_element pin_list –type test_point_type \
–test_points_per_test_point_enable 2 (default: 1)
Control_01
Din1
Dout1
0 D Q
scan_in SI
scan_enable
CTR
test_mode
0 D Q
SI
test_point_clock TPE
Din2
Dout2
scan_out
