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Sram Programmable Fpgas: Configuration Memory Cells

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Sram Programmable Fpgas: Configuration Memory Cells

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yasar saleem
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Chapter 2

SRAM Programmable FPGAs


Steve Trimberger, Xilinx, Inc.

2.1. Introduction
Since their introduction, SRAM-programmable FPGAs have become very popular.
Carter [1986], Hsieh [1987, 1990], Kean [1989], Furtek [1990], Hastie [1990],
Kawana [1990], Muroga [1991], Ebeling [1991], Chow [1991], Hauck [1992], Hill
and Britton [Hill 1992][Britton 1993] and Cliff [1993] have all proposed SRAM-
programmable FPGAs.
This chapter focuses on the three Xilinx families of FPGAs [Carter 1986] [Hsieh
1987] [Hsieh 1990] as representatives of the class of SRAM-programmable FPGAs
with mature software. These three FPGA families share a common structure: an array
of configurable logic blocks surrounded by configurable interconnect. The three
families differ in the details of the logic and interconnect structures. Members of a
family have identical block and wiring structure, but differ in the size of the array.
This chapter begins with an overview of the programming technology, it covers
device architectures for the three devices, software and design applications.

2.2. Programming Technology

SRAM Programming
An SRAM-programmable FPGA is programmed by loading configuration memory
cells from an external source. The configuration memory cells control the logic and
interconnect that perform the application function of the FPGA. There is no separate
RAM area on the chip, the memory cells are distributed among the logic they control.
The configuration memory is written only once for each application so, unlike
commercial static RAM memory chips, high-speed read and write is not important.
Stability and density are primary concerns. Figure 2.2.la shows the CMOS five-
transistor memory cell used in Xilinx FPGAs. The ReadlWrite pass transistor (RIW),
is used both to load the cell and to read back the programming. During normal
operation it is off, and the cell holds its programming.

S. M. Trimberger (ed.), Field-Programmable Gate Array Technology


© Kluwer Academic Publishers 1994
16 FPGA Technology

Five Transistor RAM Cell

WORD LINE

BIT
- - __ I
LINE
A B X3713

Four Transistor RAM Cell

WORDUNE

----,
Vee I - vec-'
I
I
I
I

BIT BIT
LINE LINE
B

Six Transistor RAM Cell

WORDUNE

----,
Vee I
I

c
I
BIT I BIT
.. - - __ I
LINE LINE
B

X4011

Figure 2.2.1. a) Xilinx Five-Transistor Configuration Memory Cell. b) Four-


Transistor Memory Cell. c) Six-Transistor Memory Cell.

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