M48T35AY

M48T35AV

5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER® SRAM

FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. 28-pin, PCDIP CAPHAT™ Package
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT AND BATTERY
■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS
■ BATTERY LOW FLAG (BOK)
■ FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK 28

■ AUTOMATIC POWER-FAIL CHIP 1

DESELECT AND WRITE PROTECTION
PCDIP28 (PC)
■ WRITE PROTECT VOLTAGES
Battery/Crystal
(VPFD = Power-fail Deselect Voltage): CAPHAT
– M48T35AY: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
– M48T35AV: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V Figure 2. 28-pin SOIC Package
■ SELF-CONTAINED BATTERY AND
CRYSTAL IN THE CAPHAT™ DIP
PACKAGE SNAPHAT (SH)
■ SOIC PACKAGE PROVIDES DIRECT Battery/Crystal
CONNECTION FOR A SNAPHAT®
HOUSING CONTAINING THE BATTERY
AND CRYSTAL
■ SNAPHAT® HOUSING (BATTERY AND
CRYSTAL) IS REPLACEABLE
■ PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 32Kb x8 SRAMs
28
1

SOH28 (MH)

April 2004 1/25

M48T35AY, M48T35AV

TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 28-pin, PCDIP CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....5
Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . ....... ...... ....... ...... ...... .....5

OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10.Checking the BOK Flag Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . ...... ...... . . . . 16
Figure 14.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... . . . . 16
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... . . . . 16
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... . . . . 17

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Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline . . . . . . . . . . . . . . 19
Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data . . . . . . . 19
Figure 17.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline. 20
Table 13. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Pack. Mech. Data 20
Figure 18.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 21
Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 21
Figure 19.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 22
Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 22

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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M48T35AY, M48T35AV

SUMMARY DESCRIPTION
The M48T35AY/V TIMEKEEPER ® RAM is a 32Kb nection to a separate SNAPHAT® housing con-
x 8 non-volatile static RAM and real time clock. taining the battery and crystal. The unique design
The monolithic chip is available in two special allows the SNAPHAT battery package to be
packages to provide a highly integrated battery mounted on top of the SOIC package after the
backed-up memory and real time clock solution. completion of the surface mount process. Inser-
The M48T35AY/V is a non-volatile pin and func- tion of the SNAPHAT housing after reflow pre-
tion equivalent to any JEDEC standard 32Kb x 8 vents potential battery and crystal damage due to
SRAM. It also easily fits into many ROM, EPROM, the high temperatures required for device surface-
and EEPROM sockets, providing the non-volatility mounting. The SNAPHAT housing is keyed to pre-
of PROMs without any requirement for special vent reverse insertion.
WRITE timing or limitations on the number of The SOIC and battery/crystal packages are
WRITEs that can be performed. shipped separately in plastic anti-static tubes or in
The 28-pin, 600mil DIP CAPHAT™ houses the Tape & Reel form.
M48T35AY/V silicon with a quartz crystal and a For the 28-lead SOIC, the battery/crystal package
long-life lithium button cell in a single package. (e.g. SNAPHAT) part number is “M4T28-BR12SH”
The 28-pin, 330mil SOIC provides sockets with (see Table 17., page 23).
gold plated contacts at both ends for direct con-

Figure 3. Logic Diagram Table 1. Signal Names

VCC A0-A14 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

15 8
E Chip Enable
A0-A14 DQ0-DQ7
G Output Enable

W M48T35AY W WRITE Enable

M48T35AV
E VCC Supply Voltage

VSS Ground
G

VSS
AI02797B

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 M48T35AY, M48T35AV

Figure 4. DIP Connections Figure 5. SOIC Connections

A14 1 28 VCC A14 1 28 VCC

A12 2 27 W A12 2 27 W
A7 3 26 A13 A7 3 26 A13
A6 4 25 A8 A6 4 25 A8
A5 5 24 A9 A5 5 24 A9
A4 6 23 A11 A4 6 23 A11
A3 7 M48T35AY 22 G A3 7 M48T35AY 22 G
A2 8 M48T35AV 21 A10 A2 8 M48T35AV 21 A10
A1 9 20 E A1 9 20 E
A0 10 19 DQ7 A0 10 19 DQ7
DQ0 11 18 DQ6 DQ0 11 18 DQ6
DQ1 12 17 DQ5 DQ1 12 17 DQ5
DQ2 13 16 DQ4 DQ2 13 16 DQ4
VSS 14 15 DQ3 VSS 14 15 DQ3
AI02798B
AI02799

Figure 6. Block Diagram

OSCILLATOR AND 8 x 8 BiPORT

CLOCK CHAIN SRAM ARRAY

32,768 Hz
CRYSTAL A0-A14

POWER

DQ0-DQ7
32,760 x 8
SRAM ARRAY
LITHIUM
CELL E

VOLTAGE SENSE W
VPFD
AND
SWITCHING
G
CIRCUITRY

VCC VSS AI01623

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M48T35AY, M48T35AV

OPERATION MODES
As Figure 6., page 5 shows, the static memory ar- cells. The M48T35AY/V includes a clock control
ray and the quartz controlled clock oscillator of the circuit which updates the clock bytes with current
M48T35AY/V are integrated on one silicon chip. information once per second. The information can
The two circuits are interconnected at the upper be accessed by the user in the same manner as
eight memory locations to provide user accessible any other location in the static memory array.
BYTEWIDE™ clock information in the bytes with The M48T35AY/V also has its own Power-fail De-
addresses 7FF8h-7FFFh. tect circuit. The control circuitry constantly moni-
The clock locations contain the year, month, date, tors the single 3V supply for an out of tolerance
day, hour, minute, and second in 24 hour BCD for- condition. When VCC is out of tolerance, the circuit
mat. Corrections for 28, 29 (leap year - valid until write protects the SRAM, providing a high degree
2100), 30, and 31 day months are made automat- of data security in the midst of unpredictable sys-
ically. Byte 7FF8h is the clock control register. This tem operation brought on by low VCC. As VCC falls
byte controls user access to the clock information below the Battery Back-up Switchover Voltage
and also stores the clock calibration setting. (VSO), the control circuitry connects the battery
The eight clock bytes are not the actual clock which maintains data and clock operation until val-
counters themselves; they are memory locations id power returns.
consisting of BiPORT™ READ/WRITE memory

Table 2. Operating Modes

Mode VCC E G W DQ0-DQ7 Power

Deselect VIH X X High Z Standby

WRITE 4.5 to 5.5V VIL X VIL DIN Active

or
READ 3.0 to 3.6V VIL VIL VIH DOUT Active

READ VIL VIH VIH High Z Active

Deselect VSO to VPFD (min)(1) X X X High Z CMOS Standby

Deselect ≤ VSO(1) X X X High Z Battery Back-up Mode

Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 11., page 18 for details.

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 M48T35AY, M48T35AV

READ Mode
The M48T35AY/V is in the READ Mode whenever Access time (tELQV) or Output Enable Access time
W (WRITE Enable) is high and E (Chip Enable) is (tGLQV).
low. The unique address specified by the 15 ad- The state of the eight three-state Data I/O signals
dress inputs defines which one of the 32,768 bytes is controlled by E and G. If the outputs are activat-
of data is to be accessed. Valid data will be avail- ed before tAVQV, the data lines will be driven to an
able at the Data I/O pins within Address Access indeterminate state until tAVQV. If the Address In-
time (tAVQV) after the last address input signal is puts are changed while E and G remain active,
stable, providing that the E and G access times output data will remain valid for Output Data Hold
are also satisfied. time (tAXQX) but will go indeterminate until the next
If the E and G access times are not met, valid data Address Access.
will be available after the latter of the Chip Enable

Figure 7. READ Mode AC Waveforms

tAVAV

A0-A14 VALID

tAVQV tAXQX

tELQV tEHQZ

tELQX

tGLQV tGHQZ

tGLQX
DQ0-DQ7 VALID

AI00925

Note: WRITE Enable (W) = High.

Table 3. READ Mode AC Characteristics

M48T35AY M48T35AV
Symbol (1) –70 –100 Unit
Parameter
Min Max Min Max
tAVAV READ Cycle Time 70 100 ns
tAVQV Address Valid to Output Valid 70 100 ns
tELQV Chip Enable Low to Output Valid 70 100 ns
tGLQV Output Enable Low to Output Valid 35 50 ns
(2) Chip Enable Low to Output Transition 5 10 ns
tELQX

tGLQX(2) Output Enable Low to Output Transition 5 5 ns

tEHQZ(2) Chip Enable High to Output Hi-Z 25 50 ns

tGHQZ(2) Output Enable High to Output Hi-Z 25 40 ns

tAXQX Address Transition to Output Transition 10 10 ns

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.

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M48T35AY, M48T35AV

WRITE Mode
The M48T35AY/V is in the WRITE Mode whenev- er READ or WRITE cycle. Data-in must be valid tD-
er W and E are low. The start of a WRITE is refer- VWH prior to the end of WRITE and remain valid for
enced from the latter occurring falling edge of W or tWHDX afterward. G should be kept high during
E. A WRITE is terminated by the earlier rising WRITE cycles to avoid bus contention; however, if
edge of W or E. The addresses must be held valid the output bus has been activated by a low on E
throughout the cycle. E or W must return high for and G, a low on W will disable the outputs tWLQZ
a minimum of tEHAX from Chip Enable or tWHAX after W falls.
from WRITE Enable prior to the initiation of anoth-

Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveform

tAVAV

A0-A14 VALID

tAVWH

tAVEL tWHAX

tWLWH

tAVWL

W
tWLQZ tWHQX

tWHDX

DQ0-DQ7 DATA INPUT

tDVWH
AI00926

Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms

tAVAV

A0-A14 VALID

tAVEH

tAVEL tELEH tEHAX

tAVWL

tEHDX

DQ0-DQ7 DATA INPUT

tDVEH
AI00927

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 M48T35AY, M48T35AV

Table 4. WRITE Mode AC Characteristics

M48T35AY M48T35AV
Symbol (1) –70 –100 Unit
Parameter
Min Max Min Max
tAVAV WRITE Cycle Time 70 100 ns
tAVWL Address Valid to WRITE Enable Low 0 0 ns
tAVEL Address Valid to Chip Enable Low 0 0 ns
tWLWH WRITE Enable Pulse Width 50 80 ns
tELEH Chip Enable Low to Chip Enable High 55 80 ns
tWHAX WRITE Enable High to Address Transition 0 10 ns
tEHAX Chip Enable High to Address Transition 0 10 ns
tDVWH Input Valid to WRITE Enable High 30 50 ns
tDVEH Input Valid to Chip Enable High 30 50 ns
tWHDX WRITE Enable High to Input Transition 5 5 ns
tEHDX Chip Enable High to Input Transition 5 5 ns

tWLQZ(2,3) WRITE Enable Low to Output Hi-Z 25 50 ns

tAVWH Address Valid to WRITE Enable High 60 80 ns

tAVEH Address Valid to Chip Enable High 60 80 ns

tWHQX(2,3) WRITE Enable High to Output Transition 5 10 ns

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

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M48T35AY, M48T35AV

Data Retention Mode Figure 10. Checking the BOK Flag Status
With valid VCC applied, the M48T35AY/V operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window (see Figure 15, Table 10, and Table
11., page 18). All outputs become high imped- POWER-UP
ance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may READ DATA
corrupt data at the currently addressed location, AT ANY ADDRESS
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected WRITE DATA
COMPLEMENT BACK
state, provided the VCC fall time is not less than tF. TO SAME ADDRESS
The M48T35AY/V may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There- READ DATA
fore, decoupling of the power supply lines is rec- AT SAME
ommended. ADDRESS AGAIN
When VCC drops below VSO , the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35AY/V IS DATA
COMPLEMENT NO (BATTERY LOW)
for an accumulated period of at least 7 years when
OF FIRST
VCC is less than VSO. As system power returns READ?
and VCC rises above VSO, the battery is discon-
NOTIFY SYSTEM
nected and the power supply is switched to exter- (BATTERY OK) YES OF LOW BATTERY
nal VCC. Write protection continues until VCC (DATA MAY BE
reaches VPFD (min) plus trec (min). E should be CORRUPTED)
kept high as VCC rises past VPFD (min) to prevent WRITE ORIGINAL
inadvertent WRITE cycles prior to processor stabi- DATA BACK TO
lization. Normal RAM operation can resume trec af- SAME ADDRESS
ter VCC exceeds VPFD (max).
Also, as VCC rises, the battery voltage is checked. CONTINUE
If the voltage is less than approximately 2.5V, an
internal Battery Not OK (BOK) flag will be set. The
BOK flag can be checked after power up. If the
BOK flag is set, the first WRITE attempted will be AI00607
blocked. The flag is automatically cleared after the
first WRITE, and normal RAM operation resumes.
Figure 10 illustrates how a BOK check routine
could be structured.
For more information on Battery Storage Life refer
to the Application Note AN1012.

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 M48T35AY, M48T35AV

CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers (see Ta- The user can then load them with the correct day,
ble 5) should be halted before clock data is read to date, and time data in 24 hour BCD format (see
prevent reading data in transition. The BiPORT™ Table 5). Resetting the WRITE Bit to a '0' then
TIMEKEEPER cells in the RAM array are only transfers the values of all time registers 7FF9h-
data registers and not the actual clock counters, 7FFFh to the actual TIMEKEEPER counters and
so updating the registers can be halted without allows normal operation to resume. The FT Bit and
disturbing the clock itself. the bits marked as '0' in Table 5 must be written to
Updating is halted when a '1' is written to the '0' to allow for normal TIMEKEEPER and RAM op-
READ Bit, D6 in the Control Register 7FF8h. As eration. After the WRITE Bit is reset, the next clock
long as a '1' remains in that position, updating is update will occur within one second.
halted. See the Application Note AN923, “TIMEKEEPER ®
After a halt is issued, the registers reflect the Rolling Into the 21 st Century” for information on
count; that is, the day, date, and the time that were Century Rollover.
current at the moment the halt command was is- Stopping and Starting the Oscillator
sued. The oscillator may be stopped at any time. If the
All of the TIMEKEEPER registers are updated si- device is going to spend a significant amount of
multaneously. A halt will not interrupt an update in time on the shelf, the oscillator can be turned off to
progress. Updating is within a second after the bit minimize current drain on the battery. The STOP
is reset to a '0.' Bit is the MSB of the seconds register. Setting it to
Setting the Clock a '1' stops the oscillator. The M48T35AY/V is
shipped from STMicroelectronics with the STOP
Bit D7 of the Control Register 7FF8h is the WRITE Bit set to a '1.' When reset to a '0,' the M48T35AY/
Bit. Setting the WRITE Bit to a '1,' like the READ
V oscillator starts within 1 second.
Bit, halts updates to the TIMEKEEPER® registers.

Table 5. Register Map

Data Function/Range
Address
D7 D6 D5 D4 D3 D2 D1 D0 BCD Format

7FFFh 10 Years Year Year 00-99

7FFEh 0 0 0 10 M. Month Month 01-12
7FFDh 0 0 10 Date Date Date 01-31
7FFCh 0 FT CEB CB 0 Day Century/Day 00-01/01-07
7FFBh 0 0 10 Hours Hours Hours 00-23
7FFAh 0 10 Minutes Minutes Minutes 00-59
7FF9h ST 10 Seconds Seconds Seconds 00-59
7FF8h W R S Calibration Control
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to '0' upon power ST = STOP Bit
for normal operation) 0 = Must be set to '0'
R = READ Bit CEB = Century Enable Bit
W = WRITE Bit CB = Century Bit

Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to CEB.

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M48T35AY, M48T35AV

Calibrating the Clock

The M48T35AY/V is driven by a quartz-controlled month which corresponds to a total range of +5.5
oscillator with a nominal frequency of 32,768 Hz. or –2.75 minutes per month.
The devices are tested not to exceed 35 ppm Two methods are available for ascertaining how
(parts per million) oscillator frequency error at much calibration a given M48T35AY/V may re-
25°C, which equates to about ±1.53 minutes per quire. The first involves simply setting the clock,
month. With the calibration bits properly set, the letting it run for a month and comparing it to a
accuracy of each M48T35AY/V improves to better known accurate reference (like WWV broadcasts).
than +1/–2 ppm at 25°C. While that may seem crude, it allows the designer
The oscillation rate of any crystal changes with to give the end user the ability to calibrate his clock
temperature (see Figure 11., page 13). Most clock as his environment may require, even after the fi-
chips compensate for crystal frequency and tem- nal product is packaged in a non-user serviceable
perature shift error with cumbersome “trim” capac- enclosure.
itors. The M48T35AY/V design, however, employs The second approach is better suited to a manu-
periodic counter correction. The calibration circuit facturing environment, and involves the use of
adds or subtracts counts from the oscillator divider some test equipment. When the Frequency Test
circuit at the divide by 256 stage, as shown in Fig- (FT) Bit, the seventh-most significant bit in the Day
ure 12., page 13. The number of times pulses are Register is set to a '1,' and D7 of the Seconds Reg-
blanked (subtracted, negative calibration) or split ister is a '0' (Oscillator Running), DQ0 will toggle at
(added, positive calibration) depends upon the 512 Hz during a READ of the Seconds Register.
value loaded into the five calibration bits found in Any deviation from 512 Hz indicates the degree
the Control Register. Adding counts speeds the and direction of oscillator frequency shift at the test
clock up, subtracting counts slows the clock down. temperature. For example, a reading of 512.01024
The Calibration Byte occupies the five lower order Hz would indicate a +20 ppm oscillator frequency
bits (D4-D0) in the Control Register 7FF8h. These error, requiring a –10 (WR001010) to be loaded
bits can be set to represent any value between 0 into the Calibration Byte for correction.
and 31 in binary form. Bit D5 is the Sign Bit; '1' in- Note: Setting or changing the Calibration Byte
dicates positive calibration, '0' indicates negative does not affect the Frequency Test output fre-
calibration. Calibration occurs within a 64 minute quency.
cycle. The first 62 minutes in the cycle may, once
The FT Bit MUST be reset to '0' for normal clock
per minute, have one second either shortened by
operations to resume. The FT Bit is automatically
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2 Reset on power-down.
minutes in the 64 minute cycle will be modified; if For more information on calibration, see Applica-
a binary 6 is loaded, the first 12 will be affected, tion Note AN934, “TIMEKEEPER® Calibration.”
and so on. Century Bit
Therefore, each calibration step has the effect of Bit D5 and D4 of Clock Register 7FFCh contain
adding 512 or subtracting 256 oscillator cycles for the CENTURY ENABLE Bit (CEB) and the CEN-
every 125,829,120 actual oscillator cycles, that is TURY Bit (CB). Setting CEB to a '1' will cause CB
+4.068 or –2.034 ppm of adjustment per calibra- to toggle, either from a '0' to '1' or from '1' to '0' at
tion step in the calibration register. Assuming that the turn of the century (depending upon its initial
the oscillator is in fact running at exactly 32,768 state). If CEB is set to a '0,' CB will not toggle.
Hz, each of the 31 increments in the Calibration Note: The WRITE Bit must be set in order to write
Byte would represent +10.7 or –5.35 seconds per to the CENTURY Bit.

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 M48T35AY, M48T35AV

Figure 11. Crystal Accuracy Across Temperature

ppm

20

-20

-40

∆F = -0.038 ppm (T - T )2 ± 10%

0
-60 F C2

T0 = 25 °C

-80

-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C
AI02124

Figure 12. Clock Calibration

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

AI00594B

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M48T35AY, M48T35AV

VCC Noise And Negative Going Transients Figure 13. Supply Voltage Protection
ICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as VCC
low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass ca- VCC
pacitor value of 0.1µF (as shown in Figure 13) is
recommended in order to provide the needed fil-
tering. 0.1µF DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on VCC that drive it to values VSS
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from AI02169
these voltage spikes, it is recommended to con-
nect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.

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 M48T35AY, M48T35AV

MAXIMUM RATING
Stressing the device above the rating listed in the not implied. Exposure to Absolute Maximum Rat-
“Absolute Maximum Ratings” table may cause ing conditions for extended periods may affect de-
permanent damage to the device. These are vice reliability. Refer also to the
stress ratings only and operation of the device at STMicroelectronics SURE Program and other rel-
these or any other conditions above those indicat- evant quality documents.
ed in the Operating sections of this specification is

Table 6. Absolute Maximum Ratings

Symbol Parameter Value Unit
Grade 1 0 to 70 °C
TA Ambient Operating Temperature
Grade 6 –40 to 85 °C
TSTG Storage Temperature (VCC Off, Oscillator Off) –40 to 85 °C

TSLD(1,2,3) Lead Solder Temperature for 10 seconds 260 °C

M48T35AY –0.3 to 7 V
VIO Input or Output Voltages
M48T35AV –0.3 to 4.6 V
M48T35AY –0.3 to 7 V
VCC Supply Voltage
M48T35AV –0.3 to 4.6 V
IO Output Current 20 mA
PD Power Dissipation 1 W
Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

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M48T35AY, M48T35AV

DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions listed in the relevant tables. De-
surement conditions, as well as the DC and AC signers should check that the operating conditions
characteristics of the device. The parameters in in their projects match the measurement condi-
the following DC and AC Characteristic tables are tions when using the quoted parameters.
derived from tests performed under the Measure-

Table 7. Operating and AC Measurement Conditions

Parameter M48T35AY M48T35AV Unit
Supply Voltage (VCC) 4.5 to 5.5 3.0 to 3.6 V

Grade 1 0 to 70 0 to 70 °C
Ambient Operating Temperature (TA)
Grade 6 –40 to 85 –40 to 85
Load Capacitance (CL) 100 50 pF
Input Rise and Fall Times ≤5 ≤5 ns
Input Pulse Voltages 0 to 3 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 1.5 V
Note: Output Hi-Z is defined as the point where data is no longer driven.

Figure 14. AC Measurement Load Circuit

645Ω
DEVICE
UNDER
TEST

CL = 100pF 1.75V
(or 5pF)

CL includes JIG capacitance

AI02586

Note: 50pF for M48T35AV.

Table 8. Capacitance
Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 10 pF

COUT(3) Output Capacitance 10 pF

Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.

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 M48T35AY, M48T35AV

Table 9. DC Characteristics
M48T35AY M48T35AV
Symbol Parameter (1) –70 –100 Unit
Test Condition
Min Max Min Max
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 ±1 µA

ILO(2) Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA

ICC Supply Current Outputs open 50 30 mA

Supply Current (Standby)
ICC1 E = VIH 3 2 mA
TTL
Supply Current (Standby)
ICC2 E = VCC – 0.2V 3 2 mA
CMOS

VIL(3) Input Low Voltage –0.3 0.8 –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 0.4 V

VOH Output High Voltage IOH = –1mA 2.4 2.4 V

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. Outputs deselected.
3. Negative spikes of –1V allowed for up to 10ns once per Cycle.

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M48T35AY, M48T35AV

Figure 15. Power Down/Up Mode AC Waveforms

VCC
VPFD (max)

VPFD (min)

VSO

tF tR
tFB tRB
tPD tDR trec

INPUTS RECOGNIZED DON'T CARE RECOGNIZED

HIGH-Z
OUTPUTS VALID VALID
(PER CONTROL INPUT) (PER CONTROL INPUT)

AI01168C

Table 10. Power Down/Up AC Characteristics

Symbol Parameter(1) Min Max Unit

tPD E or W at VIH before Power Down 0 µs

tF(2) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

M48T35AY 10 µs
tFB(3) VPFD (min) to VSS VCC Fall Time
M48T35AV 150 µs
tR VPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1 µs

trec(4) VPFD (max) to Inputs Recognized 40 200 ms

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
es VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. trec (min) = 20ms for industrial temperature Grade 6 device.

Table 11. Power Down/Up Trip Points DC Characteristics

Symbol Parameter(1,2) Min Typ Max Unit

M48T35AY 4.2 4.35 4.5 V

VPFD Power-fail Deselect Voltage
M48T35AV 2.7 2.9 3.0 V
M48T35AY 3.0 V
VSO Battery Back-up Switchover Voltage
M48T35AV VPFD –100mV V

Grade 1 10(3) YEARS

(5) Expected Data Retention Time
tDR
Grade 6 10(4) YEARS
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. All voltages referenced to VSS.
3. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top tDR = 7 years (typ).
4. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - Grade 6 device).
5. At 25°C, VCC = 0V.

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 M48T35AY, M48T35AV

PACKAGE MECHANICAL INFORMATION

Figure 16. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline

A2 A

A1 L C

B1 B e1
eA
e3

1 PCDIP

Note: Drawing is not to scale.

Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430
eA 15.24 16.00 0.600 0.630
L 3.05 3.81 0.120 0.150
N 28 28

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M48T35AY, M48T35AV

Figure 17. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline

A2 A
C
B e eB
CP

D
N

E H

A1 α L
1

SOH-A

Note: Drawing is not to scale.

Table 13. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Pack. Mech. Data
mm inches
Symb
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004

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 M48T35AY, M48T35AV

Figure 18. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline

A1 A2
A A3

eA B L
eB
D

SHTK-A

Note: Drawing is not to scale.

Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
mm inches
Symb
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090

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M48T35AY, M48T35AV

Figure 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

A1 A2
A A3

eA B L
eB
D

SHTK-A

Note: Drawing is not to scale.

Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm inches
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090

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 M48T35AY, M48T35AV

PART NUMBERING

Table 16. Ordering Information Scheme

Example: M48T 35AY –70 MH 1 E

Device Type
M48T

Supply Voltage and Write Protect Voltage

35AY = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
35AV = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V

Speed
–70 = 70ns (35AY)
–10 = 100ns (35AV)

Package
PC = PCDIP28
MH(1) = SOH28

Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C(2)

Shipping Method
For SOH28:
blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = Tubes

Note: 1. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under the part number “M4TXX-
BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see Table 17).
2. Available in SOIC package only.
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell bat-
tery.

For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.

Table 17. SNAPHAT Battery Table

Part Number Description Package
M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH
M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

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M48T35AY, M48T35AV

REVISION HISTORY

Table 18. Document Revision History

Date Rev. # Revision Details
November 1999 1.0 First Issue
21-Apr-00 2.0 From Preliminary Data to Data Sheet
29-May-00 2.1 tFB change (Table 10)

Reformatted; temp./voltage info. added to tables (Table 8, 9, 3, 4, 10, 11); add Century
20-Jul-01 3.0
Bit text
20-May-02 3.1 Modify reflow time and temperature footnotes (Table 6)
31-Mar-03 4.0 v2.2 template applied; data retention condition updated (Table 11)
01-Apr-04 5.0 Reformatted; updated with Lead-free package information (Table 6, 16)

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 M48T35AY, M48T35AV

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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All other names are the property of their respective owners.

© 2004 STMicroelectronics - All rights reserved

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