Hardware Software Co-Design
ES/SE/SS ZG626, MEL ZG651
Session 5
Pawan Sharma
BITS Pilani
[email protected]Pilani Campus 21/08/2021
Today’s Lecture
Specification and Modeling Concepts
• State Oriented Models
• Activity Oriented Models
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5-steps of Co-Design
Modeling
Analysis and Estimation
System Level partitioning, synthesis and Interfacing
Implementation Generation
Co-Simulation and Emulation
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High Level Synthesis Approach
target architecture
single chip
implementation of
target architecture
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HW
Model SW
System Design = Specifying Functionality + Implementing the
functionality using a set of physical components
Models help us understand a complex problem and its potential
solutions through abstraction
Designers first choose different models in different phases of the
design process
next step, is to transform the system functionality into an
architecture,
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Model-driven development
paradigm
• Primary focus on defining partitioned subsystems
using formal models
• based on concept with little worry about
implementation
• less sensitive to computing technology and its
evolution
• whats the outcome??
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Model Characteristics
5-characteristics
• Abstraction: System models are representations that highlight some
characteristics while abstracting away some others. Typically, system
models that capture all aspects of a design are complex and less useful
than feature-specific models.
• Understandibility: A direct function of the expressiveness (capacity to
convey a complex idea with little direct information) of the modeling form
• Accuracy: model must provide a true-to-life representation of the modeled
system’s features of interest
• Predictiveness: able to use a model to correctly predict the modeled
system’s interesting but nonobvious properties, either through
experimentation (such as by executing a model on a computer) or through
some type of formal analysis.
• Inexpensive: must be significantly cheaper to construct and analyze than
the modeled system.
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HW
Model 1 of an Elevator SW
The purpose of a model is to provide an abstracted view of a system.
English Description:
• If the elevator is stationary and the floor requested is equal to the
current floor then the elevator remains idle.
• If the elevator is stationary and the floor requested is less than the
current floor, then lower the elevator to the requested floor
• If the elevator is stationary and the floor requested is greater than the
current floor, then raise the elevator to the requested floor
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Model -2 of elevator
Algorithmic Style: Represented as a set of programming
statements
Loop
if (req_floor = curr_floor) then
direction = idle;
elseif (req_floor < curr_floor) then
direction =down;
elseif (req_floor >curr_floor) then direction =up;
endif;
endLoop;
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Model-3 of Elevator
HW
State Machine
SW
req_floor <curr_floor) /
direction:=down req_floor =curr_floor) / req_floor >curr_floor) /
direction:=idle direction:=up
req_floor <curr_floor) / req_floor >curr_floor) /
direction:=down direction:=up
down idle up
req_floor =curr_floor) /
direction:=idle
req_floor >curr_floor) / direction:=up
(req_floor <curr_floor) / direction:=down
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3-Models
• Each of these models represent a set of objects and the
interconnections amongst them
• The state machine example consists of a set of states and
transitions between these states
• The algorithmic model in contrast consists of a set of statements
that are executed under a control sequence that uses branches
and looping
• Advantage to have these models at our disposal is that they allow
designers to represent different views of a system, thereby
exposing its different characteristics
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• Different models are also required for different application
domains, for example, designers would model real time systems
and data base systems differently, since the former focus on
temporal behaviour while the latter focus on data organization.
• once the designer has found an appropriate model to specify the
functionality, he can describe in detail how a system will work.
• The next step is to transform the model into an architecture. That
define the model’s implementation by specifying the number and
type of components as well their interconnections.
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Architectures of elevator
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Model Taxonomy
• State Oriented Model
• Finite-state machine (FSM), Petri net, Hierarchical concurrent FSM
• Activity Oriented Model
• Dataflow graph, Flowchart
• Structure Oriented Model
• Block diagram, RT netlist, Gate netlist
• Data Oriented Model
• Entity-relationship diagram, Jackson’s diagram
• Heterogeneous Model
• Control/dataflow graph, Structure chart, Programming language paradigm,
Object-oriented paradigm, Program-state machine, Queueing model
• Object-oriented model
• For breaking complex software into simpler, well-defined pieces
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HW
SW
State Oriented Model: FSM
Consists of states, transitions, and triggers by external
events (e.g. FSMs)
Most suitable for real time reactive systems where the
temporal behavior is most important. Can be defined
as the quintuple:
< S,I,O,f,h >
FSM S, I, O, f : S I S, h : S I O >
Distinguished start state and final state
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HW
Mealy Machine SW
Q f (X ,Q) Z g(X ,Q)
input or transition
based model
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HW
Moore Machine
SW
Q f (X ,Q) Z g(Q)
state based model
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EEE G626
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Mealy and Moore Model of
elevator
Mealy Moore
require 9 states compared to 3 in mealy. Why? -- Each
state tells the value that must be produced at the
output ( y ) while the machine is in that state
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Design Steps for Moore Machine
Step 1: Draw the state transition diagram.
Step 2: Based on the state diagram, write two truth tables, one for
the next state and the other for the output. Then rearrange the
truth tables, replacing the state names with signal names ( q for
flip-flop outputs, d for flip-flop inputs) and using corresponding
binary values. To do this, choose first the encoding style
Step 3: Extract, from the rearranged truth tables, the optimal
Boolean expressions for next_state and for the output.
Step 4: Draw the corresponding circuit, placing all flip-flops (DFFs
only) in the lower section and the combinational logic for the
expressions derived above in the upper section
Step 5 (optional): Analyze the application and include the extra
register (for glitch removal or pipelining) if you conclude that it is
necessary.
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Example
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With non-overlapping bits
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Data Flow Diagram
• model for describing computational intensive systems
• nodes represent operations or functions and the arcs represent the order in which the nodes
are executed.
• Based on 2 principles:
Asynchrony
Functionality
• DFG can be described as a quintuple
• < N, A, V, v0, f >
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Square root computation
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Finite Machine with Datapath
• Most of the real systems combine the features of control and
computation.
• Thus, we must combine the features of the FSM and the DFG
models.
• One solution is to divide time into equal time intervals, called
states, and allocate one or more states for each node in the DFG.
• Since DFG computations are executed in a datapath we call this
model a finite-state machine with datapath (FSMD).
• In order to include a datapath, we must extend this definition by
adding the set of datapath variables, inputs and outputs.
• More formally, we define a variables set V which defines the state
of the datapath by defining the values of all variables in each
state.
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FSMD inputs (I) = set of FSM inputs Ic and a set of datapath inputs ID.
I = Ic x ID
Similarly, Output set, O = Oc x OD
• Variable values are specified using arithmetic expressions, Expr (V) we
define set of all possible expressions, Expr(V), over the set of variables V, to
be the set of all constants K of the same type as variables in V, the set of
variables V itself and all the expressions obtained by combining two
expressions with arithmetic, logic, or rearrangement operators.
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• Using Expr(V), we can also define the values of status signals as
well as transformations in the datapath.
• Let STAT = {statk = ei ∆ ej | ei,ej ϵ Expr(V), ∆ ϵ { ≤, ≥, ≠, <, >, = }}
be the set of all status signals which are described as relations
between variables or expressions of variables
• Examples of status signals are: Data ≠ 0, (a – b) > (x + y),
(counter = 0) AND (x > 10)
• relations defining status signals are either true, in which case the
status signal has a value of 1 or false in which case it has a value
of 0.
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• With formal definition of expressions and relations over a set of
variables we can simplify function
f : (S x V) x I S X V
by separating it into two parts: fc and fD
• The function fc defines the next state of the control unit
fc : S x Ic x STAT S
while the function fD defines the values of datapath variables in the next
state
fD : S x V X ID V
in other words, for each state si ϵ S, we compute a new value for each
variable Vj ϵ V in the datapath by evaluating an expression ei ϵ Expr(V)
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Similarly, we can decompose the output function
h : S x V x I O into two different functions, hc and hD
where hc defines the external control outputs Oc as in the
definition of an FSM and hD defines external datapath
outputs.
Therefore,
hc : S x lc x STAT Oc
and
hD : S x V X ID OD
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