Partial Response and

Viterbi Detection

Prof. David Johns

University of Toronto

([email protected])
(www.eecg.toronto.edu/~johns)

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© D.A. Johns, 1997

Partial-Response Motivation
Disadvantage — Feed-Forward Equalizer
• An FFE boosts the noise in areas where received sig-
nal power is low
• Example:

FFE
Ak = ±1 output data
H tc(z) H 1(z) Â k = ± 1
input data
H tc H1 H tc × H 1

f f f
Nyquist Pulse

• Noise is boosted at high frequencies.

slide 2 of 59
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© D.A. Johns, 1997
 Partial-Response Motivation
Disadvantage — Decision Feedback Equalizer
• A DFE does not make use of all the impulse response.
–1 –2
H tc(z) = 1 + 0.9z + 0.1z
Ak = ±1 qk output data
H tc(z)
input data – Â k = ± 1
DFE
H 2(z)
–1 –2
H 2(z) = 0.9z + 0.1z

• Since  k = A k , impulse response is δ(k)

• If single input, better to look for 1, 0.9, 0.1, 0, 0 than
1, 0, 0, 0, 0, 0
• Postcursor ISI may have significant signal power.

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© D.A. Johns, 1997

Partial-Response Motivation

• Rather than equalizing to a Nyquist pulse, equalize to

a partial-response signal
• Equalize to 1 + z –1 in DFE example
• Less noise boost
• More of the impulse response used to determine
transmitted signal
• Need to look at a string of received symbols rather
than symbol-by-symbol detection — MLSD

• Disadvantage — extra complexity and may not

recover full dynamic range loss

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© D.A. Johns, 1997
 Nyquist Criterion for Zero ISI
Noise

Data Data
Transmitter Receiver
Filter
Channel Σ Filter
Detector
in kT out

Impulse response h(t)

• Nyquist’s First Criterion for zero ISI

 k = 0
1
h ( kT ) = 
0 k≠0

2πn
∑ H  ω – ---------
T 
- = T
n

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© D.A. Johns, 1997

Minimum Bandwidth System with Zero ISI

 ω ≤π⁄T
H (ω ) =  T
 0 elsewhere
• A brickwall low-pass spectrum with a cutoff
frequency of 1 ⁄ ( 2T ) (“sinc” impulse response)
h(t)
H(f)

f t
1 1-
– ------ 0 ----- –T 0 T 2T
2T 2T

• However — impulse response decays at a rate of 1 ⁄ t

due to the frequency discontinuity in H(f) .
• Excessive ISI if any timing perturbation occurs

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 Non-Minimum Bandwidth System

• One way to overcome jitter problem is to use more

than the minimum bandwidth.
• A popular class of non-minimum bandwidth solutions
are — Cosine Roll-Off Filters
• Can still transmit and receive only one of two sym-
bols.

• But are minimum bandwidth systems practical? Yes.

— use partial-response signaling.

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© D.A. Johns, 1997

Partial-Response Signaling
• By relaxing the zero-ISI criterion of Nyquist, the
maximum symbol rate of 2 symbols/hertz can be
achieved.

• Allow a controlled amount of ISI by digitally FIR fil-

tering the data — results in more signal levels.

• Three popular FIR filters:

–1
1+z duobinary - class 1 zero at fs ⁄ 2
–1
1–z dicode zero at dc
–2
1–z modified duobinary - class 4 zeros at dc, f s ⁄ 2
(also called PR4 or PRIV)

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© D.A. Johns, 1997
 Duobinary (1+z-1)
0, 1 –1
z
0, 1, 2 received signal

–1 Equalized Channel Response

1+z
h(t)
H(f)

f
t
1 0 1 –T 0 T
– ------ ------ 2T
2T 2T
• Impulse response decays at a rate of 1 ⁄ t 2 since H(f)
is continuous but its first derivative is not.
• However, it transmits signal power at dc.

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© D.A. Johns, 1997

Dicode (1-z-1)
0, 1 –1
z
– ± 1, 0
received signal
Equalized Channel Response
–1
1–z

H(f) h( t )
T
f t
–T 0 2T
1 0 1
– ------ ------
2T 2T
• Impulse response decays at a rate of 1 ⁄ t due to the
frequency discontinuity in H(f) .
• However, it does not transmit any signal power at dc.

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© D.A. Johns, 1997
 Modified Duobinary (1-z-2) — class 4
0, 1 –2
z
– ± 1, 0
received signal
Equalized Channel Response
–2 –1 –1
1–z = (1 – z )( 1 + z )

H(f) h( t )

f t
–T 0 T 2T
1 0 1
– ------ ------
2T 2T

• h(t) decays at a rate of 1 ⁄ t 2 since H(f) is continuous.

• It does not transmit signal power at either dc or f s ⁄ 2 .

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Class-4 Partial Response Signaling Scheme

• Spectral nulls at DC and f s ⁄ 2
• Can be encoded/decoded by two interleaved dicode
encoder/decoder each operating at half the rate.

–1
1–z Encoder/Decoder (fs/2)

fs 1–z
–1
Encoder/Decoder (fs/2) fs

• Thus, we need only decode a dicode and use two

interleaved identical blocks to decode PRIV.
• If binary inputs, 3 level output — BPR4 or BPRIV
• (If 4 level inputs, 9 level output — QPR4 or QPRIV)

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 Magnetic Recording Similarities
• At low densities, a magnetic read signal is inherently
1-D encoded (i.e. a dicode).

0 1 0 0 1 0 1 1 0

+1 -1 0 +1 -1 +1 0 -1

• At higher densities, high-frequency roll-off important

(modelled as a Lorentzian pulse).
• If equalized to a 1-D channel, high-frequency noise is
amplified.

• Find a good approximation to channel so that the

boost required by equalizer is kept small.

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© D.A. Johns, 1997

Magnetic Recording Similarities

• Magnetic recording channel often modelled as
Lorentzian pulse
Frequency Response of a Lorentzian Magnetic Read Channel
1

0.9 t/T=0

0.8

0.7

0.6 t/T=1
|H(w)|

0.5

0.4

0.3
t/T=1.5
0.2

0.1 t/T=2

0
0 0.5 1 1.5 2 2.5 3 3.5
w

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© D.A. Johns, 1997
 Magnetic Recording Similarities
n
• Similar to ( 1 – z –1 ) ( 1 + z –1 ) partial-response channel.
n
Frequency Response of (1-D)(1+D) PRS Scheme
1

0.9 n=0 (dicode)

0.8
n=1 (PR4)
0.7

0.6
|H(w)|

0.5

0.4
n=2 (EPR4)
0.3

0.2

0.1
n=5
0
0 0.5 1 1.5 2 2.5 3 3.5
w

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© D.A. Johns, 1997

SNR Degradation for Dicode

• Now 3 levels being sent rather than just two.

1 ∆
-1
Uncoded binary signal “1-D” encoded ternary signal

• Thus, a bit-by-bit detection results in SNR perfor-

mance degradation (about 2-3 dB loss).
• However, the 3 levels have some redundancy
included.
• SNR performance can be recovered in detection by
employing Maximum-Likelihood Sequence
Estimation (MLSE) detection schemes
• The Viterbi Algorithm is an efficient way of realizing
MLSE detection

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© D.A. Johns, 1997
 Trellis Introduction
Input
0, 1 –1 state
z Output
– ± 1, 0

0/0
time
k-1 k k+1
0/0 0/0
0 0
1/+1 1/+1

1/+1 0/-1 state

0/-1 0/-1
1
1/0 1/0
1

State Diagram Trellis Diagram

1/0

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© D.A. Johns, 1997

Trellis Representation of Dicode (1-z-1)

• A trellis can be used to describe an encoder.
• Example:
time
k-1 k
Data 0/0
0
0, 1 –1 state 1/+1
z Encoded Data
– ± 1, 0 state
0/-1
1 1/0

Trellis

Data Encoded Data

0 1 1 0 1 0 0 +1 0 -1 +1 -1 0
Encoder

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© D.A. Johns, 1997
 Transmit Trellis for Dicode (1-z-1)
k-1 k
0/0
0
1/+1

0/-1
1
1/0

• Note that following a ‘+1’ output, there can be an

arbitrary number of zeros followed by a ‘-1’.
• In other words, if two ‘+1’ symbols are detected with
no ‘-1’ between them, an error occurred in transmis-
sion.
• Similar for a ‘-1’ output.
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© D.A. Johns, 1997

Conventional Bit-by-Bit Detection

noise corrupted received signals
Data
1 1 0 1 0 0 0.8 0.3 -0.4 0.9 -0.8 -0.1
Channel y
Encoded Data
+1 0 -1 +1 -1 0 Encoded Data Received
+1 0 0 +1 -1 0
y

thresholds at ± 0.5

• Note the error in bit 3 received.

• Error can be detected since a “-1” must be next non-
zero symbol after a “+1”.
• Did the error most likely occur in symbol 2, 3 or 4?
•
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 Viterbi Algorithm (VA)
• VA is an iterative method for determining the most
likely sequence sent — maximum likelihood detector.
• Accomplished by creating a receive trellis having
branch metrics proportional to the difference
squared between received signal and each ideal sym-
bol value.
• The most likely sequence is the shortest path
through the receive trellis.
• State metrics and path memory also stored to
reduce search time through trellis — they are the
length of shortest path and path taken at each node.

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Viterbi Algorithm Example

0/0
1/+1 0.8 0.3 -0.4 0.9 -0.8 -0.1
Channel
0/-1
Data 1/0 Encoded Data
1 1 0 1 0 0 +1 0 -1 +1 -1 0

large noise

0.64 0.73 0.49 1.3 0.54 0.55

0.00 0.64 0.09 0.16 0.81 0.64 0.01

0.04 0.49 1.96 0.01 3.24 1.21

3.24 1.69 0.36 3.61 0.04 0.89

0.00 0.64
0.09 0.16 0.81 0.64 0.01

0.04 0.13 0.29 0.50 1.14 1.15

Data
Received 1 1 0 1 0 0

Encoded Data Received

0 +1 0 -1 +1 -1 0

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 Viterbi Algorithm Example
0.64 large noise
0.00 0.64 0.49
0.73

0.04 0 0.00 0.64 0.09 0.16

0.04 0 0.49 0 1.96 1

3.24 0

0.00 0.64 0
3.24 1.69 1 0.36 1
0.04 0.64
0.00 0.09 0.16
Timestep 1 Timestep 3 0.13 0.29

large noise
0.64 0.73 0.49 1.3

0.00 0.64 0.09 0.00 0.64 0.09 0.16 0.81

0.04 0 0.49 0 0.04 0 0.49 0 1.96 1 0.01 0

3.24 0 1.69 1 3.24 0 1.69 1 0.36 1 3.61 0

0.00 0.64 0.00 0.64

0.09 0.09 0.16 0.81
0.04 0.13 0.29 0.50

Timestep 2 Timestep 4

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Detailed Received Trellis Description (BPR4)

• Transmitted signal — one of three values, ± a, 0
• Received signal — y k .
state metrics m0 k – 1 m0 k
2
( yk – 0 )

2 2
( yk + a ) ( yk – a ) branch metrics

2
( yk – 0 )
state metrics m1 k – 1 m1 k
• Equations:
2 2
m0 k = min { ( m0 k – 1 + y k ) , ( m1 k – 1 + ( y k + a ) ) }
2 2
m1 k = min { ( m1 k – 1 + y k ) , ( m0 k – 1 + ( y k – a ) ) }

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 Simplifications to Remove Multiplications
• Remove y 2k terms since it occurs in both terms and
we are only interested in finding the minimum path
(don’t need the absolute length of the path).
• State-metrics can now be either positive or negative.

m0 k – 1 m0 k m0 k – 1 m0 k
2
( yk – 0 ) 0
2
–yk
2 2
( yk + a ) ( yk – a ) ( 2ay k + a )
2
( – 2ay k + a )
2

2
( yk – 0 ) 0
m1 k – 1 m1 k m1 k – 1 m1 k

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© D.A. Johns, 1997

Simplifications to Remove Multiplications

• Divide all branches by 2a (assume a > 0 )
• Simply scales state metrics.
m0 k – 1 m0 k m0 k – 1 m0 k
0 0
÷ 2a
( 2ay k + a )
2
( – 2ay k + a )
2
 y + a---  – y + a---
 k 2  k 2
0 0
m1 k – 1 m1 k m1 k – 1 m1 k

• Equations:
m0 k = min { m0 k – 1 , ( m1 k – 1 + y k + a ) }
m1 k = min { m1 k – 1 , ( m0 k – 1 – y k + a ) }

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 Difference Metric Algorithm
• [Wood and Peterson, Trans. on Comm., May 1986]

• We are not interested in absolute state-metric values

— only which state-metric is smaller.

• Store only the difference in the state-metrics, ∆mk

∆m k ≡ m0 k – m1 k

• We shall see that while absolute state-metric values

increase in time, their difference does not.

• This “difference metric algorithm” results in less com-

plex realizations for both digital and analog realiza-
tions in cases where there are only two state-metrics.

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Difference Metric Algorithm

• Subtract off m1 k – 1 from input state-metrics and add it
into each branch metric instead.
• Now, m1k – 1 can be subtracted off branch metrics
since it is the same in all branches.

m0 k – 1 m0 k ∆m k – 1 m0 k
0 0
eliminating
m1 k – 1
 y + a---  – y + a---  y + a---  – y + a---
 k 2  k 2  k 2  k 2
0 0
m1 k – 1 m1 k 0 m1 k

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© D.A. Johns, 1997
 Difference Metric Algorithm
• Different path choices.
∆m k – 1
0 m0 k Condition
 ∆m a a
< y k + --- and  ∆m k – 1 < y k – ---
 k – 1
2  2
 y + a---  – y + a---
 k 2  k 2 Result
a
0 0 m1 k ∆m k = y k – ---
2

∆m k – 1 m0 k
0 Condition
 ∆m a  a
 y + a---  – y + a---  k – 1 > y k + --- and  ∆m k – 1 > y k – ---
2 2
 k 2  k 2
Result
0 0 m1 k a
∆m k = y k + ---
2

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Difference Metric Algorithm

• Different path choices.
∆m k – 1
0 m0 k Condition
 ∆m a  a
 k – 1 < y k + --- and  ∆m k – 1 > y k – ---
 y + a---  – y + a--- 2 2
 k 2  k 2 Result
0 0 m1 k ∆m k = ∆m k – 1

∆m k – 1 m0 k
0 Condition
 ∆m a  a
 y + a---  – y + a---  k – 1 > y k + --- and  ∆m k – 1 < y k – ---
2 2
 k 2  k 2 IMPOSSIBLE
0 0 m1 k Result
do nothing

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 Difference Metric Algorithm

• Equations:
 a a
 y k + --2- ∆m k – 1 > y k + ---
2

 a a
∆m k =  ∆m k – 1 y k – --- < ∆m k – 1 < y k + ---
 2 2
 a a
 y k – --- ∆m k – 1 < y k – ---
 2 2

• These equations describe an adjustable threshold

device.
• Used in digital PR4 implementations.
• They are also simple to implement in analog.

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Typical Digital Implementation

even
samples digital digital even
difference path output
algorithm memory
6-bit digital
from
channel A/D equalizer digital digital odd
difference path output
odd algorithm memory
samples
fs fs/2

• 6-bit flash A/D requires 63 comparators + decoding

logic.
• A/D converter might consume around 300mW (or
more)
• FIR equalizer might be 1mW/MHz/tap
— 8-tap at 100MHz = 800mW

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 Typical Digital Implementation

• Digital equalizer requires multi-bit multiplies in feed-

forward equalizer (power hungry)
• If decision feedback is used, it will need to use early
estimates of output (cannot wait for MLSE to finish).
• Digital difference algorithm requires some minor
adders and digital comparators.
• Digital path memory logic consists of about 16 serial/
parallel shift registers.

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© D.A. Johns, 1997

Typical Analog Implementation

even
samples analog digital even
difference path output
algorithm memory
from analog
channel equalizer analog digital odd
difference path output
odd algorithm memory
samples
fs/2

• Analog equalizer needed (less power than digital but

more challenging)

• Digital path memory is the same as in fully digital

realization.

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 Typical Analog Implementation

• Analog difference algorithm is very small (about the

size of 2 comparators)

• Thus, power is saved and speed can be increased

over 6-bit A/D converter.

• Note that dynamic range in analog parts need only be

around 6 bits (i.e. 40dB)

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Analog Implementation

yk-a/2
+
+a/2 ∆mk-1+a/2 S
Q
0 ∆mk-1
DC
Mux ∆mk-1
- R to path
y(t) S/H level
S/H memory
-a/2 ∆mk-1-a/2 shifter + R
Q
S
yk+a/2
-

Threshold Device Viterbi Detector CLK

• Path memory consists of two serial/parallel in/out

shift registers.
0 ... State “0”

1 ... State “1”

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 Some Practical Limitations

• In a digital implementation, performance is degraded

by limiting the number of bits used in A/D conversion
• Typically use about 6-bit A/D converters (easily
achievable in an all analog implementation).

• Truncating the trace-back length (path memory) also

degrades the performance.

• Typically use length of 16 for little loss in perfor-

mance.

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Why an Analog Implementation?

• Avoids using a pre-stage A/D converter.
• Combines the A/D and VA into one stage with a com-
plexity near to a 2-bit A/D (Special-purpose A/D con-
verter).
• Consumes less power.
• Operates faster.
• 6-bit accuracy is enough (Moderate Precision Cir-
cuitry).
• Low-dynamic range requirement (Low-Voltage Oper-
ation).
• The difference algorithm updates only one sampled
data without using previous samples (no accumula-
tive analog errors)

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 Simulation and Experimental Results
• Simulation and experimental (discrete prototype)
results confirm validity of the analog approach and its
robustness against imperfections.
0 0 0
10 10 10

-1 -1 -1
10 10 10

-2 -2 -2
10 10
Bit Error Rate, BER

Bit Error Rate, BER

10

Bit Error Rate, BER

-3 -3
10 10 -3
10

-4 -4
10 10 -4
10
o 2% o 2%
-5 x 5% -5 x 5%
10 + 10% 10 + 10% -5
10 o Measurment
--- Threshold Device --- Threshold Device
Viterbi Bound Viterbi Bound --- Threshold Device
-6 -6 Viterbi Bound
10 10 -6
0 5 10 15 0 5 10 15 10
Signal to Noise Ratio, SNR Signal to Noise Ratio, SNR 0 5 10 15
Signal to Noise Ratio, SNR
DC Offset or Absolute Gain Error Gain Mismatch

Offsets and mismatches are described in percentage of a Measured BER Performance of the Detector
(Path Memory = 17)

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Input-Interleaved Algorithm

• The implementation above updates ∆mk once the

comparator outputs are known.

• Thus, critical speed path is 2 sample-and-holds.

(Sample input and compare, then, perhaps, update
∆mk with another sample-and-hold).

• The input-interleaved algorithm reduces the critical

speed path to a single sample-and-hold (i.e. can
operate at twice the speed).

• It uses two sample-and-holds at the input and

switches which one the input goes to if ∆mk needs to
be updated.

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 Input Interleaved Algorithm

• According to the update mechanism, ∆mk-1 is a DC-

shifted version of a previously-sampled input signal
∆m k – 1 = y k – j ± 0.5

• We can use the previously held input signal plus

appropriate sign of DC shift for ∆mk.

• When ∆mk needs to be updated, switch input on to

other sample-and-hold capacitor and use the just
sampled input and a sign-bit for new ∆mk

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Input-Interleaved Algorithm
• Toggle between two S/Hs which store yk and yk-j
• Use a flip-flop to properly switch the DC signal
φ1.T
Vref
yk-yk-j-{
+ Polarity
0
Σ Switch +
- - S
-
Polarity To the Path
y(t) Vref
Switch Memory
+
+ + S Polarity
Σ Switch -
- yk-yk-j+{
0
Vref
φ1.T
T and T

T T S SR
F-F F-F
T S

• Speed improvement, as no additional S/H is required

(yk-j has already been stored)

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 BiCMOS Integrated-Circuit Implementation
φ1.T φ1.T

A0
+ A1 A0
+ L L- + A0

Latch
- - B0
L DL
Bias B0

φ2 φ3

φ1.T - + - + S S
S T
+ V/I - + V/I -

SW + SW + + + SW
- +
+ +
+ - + - +
y(t) Switch Switch V/I Switch VDC A1 A0
- - - -
- - -
+ + - - - +
SW SW SW

+ V/I - + V/I -
φ1.T S T T
- + - +

φ2 φ3 Q Q
φ1
Bias A1

- L DL - A1

Latch
+ L+ B1
L- + T φ1.T φ1.T T
B1

φ1.T φ1.T

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BiCMOS Integrated-Circuit Implementation

out+ out- out- out+
bias1

bias2
out- out+

SW SW

in+ in-
in+ in-

Switch
bias3

V/I

in+
out+ out-

in-

L+ L- L
DL

bias3

Latch

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BiCMOS Integrated-Circuit Implementation
• Path memory consists of 2x12 multiplexed-input D
flip-flops
“0” D D ... D State “0”

“1” D D ... D State “1”

B1/B0 B1/B0 φ4

in0/in1

out0/out1

in1/in0

A1/A0 A1/A0 φ5

• Clock phases
CLK

φ1 φ2 φ3 φ4 φ5

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BiCMOS Integrated-Circuit Implementation

• Compared to other analog implementations
[Matthews and Spencer, JSSC, Dec. 93]
• Less complex (Individual state metrics are not
calculated)
• Less prone to imperfections (Feedback signals are
only digital)
• Fully differential
• Faster (Master-slave S/Hs are not used)

[Yamasaki, ISSCC, 1994]

• No details given

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 Integrated-Circuit Implementation

Analog

Control
Logic

Digital

Second
Dicode

0.1mm

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Experimental Results

• Process: 0.8 µm BiCMOS

• Area (dicode): ~0.25 mm2
• Analog: ~0.06 mm2
• Digital: ~0.1 mm2
• Bypass capacitors, ...
• Power consumption (dicode):
• 3.3V power supply
• ~12mW at 50MHz
• ~15mW at 100MHz

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 Experimental Results
• Setup
CLK
White
Noise
Generator

Pseudo Σ Chip Phase

Random Encoder Under
Generator Σ Test Adjust

Level
Delay Compare
Translator

Error
Counter

• Measured Bit-Error-Rate (BER) performance

0
10

−1
10

−2
10
Bit−Error Rate (BER)

−3
10

−4
10

−5
10

−6 o Measured at 50MHz/Dicode
10
x Measured at 100MHz/Dicode
−7 Threshold Device
10

−8
10
4 6 8 10 12 14 16 18
Signal−to−Noise Ratio (SNR), dB

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A General Implementation Approach

• Analog implementations are useful if the preceding

signal processing is simple
• Magnetic recording
• Data transmission over unshielded cables
• Simplifications are only possible in some special
cases (i.e. PR4)
• This general approach can be used in
• More general PRS schemes (i.e. EPR4, EEPR4)
• Convolutional codes
• Multi-level digital communication
• Irregular trellises

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 A General Implementation Approach
• This approach takes full advantage of the ability of
simple analog circuits in realizing the ACS function
i = 1, 2, …, N
m i ( k ) = Max { m j ( k – 1 ) – e ji ( k ) }
j j = 1, 2, … , M

m1(k-1)
e1i
m2(k-1) e2i
mi(k)

...
eMi

mM(k-1)

• Branch metrics, eij, are usually expressed in terms of

linear combinations of the received samples and DC
signals

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Circuit Realization

• A generalized differential cell is employed to realize

the ACS function

m1(k-1) m2(k-1) mM(k-1) m1(k-1) m2(k-1) mM(k-1)

e1i + e2i + eMi +

- - - R R R
Vin1 Vin2
. . . VinM ... ...

Vout mi(k) mi(k)

αe1i αe2i αeMi

V
out
= Max { V in j } – v BE m
i
(k) = Max { m j ( k – 1 ) – e ji ( k ) } – v BE m
i
(k) = M ax { m j ( k – 1 ) – α R e ji ( k ) } –
j j j

• Using degenerated differential pairs in V/I conversions

makes the linear combinations simple to realize

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• Optional DC currents added to the error signals
reduce the unnecessary DC voltage drops across the
resistors

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Circuit Realization
• Branch currents in the differential cells are compari-
son results
• To achieve high speeds, ping-pong S/Hs are preferred
to master-slave S/Hs in feeding the state metrics back

Master-Slave S/H Ping-Pong S/H

• Algorithmic growth of state metrics is overcome by a

fast Common-Mode FeedBack (CMFB) circuit
• Fast CMFB minimizes the signal swings of the state
metrics — this approach is usually not practical in dig-
ital realizations

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© D.A. Johns, 1997
 Design Example: Binary Dicode

bias1

bias2

φ1 φ1
ref
φ2 φ2
φ2 φ2
bias3 φ1 φ1

bias3

bias1

bias2

- 0.5 + + y(t) - +0.5 -

bias3

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© D.A. Johns, 1997

Integrated Circuit Implementation

• A chip containing Viterbi decoders for a binary dicode

and an Extended PR4 (EPR4, (1-D)(1+D)2) has been
fabricated in a 0.8 µm BiCMOS process
• Based on simulations, fast speed (>100 MHz) can be
achieved with ~15mW/state (Excluding path memory)
• The area is ~0.03mm2/state (Excluding path memory)
• In a CMOS implementation, lower gm causes some
degradation in:
• Obtaining simple low-impedance nodes
• ACS performance due to the high dependency of
vGS to the drain current

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 Integrated Circuit Implementation

Clock 50 Ω
Generator Drivers

EPR4
50 Ω
Drivers

Dicode

Test
Dicode

Clock
Generator

0.1mm

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© D.A. Johns, 1997

Preliminary Experimental Results

• Results on dicode
−1
10

−2
10
Bit−Error Rate (BER)

−3
10

−4
10

−5
10 o Measured at 1 MHz
__ Viterbi Bound

−6
10
8 9 10 11 12 13 14
Signal−to−Noise Ratio (SNR), dB

• High-frequency tests have been conducted up to 80

MHz (Off-chip path memory)

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 Summary
• The use of partial-response signals allows one to
send closer to the maximum rate of
2 symbols/hertz.
• Making use of partial-response signalling reduces
the need for large equalization boost.
• The difference algorithm is efficient for PR4 signals
• Analog realizations of the difference algorithm save
silicon and power over digital realizations
(however, an analog equalizer is needed)
• Input-interleaved algorithm increases the speed for
an analog implementation
• A general analog Viterbi approach was discussed.
(However, it makes use of bipolar transistors).

slide 59 of 59
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© D.A. Johns, 1997