SLVS312A – JULY 2000 – REVISED DECEMBER 2002

D Overvoltage Protection and Lockout for D OR P PACKAGE

12 V, 5 V, 3.3 V (TOP VIEW)

D Undervoltage Protection and Lockout for PGI 1 8 PGO

5 V and 3.3 V GND 2 7 VDD
D Fault Protection Output With Open-Drain FPO 3 6 VS5
Output Stage PSON 4 5 VS33
D Open-Drain Power Good Output Signal for
Power Good Input, 3.3 V and 5 V
D Power Good Delay; 300-ms TPS3510,
150-ms TPS3511
D 75-ms Delay for 5-V and 3.3-V Power
Supply Short-Circuit Turnon Protection
D 2.3-ms PSON Control to FPO Turnoff Delay
D 38-ms PSON Control Debounce
D 73-µs Width Noise Deglitches
D Wide Supply Voltage Range From 4 V
to 15 V

description
The TPS3510/1 is designed to minimize external components of personal-computer switching power supply
systems. It provides protection circuits, power good indicator, fault protection output (FPO) and PSON control.
Overvoltage protection (OVP) monitors 3.3 V, 5 V, and 12 V (12-V signal detects via VDD pin). Undervoltage
protection (UVP) monitors 3.3 V and 5 V. When an OV or UV condition is detected, the power good output (PGO)
is set to low and FPO is latched high. PSON from low to high resets the protection latch. UVP function is enabled
75 ms after PSON is set low and debounced. Furthermore, there is a 2.3-ms delay (and an additional 38-ms
debounce) at turnoff. There is no delay during turnon.
Power good feature monitors PGI, 3.3 V and 5 V and issues a power good signal when the output is ready.
The TPS3510/1 is characterized for operation from –40°C to 85°C.

typical application
5 VSB PGI

PGO

12 V
0.5 V
1 8 Drop
PGI PGO
2 7
GND VDD VSB
3 6
FPO VS5 5V
4 5
PSON PSON VS33 3.3 V
(From Motherboard)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


 
   !"   #!$%  &"' Copyright  2002, Texas Instruments Incorporated
&!    #"   #" (" " 
") !"
&& *+' &!  # ", &"  " "%+  %!&"
",  %% #""'

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

FUNCTION TABLE
UV CONDITION OV CONDITION
PGI PSON FPO PGO
(3.3 V OR 5 V) (3.3 V, 5 V, OR 12 V)
<0.95 V L no no L L
<0.95 V L no yes H L
<0.95 V L yes no L L
0.95 V<PGI<1.15 V L no no L L
0.95 V<PGI<1.15 V L no yes H L
0.95 V<PGI<1.15 V L yes no H L
PGI > 1.15 V L no no L H
PGI > 1.15 V L no yes H L
PGI > 1.15 V L yes no H L
x H x x H L
x = don’t care
FPO = L means: fault IS NOT latched
FPO = H means: fault IS latched
PGO = L means: fault
PGO = H means: NO fault

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

functional block diagram

VDD

12 V OV
+
_ POR

VS5

5 V OV
FPO
+ S Q
73-µs
_
Debounce

VS33
73-µs 2.3-ms
Delay VDD
Debounce

3.3 V OV
38-ms
Debounce PSON
+
_

3.3 V UV 75-ms
+ Delay
_

5 V UV VDD
+
_
PGO
PGI1
+ 150-µs
Delay†
_ Debounce

Band-Gap
Reference PGI2
1.15 V + 150-µs Debounce
_ and
PGI 4.8-ms Delay

Band-Gap
Reference
0.95 V

† 300 ms for TPS3510 and 150 ms for TPS3511

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

timing diagram

VDD

PSON

FPO

PGI

3.3 V, 5 V

12 V

PGO

td1 tb td1
PG OFF
td1
Delay

td2
Protect PSON
Occur PSON AC Off
On
On
PSON Off

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
FPO 3 O Inverted fault protection output, open drain output stage
GND 2 Ground
PGI 1 I Power good input
PGO 8 O Power good output, open drain output stage
PSON 4 I ON/OFF control
VDD 7 I Supply voltage/12 V overvoltage protection input pin
VS33 5 I 3.3 V over/undervoltage protection
VS5 6 I 5 V over/undervoltage protection

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

detailed description
power good and power good delay
A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer
manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate
that the 5-V and 3.3-V outputs are above the under-voltage threshold limit. At this time the converter should be
able to provide enough power to ensure continuous operation within the specification. Conversely, when either
the 5-V or the 3.3-V output voltages fall below the under-voltage threshold, or when ac power has been removed
for a time sufficiently long so that power supply operation is no longer ensured, PGO should be de-asserted to
a low state.
Figure 1 represents the timing characteristics of the power good (PGO), dc enable (PSON), and the 5 V/3.3 V
supply rails.

PSON On
Off

75%
5-V/3.3-V
Output 10%

PGO

t5 t4
t3

t2

Figure 1. Timing of PSON and PGO

Although there is no requirement to meet specific timing parameters, the following signal timings are
recommended:
2 ms ≤ t2 ≤ 20 ms, 100 ms < t3 < 2000 ms, t4 > 1 ms, t5 ≤ 10 ms
Furthermore motherboards should be designed to comply with the previously recommended timing. If timings
other than these are implemented or required, this information should be clearly specified.
The TPS3510/1 family of power-supply supervisors provides a power-good output (PGO) for the 3.3-V and 5-V
supply voltage rails and a separate power-good input (PGI). An internal timer is used to generate a power-good
delay. If the voltage signals at PGI, VS33, and VS5 rise above the under-voltage threshold, the open-drain
power-good output (PGO) goes high after a delay of 150 ms or 300 ms. When the PGI voltage or either the 3.3-V
and 5-V power rails drops below the under-voltage threshold, PGO is disabled immediately (after 150-µs
debounce).
power supply remote on/off (PSON) and fault protect output (FPO)
Since the latest personal computer generation focuses on easy turnon and power saving functions, the PC
power supply requires two characteristics. One is a dc power supply remote on/off function, the other is standby
voltage to achieve very low power consumption of the PC system. Thus the main power needs to be shut down.
The power supply remote on/off (PSON) is an active low signal that turns on all of the main power rails including
3.3 V, 5 V, –5 V, 12 V, and –12 V power rails. When this signal is held high by the PC motherboard or left open
circuited, the signal of the fault protect output (FPO) also goes high. Thus, the main power rails should not deliver
current and should be held at 0 V.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

power supply remote on/off (PSON) and fault protect output (FPO)(continued)
When the FPO signal is held high due to an occurring fault condition, the fault status is latched and the outputs
of the main power rails should not deliver current but are held at 0 V. Toggling the power supply remote on/off
(PSON) from low to high resets the fault-protection latch. During this fault condition only the standby power is
not affected.
When PSON goes from high to low or low to high, the 38-ms debounce block is active to avoid a glitch on the
input that disables/enables the FPO output. During this period the under-voltage function is disabled for 75 ms
to prevent turnon failure. At turnoff, there is an additional delay of 2.3 ms from PSON to FPO.
Power should be delivered to the rails only if the PSON signal is held at ground potential, thus FPO is active-low.
The FPO pin can be connected to 5 V (or up to 15 V) through a pullup resistor.
undervoltage protection
The TPS3510/1 provides under-voltage protection (UVP) for the 3.3-V and 5-V rails. When an undervoltage
condition appears at either one of the 3.3-V (VS33) or 5-V (VS5) input pins for more than 146 µs, the FPO output
goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or VDD
is removed.
The need for undervoltage protection is often overlooked in off-line switching power supply system design. But
it is very important in battery-powered or hand-held equipment since the TTL or CMOS logic often results in
malfunction.
In flyback or forward-type off-line switching power supplies, usually designed for low power, the overload
protection design is very simple. Most of these types of power supplies are only sensing the input current for
an overload condition. The trigger point needs to be set much higher than the maximum load in order to prevent
false turnon.
However, this causes one critical problem. If the connected load is larger than the maximum allowable load but
smaller than the trigger point, the system always becomes overheated with failure and damage occurring.
overvoltage protection
The overvoltage protection (OVP) of TPS3510/1 monitors 3.3 V, 5 V, and 12 V (12 V is sensed via the VDD pin).
When an overvoltage condition appears at one of the 3.3-V, 5-V, or 12-V input pins for more than 73 µs, the FPO
output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high
or VDD is removed. During fault conditions, most power supplies have the potential to deliver higher output
voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages
to be high enough to cause internal or external damage of the system. To protect the system under these
abnormal conditions, it is common practice to provide overvoltage protection within the power supply.
Because TTL and CMOS circuits are very vulnerable to overvoltages, it is becoming industry standard to provide
overvoltage protection on all 3.3-V and 5-V outputs. However, not only the 3.3-V and 5-V rails for the logic circuits
on the motherboard need to be protected, but also the 12-V peripheral devices such as the hard disk, floppy
disk, and CD-ROM players etc., need to be protected.
short-circuit power supply turnon
During safety testing the power supply might have tied the output voltage direct to ground. If this happens during
the normal operating, this is called a short-circuit or over-current condition. When it happens before the power
supply turns on, this is called a short-circuit power supply turnon. It can happen during the design period, in the
production line, at quality control inspection or at the end user. The TPS3510/1 provides an undervoltage
protection function with a 75-ms delay after PSON is set low.

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Output voltage VO: FPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
PGO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
P 1092 mW 8.74 mW/°C 699 mW 568 mW
D 730 mW 5.84 mW/°C 467 mW 379 mW

recommended operating conditions at specified temperature range

MIN NOM MAX UNIT
Supply voltage, VDD 4 15 V
PSON, VS5, VS33 7
Input voltage, VI VDD + 0.3 V V
PGI
(max = 7 V)
FPO 15
voltage VO
Output voltage, V
PGO 7
FPO 20
O tp t sink ccurrent,
Output rrent IO,sink mA
PGO 10
Supply voltage rising time, tr See Note 2 1 ms
Operating free-air temperature range, TA –40 85 °C
NOTE 2: VDD rising and falling slew rate must be less than 14 V/ms.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

electrical characteristics over recommended operating conditions (unless otherwise noted)

overvoltage protection
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VS33 3.7 3.9 4.1
Overvoltage threshold VS5 5.7 6.1 6.5 V
VDD 13.2 13.8 14.4
ILKG Leakage current (FPO) V(FPO) = 5 V 5 µA
VOL Low-level output voltage (FPO) VDD = 5 V, Isink = 20 mA 0.7 V
Noise deglitch time OVP VDD = 5 V 35 73 110 µs

PGI and PGO

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PGI1 1.1 1.15 1.2
VPGI Inp t threshold voltage
Input oltage (PGI) V
PGI2 0.9 0.95 1
VS33 2 2.2 2.4
VIT Under oltage threshold
Undervoltage V
VS5 3.3 3.5 3.7
ILKG Leakage current (PGO) PGO = 5 V 5 µA
VOL Low-level output voltage (PGO) VDD = 4 V, Isink = 10 mA 0.4 V
Short-circuit protection delay 3.3 V, 5 V 49 75 114 ms
TP3510 200 300 450
PGI to PGO
td1 Delay time TP3511 VDD = 5 V 100 150 225 ms
PGI to FPO 3.2 4.8 7.2
PGI to PGO 88 150 225
Noise deglitch time PGI to FPO VDD = 5 V 180 296 445 µs
UVP to FPO 82 146 220

PSON control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
II Input pullup current PSON = 0 V 120 µA
VIH High-level input voltage 2.4 V
VIL Low-level input voltage 1.2 V
tb Debounce time (PSON) VDD = 5 V 24 38 57 ms
td2 Delay time (PSON to FPO) VDD = 5 V tb+1.1 tb+2.3 tb+4 ms

total device
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD Supply current PSON = 5 V 1 mA

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

SUPPLY CURRENT INPUT CURRENT (PSON)

vs vs
SUPPLY VOLTAGE INPUT VOLTAGE (PSON)
400 20
VDD = 4 V
TA = –40°C
300 0
I DD – Supply Current – µ A

–20
TA = 85°C

I I – Input Current – µ A
200
TA = 25°C
–40
100
TA = 0°C
–60
0
–80
TA = –40°C
–100 TA = 0°C
–100 TA = 25°C
TA = 85°C
–200
PGI = 1.4 V –120
PSON = 5 V
–300
0 2.5 5 7.5 10 12.5 15 –140
0 1 2 3 4 5 6 7
VDD – Supply Voltage – V VI – Input Voltage – V

Figure 2 Figure 3

LOW-LEVEL OUTPUT VOLTAGE (FPO) LOW-LEVEL OUTPUT VOLTAGE (FPO)

vs vs
LOW-LEVEL OUTPUT CURRENT (FPO) LOW-LEVEL OUTPUT CURRENT (FPO)
4 800
VDD = 4 V
VDD = 4 V
PSON = GND
PSON = GND
VOL– Low-Level Output Voltage – mV

700
VOL – Low-Level Output Voltage – V

Exploded View
3 600
TA = 85°C TA = 85°C

500

2 400

TA = 25°C 300
TA = –40°C TA = 25°C TA = –40°C

1 200
TA = 0°C TA = 0°C
100

0 0
0 20 40 60 80 100 120 0 5 10 15 20 25
IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA

Figure 4 Figure 5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9




     
SLVS312A – JULY 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE (PGO) LOW-LEVEL OUTPUT VOLTAGE (PGO)

vs vs
LOW-LEVEL OUTPUT CURRENT (PGO) LOW-LEVEL OUTPUT CURRENT (PGO)
4
600
VDD = 4 V VDD = 4 V
PSON = GND PSON = GND

VOL – Low-Level Output Voltage – mV

VOL – Low-Level Output Voltage – V

500 Exploded View

TA = 85°C
3

400
TA = 85°C

2 300
TA = –40°C
TA = 25°C
200 TA = 25°C
1 TA = –40°C
TA = 0°C
100 TA = 0°C

0 0
0 25 50 75 100 125 150 0 5 10 15 20
IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA

Figure 6 Figure 7
NORMALIZED SENSE THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
Normalized Input Threshold Voltage – VIT(TA)/VIT(25 °C)

1.001
VDD = 4 V
PSON = GND
1

0.999

0.998

0.997

0.996

0.995

0.994–40 –15 10 35 60 85
TA – Free-Air Temperature – °C

Figure 8

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS3510D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS3510

TPS3510DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS3510

TPS3510DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PS3510

TPS3510P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TPS3510P

TPS3510PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TPS3510P

TPS3511D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PS3511

TPS3511DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PS3511

TPS3511DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PS3511

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Aug-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS3510DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS3511DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Aug-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS3510DR SOIC D 8 2500 340.5 336.1 25.0
TPS3511DR SOIC D 8 2500 340.5 336.1 25.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated