American International University- Bangladesh

Department of Computer Science

Lab Report Cover Sheet

Course Name MICROPROCESSOR AND EMBEDDED SYSTEMS

Lab Report No. 01
Lecturer Name MD. ALI NOOR
Semester FALL 2020-21
Submission Date 26/09/2021
Section K
Group No. 04

Student Name Student ID Contribution (out of 100%)

1. Nuzhut Tabassum 19-39967-1

2. Moyinul Islam 18-37188-1

3. Md. Istihad Alam 18-38872-3

4. Zayed Zaman 19-39904-1
5. Md. Muhaiminul Islam 19-39968-1

6. Md. Meherat Hassan 19-40127-1

7. Md. Sakibul Islam Fahim 19-40170-1
 8. Md. Mahmudul Hassan 19-40751-1

EXPERIMENT NO
01
TITLE
Introduction to Microprocessor 8086, 8086 instructions and programming with 8086.

INTRODUCTION
The microprocessor 8086 can be considered to be the basic processor for the Intel X-86 family.
With the knowledge of this 16-bit processor, one can study the further versions of this processor
80386, 80406 and Pentium.
The micro-kit we are using is “MTS-86c” and “MDA 8086”.

THEORY & METHODOLOGY

The 8086 Microprocessor
The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and mid-1978,
when it was released. The 8086 become the basic x86- architecture of Intel's future processors.
 Figure: Intel 8086 internal architecture

MAXIMUM MINIMUM
MODE MODE

GND 1 40 Vcc
AD14 AD15
AD13 A16,S3
AD12 A17,S4
AD11 A18,S5
AD10 A19,S6
AD9 /BHE,S7
AD8 MN,/MX
AD7 /RD
AD6 /RQ,/GT0 HOLD
AD5
8086 /RQ,/GT1 HLDA
AD4 /LOCK /WR
AD3 /S2 IO/M
AD2 /S1 DT/R
AD1 /S0 /DEN
AD0 QS0 ALE
NMI QS1 /INTA
INTR /TEST
CLK READY
GND 20 21 RESET

Figure: Internal Diagram, Registers and PIN diagram of the 8086 microprocessor

General Purpose Registers

8086 CPU has 8 general purpose registers; each register has its own name: 
AX - the accumulator register (divided into AH / AL):
1. Generates shortest machine code
2. Arithmetic, logic and data transfer
3. One number must be in AL or AX
4. Multiplication & Division
5. Input & Output
 BX - the base address register (divided into BH / BL).
 CX - the count register (divided into CH / CL):
1. Iterative code segments using the LOOP instruction
2. Repetitive operations on strings with the REP command
3. Count (in CL) of bits to shift and rotate
 DX - the data register (divided into DH / DL):
1. DX:AX concatenated into 32-bit register for some MUL and DIV operations
2. Specifying ports in some IN and OUT operations
 SI - source index register:
1. Can be used for pointer addressing of data
2. Used as source in some string processing instructions
3. Offset address relative to DS
 DI - destination index register:
 1. Can be used for pointer addressing of data
2. Used as destination in some string processing instructions
3. Offset address relative to ES
 BP - base pointer:
1. Primarily used to access parameters passed via the stack
2. Offset address relative to SS
 SP - stack pointer:
1. Always points to top item on the stack
2. Offset address relative to SS
3. Always points to word (byte at even address)
4. An empty stack will have SP = FFFEh
Segment Registers
CS - points at the segment containing the current program.
DS - generally points at segment where variables are defined.
ES - extra segment register, it's up to a coder to define its usage.
SS - points at the segment containing the stack.

Although it is possible to store any data in the segment registers, this is never a good idea. The segment
registers have a very special purpose - pointing at accessible blocks of memory.

Segment registers work together with general purpose register to access any memory value. For example
if we would like to access memory at the physical address 12345h(hexadecimal), we could set the DS =
1230h and SI = 0045h. This way we can access much more memory than with a single register, which is
limited.
The CPU makes a calculation of the physical address by multiplying the segment register by 10h and
adding the general purpose register to it (1230h * 10h + 45h = 12345h): 

 
The address formed with 2 registers is called an effective address.
By default, BX, SI and DI registers work with DS segment register; BP and SP work with SS segment
register. Other general-purpose registers cannot form an effective address. Also, although BX can form an
effective address, BH and BL cannot.
Special Purpose Registers
IP - the instruction pointer:
1. Always points to next instruction to be executed
2. Offset address relative to CS
IP register always works together with CS segment register and it points to currently executing
instruction.
Flags Register
Flags Register - determines the current state of the processor. They are modified automatically by CPU
after mathematical operations, this allows to determine the type of the result, and to determine conditions
to transfer control to other parts of the program. Generally, you cannot access these registers directly. 

1. Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For example, when you
add bytes 255 + 1 (result is not in range 0...255). When there is no overflow this flag is set to 0.
2. Parity Flag (PF) - this flag is set to 1 when there is even number of ‘1’ bits in result, and
to 0 when there is odd number of ‘1’ bits.  
3. Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4 bits). 
4. Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to 0.
5. Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to0. (This flag
takes the value of the most significant bit.) 
6. Trap Flag (TF) - Used for on-chip debugging.
7. Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from external
devices.
8. Direction Flag (DF) - this flag is used by some instructions to process data chains, when this flag
is set to 0 - the processing is done forward, when this flag is set to 1the processing is done
backward.
9. Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when you add
bytes 100 + 50 (result is not in range -128...127). 
8086 Segmented Memory
Microprocessor 8086 consists of 9 address registers CS, DS, SS, ES, SI, DI, SP, BP, IP. Address registers
store address of instruction and data in memory. These values are used by the processor to access memory
locations.8086 assigns a 20-bit physical address to its memory locations. Thus, it is possible to address 2 20
= 1 megabyte of memory.
Segmented memory is the direct consequence of using 20-bit address in a 16-bit processor. The address is
too big to fit in a 16 bit register or memory word. The 8086 gets around this problem by portioning its
memory into segments.
A memory segment is a block of 2^16 (64K) consecutive memory bytes. Each segment is defined by a
segment number. A segment number is 16 bits, so the highest segment number is FFFFh.
Within a segment, a memory location is specified by giving an offset. The offset is the number of byte
beginning from the segment. With a 64KB segment, the offset can be given as a 16-bit number. The first
byte in a segment has offset 0. The last offset in a segment is FFFFh.
A memory location may be specified by providing a segment number and an offset, written in the form
segment: offset. This is known as logical address. For example, 1234: FF67 means offset number FF67
of segment 1234. The 20-bit physical address can be calculated by multiplying the segment number with
10h and then adding the offset with the result. For example, the physical address for A4FB:4872 is
A4FB0
+4872
A9882
Segment 0 starts at 0000:0000=00000h and ends at 0000: FFFF=0FFFFh. Segment 1 starts at
0001:0000=00010h and ends at 0001: FFFF=1000Fh. So, there is a lot of overlapping between segments.
Because segments may overlap, the segment: offset form of an address is not unique, that is the same
physical address can be represented in different segment: offset combinations. For example,
1256Ah=1256:000A, that is physical address 1256Ah can be represented as offset 000A of segment 1256.
Again, the same physical address 1256Ah can be represented as offset 016A of segment 1240 as
1256Ah=1240:016A.
There are several advantages of working with the segmented memory. First of all, after initializing the 16-
bit segment registers, the 8086 has to deal with only 16-bit effective addresses. That is 8086 has to store
and manipulate only 16-bit address components as both segment and offset are 16 bits. [1]

APPARATUS
o Microprocessor 8086 Trainer Board (MTS-86c)

o EMU8086 [ver.408 (32-bit WINOS compatible)]

o PC having Intel Microprocessor

WORKING PROCEDURE
1. The EMU8086 was Run from Installed Dictionary

2. Selected New then COM Template

3. Code was written in add your code here section

4. Code was written in code section

 5. By clicking play/emulate button code was compiled
6.
This is how we work with emu 8086.
LAB TASK
1. AIUB summer 2021 Semester MAES Lab1 Print.
Answer:

Program:
REPORT
1. Include all codes’ list file printout following lab report writing template mentioned in
appendix
ANSWER:
Enclosed in Lab Task section.

2. What is the advantage of having overlapping segments in 8086 memory system?

ANSWER:
Some of the advantages of memory overlapping segmentation in the 8086 are as follows:

- With the help of memory segmentation, a user is able to work with registers having only
16-bits.

- By memory segmentation the various portions of a program can be of more than 68kb.

- The data and the users code can be stored separately allowing for more flexibility.

- Also due to segmentation the logical address range is from 0000H to FFFFH the code can
be loaded at any location in the memory. [2]

For a memory location with physical address 1256Ah, Calculate the address in segment:offset
form for segments 1256h and 1240h.

ANSWER:
Here, Physical Address = 1256h

Logical address for segment 1256h = Segment: Offset

= 1256h:000Ah

Logical address for segment 1240h = Segment: Offset

= 1240h:016Ah

DISCUSSION
In this experiment there may be a only scope of error is typing mistake while typing the codes in
the MTS-86C or in the computer. The whole experiment was based on the implementation and
understanding the codes on the 8086 microprocessor.

CONCLUSION
The codes were implemented and run them on emu8086 and MTS-86C by following instructor’s
instruction. The output was same on both and the experiment was successful.

REFERENCE(S)
[1] Lab Manual, American International University-Bangladesh
[2] Available at:
www.careerride.com/view/advantages-of-memory-segmentation-in-8086-2301.aspx
Last Accessed On: February 7, 2018