CY7C1041CV33

4-Mbit (256K x 16) Static RAM

Features Functional Description

■ Temperature ranges The CY7C1041CV33 is a high performance CMOS static RAM
❐ Commercial: 0°C to 70°C organized as 262,144 words by 16 bits.
❐ Industrial: –40°C to 85°C To write to the device, take Chip Enable (CE) and Write Enable
❐ Automotive-A: –40°C to 85°C (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
❐ Automotive-E: –40°C to 125°C from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A17). If Byte High
■ Pin and function compatible with CY7C1041BV33 Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
■ High speed is written into the location specified on the address pins (A0
❐ tAA = 10 ns (Commercial, Industrial and Automotive-A)
through A17).
❐ tAA = 12 ns (Automotive-E) To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
■ Low active power Byte Low Enable (BLE) is LOW, then data from the memory
❐ 324 mW (max) location specified by the address pins appear on IO0 to IO7. If
■ 2.0V data retention Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. For more information, see the Truth
■ Automatic power down when deselected Table on page 9 for a complete description of Read and Write
modes.
■ TTL-compatible inputs and outputs
The input and output pins (IO0 through IO15) are placed in a high
■ Easy memory expansion with CE and OE features impedance state when the device is deselected (CE HIGH), the
■ Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin outputs are disabled (OE HIGH), the BHE and BLE are disabled
TSOP II and 48-Ball FBGA packages (BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.

Logic Block Diagram

INPUT BUFFER

A0
A1
ROW DECODER

SENSE AMPS

A2
A3 256K x 16
A4
RAM Array IO0–IO7
A5
A6 IO8–IO15
A7
A8

COLUMN DECODER

BHE
WE
CE
A11
A12

A14
A10

A16
A17
A15
A9

A13

OE
BLE

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05134 Rev. *J Revised March 22, 2010

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Selection Guide
Description -10 -12 -15 -20 Unit
Maximum Access Time 10 12 15 20 ns
Maximum Operating Current Commercial 90 85 80 75 mA
Industrial 100 95 90 85 mA
Automotive-A 100 85 mA
Automotive-E 120 90 mA
Maximum CMOS Standby Current Commercial/ 10 10 10 10 mA
Industrial
Automotive-A 10 10 mA
Automotive-E 15 15 mA

Pin Configuration
Figure 1. 44-Pin SOJ/TSOP II (Top View) [1] Figure 2. 48-Ball FBGA Pinout (Top View) [1]

A0 1 44 A17 1 2 3 4 5 6
A1 2 43 A16
A2 3 42 A15 A0 A1 A2 NC A
BLE OE
A3 4 41 OE
A4 5 40 BHE
IO0 BHE A3 A4 CE IO8 B
CE 6 39 BLE
IO0 7 38 IO15
IO1 8 37 IO14 IO1 IO2 A5 A6 IO10 IO9 C
IO2 9 36 IO13
IO3 10 35 IO12 VSS IO3 A17 A7 IO11 VCC D
VCC 11 34 VSS
VSS 12 33 VCC
IO4 13 32 VCC IO4 NC A16 IO12 VSS E
IO11
IO5 14 31 IO10
IO6 15 30 IO9 IO6 IO5 A14 A15 IO13 IO14 F
IO7 16 29 IO8
WE 17 28 NC
A5 IO7 NC A12 A13 WE IO15 G
18 27 A14
A6 19 26 A13
A7 20 25 A12 NC A8 A9 A10 A11 NC H
A8 21 24 A11
A9 22 23 A10

Note
1. NC pins are not connected on the die.

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Pin Definitions
SOJ, TSOP BGA
Pin Name IO Type Description
Pin Number Pin Number
A0–A17 1–5, 18–27, A3, A4, A5, B3, Input Address Inputs. Used to select one of the address locations.
42–44 B4, C3, C4,
D4, H2, H3, H4,
H5, G3, G4, F3,
F4, E4, D3
IO0–IO15 7–10,13–16, B1, C1, C2, D2, Input or Output Bidirectional Data IO lines. Used as input or output lines depending
29–32, 35–38 E2, F2, F1, G1, on operation.
B6, C6, C5, D5,
E5, F5, F6, G6
NC 28 A6, E3, G2, H1, No Connect No Connects. Not connected to the die.
H6
WE 17 G5 Input or Write Enable Input, Active LOW. When selected LOW, a write is
Control conducted. When deselected HIGH, a read is conducted.
CE 6 B5 Input or Chip Enable Input, Active LOW. When LOW, selects the chip.
Control When HIGH, deselects the chip.
BHE, BLE 40, 39 B2, A1 Input or Byte Write Select Inputs, Active LOW. BHE controls IO16 – IO9,
Control BLE controls IO8 – IO1.
OE 41 A2 Input or Output Enable, Active LOW. Controls the direction of the IO pins.
Control When LOW, the IO pins are allowed to behave as outputs. When
deasserted HIGH, the IO pins are tri-stated and act as input data
pins.
VSS 12, 34 D1, E6 Ground Ground for the Device. Connected to ground of the system.
VCC 11, 33 D6, E1 Power Supply Power Supply Inputs to the Device.

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Maximum Ratings Static Discharge Voltage............................................ >2001V

(MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the Latch Up Current ..................................................... >200 mA
device. These user guidelines are not tested.
Storage Temperature ................................. –65C to +150C Operating Range
Ambient Temperature with Ambient
Range VCC
Power Applied ............................................ –55C to +125C Temperature (TA)
Supply Voltage on VCC Relative to GND[2] .....–0.5V to +4.6V Commercial 0C to +70C 3.3V  10%
DC Voltage Applied to Outputs Industrial –40C to +85C
in High Z State[2] ...................................... –0.5V to VCC+0.5V Automotive-A –40C to +85C
DC Input Voltage[2] .................................. –0.5V to VCC+0.5V Automotive -E –40C to +125C
Current into Outputs (LOW)......................................... 20 mA

Electrical Characteristics
Over the Operating Range
-10 -12 -15 -20
Parameter Description Test Conditions Unit
Min Max Min Max Min Max Min Max
VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC V
+ 0.3 + 0.3 + 0.3 + 0.3
VIL [2] Input LOW Voltage –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Leakage GND < VI < VCC Com’l/Ind’l –1 +1 –1 +1 –1 +1 –1 +1 A
Current Auto-A –1 +1 –1 +1
Auto-E –20 +20 –20 +20
IOZ Output Leakage GND < VOUT < VCC, Com’l/Ind’l –1 +1 –1 +1 –1 +1 –1 +1 A
Current Output disabled Auto-A –1 +1 –1 +1
Auto-E –20 +20 –20 +20
ICC VCC Operating VCC = Max, Com’l 90 85 80 75 mA
Supply Current f = fMAX = 1/tRC Ind’l 100 95 90 85
Auto-A 100 85
Auto-E 120 90
ISB1 Automatic CE Power Max VCC, Com’l/Ind’l 40 40 40 40 mA
Down Current —TTL CE > VIH Auto-A 40 40
Inputs VIN > VIH or
VIN < VIL, f = fMAX Auto-E 45 45
ISB2 Automatic CE Power Max VCC, Com’l/Ind’l 10 10 10 10 mA
Down Current — CE > VCC – 0.3V, Auto-A 10 10
CMOS Inputs VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0 Auto-E 15 15

Note
2. VIL (min) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.

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Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25C, f = 1 MHz, VCC = 3.3V 8 pF
COUT Output Capacitance 8 pF

Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions SOJ TSOP II FBGA Unit
JA Thermal Resistance Test conditions follow standard test 25.99 42.96 38.15 C/W
(Junction to Ambient) methods and procedures for measuring
JC Thermal Resistance thermal impedance, per EIA/JESD51 18.8 10.75 9.15 C/W
(Junction to Case)

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms [3]

10-ns devices: 12-, 15-, 20-ns devices:

Z = 50 R 317
OUTPUT 3.3V
OUTPUT
50  30 pF*
* CAPACITIVE LOAD CONSISTS 30 pF* R2
OF ALL COMPONENTS OF THE 1.5V 351
TEST ENVIRONMENT

(a) (b)

High-Z characteristics:
R 317
ALL INPUT PULSES 3.3V
3.0V
90% 90% OUTPUT
10% 10% 5 pF R2
GND 351

Rise Time: 1 V/ns (c) Fall Time: 1 V/ns

(d)

Note
3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown
in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).

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Switching Characteristics
Over the Operating Range [4]
-10 -12 -15 -20
Parameter Description Unit
Min Max Min Max Min Max Min Max
Read Cycle
tpower[5] VCC(Typical) to the First Access 100 100 100 100 s
tRC Read Cycle Time 10 12 15 20 ns
tAA Address to Data Valid 10 12 15 20 ns
tOHA Data Hold from Address Change 3 3 3 3 ns
tACE CE LOW to Data Valid 10 12 15 20 ns
tDOE OE LOW to Data Valid Comm’l/Ind’l/Auto-A 5 6 7 8 ns
Auto-E 7 8
tLZOE OE LOW to Low Z[6] 0 0 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 5 6 7 8 ns
tLZCE CE LOW to Low Z[6] 3 3 3 3 ns
tHZCE CE HIGH to High Z[6, 7] 5 6 7 8 ns
tPU CE LOW to Power Up 0 0 0 0 ns
tPD CE HIGH to Power Down 10 12 15 20 ns
tDBE Byte Enable to Data Valid Comm’l/Ind’l/Auto-A 5 6 7 8 ns
Auto-E 7 8
tLZBE Byte Enable to Low Z 0 0 0 0 ns
tHZBE Byte Disable to High Z 6 6 7 8 ns
Write Cycle[8, 9]
tWC Write Cycle Time 10 12 15 20 ns
tSCE CE LOW to Write End 7 8 10 10 ns
tAW Address Setup to Write End 7 8 10 10 ns
tHA Address Hold from Write End 0 0 0 0 ns
tSA Address Setup to Write Start 0 0 0 0 ns
tPWE WE Pulse Width 7 8 10 10 ns
tSD Data Setup to Write End 5 6 7 8 ns
tHD Data Hold from Write End 0 0 0 0 ns
tLZWE WE HIGH to Low Z[6] 3 3 3 3 ns
tHZWE WE LOW to High Z[6, 7] 5 6 7 8 ns
tBW Byte Enable to End of Write 7 8 10 10 ns

Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads and Waveforms on page 5. Transition is measured 500
mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[10, 11]

tRC
RC

ADDRESS

tAA
tOHA

DATA OUT PREVIOUS DATA VALID DATA VALID

Figure 5. Read Cycle No. 2 (OE Controlled)[11, 12]

ADDRESS

tRC
CE

tACE

OE
tHZOE
tDOE
BHE, BLE tLZOE
tHZCE
tDBE
tLZBE
tHZBE
HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
tPD
VCC tPU ICC
SUPPLY 50% 50%
ISB
CURRENT

Notes
10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.

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Switching Waveforms (continued)

Figure 6. Write Cycle No. 1 (CE Controlled)[13, 14]

tWC

ADDRESS

tSA tSCE
CE

tAW
tHA
tPWE

WE

tBW

BHE, BLE

tSD tHD

DATA IO

Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)

tWC

ADDRESS

tSA tBW
BHE, BLE

tAW
tHA
tPWE

WE
tSCE

CE

tSD tHD

DATA IO

Notes
13. Data IO is high impedance if OE, BHE, and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

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Switching Waveforms (continued)

Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)

tWC

ADDRESS

tSCE
CE

tAW
tHA
tSA
tPWE
WE

tBW
BHE, BLE

tHZWE tSD tHD

DATA IO

tLZWE

Truth Table
CE OE WE BLE BHE IO0 – IO7 IO8 – IO15 Mode Power
H X X X X High Z High Z Power Down Standby (ISB)
L L H L L Data Out Data Out Read – All Bits Active (ICC)
L H Data Out High Z Read – Lower Bits Only Active (ICC)
H L High Z Data Out Read – Upper Bits Only Active (ICC)
L X L L L Data In Data In Write – All Bits Active (ICC)
L H Data In High Z Write – Lower Bits Only Active (ICC)
H L High Z Data In Write – Upper Bits Only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)

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Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed Package Operating
Ordering Code Package Type
(ns) Diagram Range
10 CY7C1041CV33-10VXC 51-85082 44-pin (400-mil) Molded SOJ (Pb-Free) Commercial
CY7C1041CV33-10ZXC 51-85087 44-pin TSOP II (Pb-Free)
CY7C1041CV33-10ZXI 44-pin TSOP II (Pb-Free)
CY7C1041CV33-10BAXA 51-85106 48-ball Fine Pitch BGA (Pb-Free) Automotive-A
CY7C1041CV33-10ZSXA 51-85087 44-pin TSOP II (Pb-Free)
12 CY7C1041CV33-12BAXE 51-85106 48-ball Fine Pitch BGA (Pb-Free) Automotive-E
CY7C1041CV33-12ZSXE 51-85087 44-pin TSOP II (Pb-Free)
20 CY7C1041CV33-20ZSXA 51-85087 44-pin TSOP II (Pb-Free) Automotive-A
CY7C1041CV33-20VXE 44-pin (400-mil) Molded SOJ (Pb-Free) Automotive-E
CY7C1041CV33-20ZSXE 44-pin TSOP II (Pb-Free)
Please contact your local Cypress sales representative for availability of these parts

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Package Diagrams
Figure 9. 44-Pin (400 Mil) Molded SOJ, 51-85082

51-85082 *C

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Package Diagrams (continued)

Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087

51-85087 *C

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Package Diagrams (continued)

Figure 11. 48-Ball FBGA (7 x 8.5 x 1.2 mm), 51-85106

51-85106 *F

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Document History Page

Document Title: CY7C1041CV33, 4-Mbit (256K x 16) Static RAM
Document Number: 38-05134
Issue Orig. of
REV. ECN NO. Description of Change
Date Change
** 109513 12/13/01 HGK New Data Sheet
*A 112440 12/20/01 BSS Updated 51-85106 from revision *A to *C
*B 112859 03/25/02 DFP Added CY7C1042CV33 in BGA package
Removed 1042 BGA option pin ACC Final Data Sheet
*C 116477 09/16/02 CEA Add applications foot note to data sheet
*D 119797 10/21/02 DFP Added 20-ns speed bin
*E 262949 See ECN RKF 1) Added Lead (Pb)-Free parts in the Ordering info (Page #9)
2) Added Automotive Specs to Datasheet
*F 361795 See ECN SYT Added Pb-Free offerings in the Ordering Information
*G 435387 See ECN NXR Removed -8 Speed bin from Product offering.
Corrected typo in description for BHE/BLE in pin definitions table on Page# 3
corrected their Pin name from OE2 to OE.
Included the Maximum Ratings for Static Discharge Voltage and Latch up Current.
Changed the description of IIX current from Input Load Current to
Input Leakage Current
Added note# 4 on page# 4
Updated the Ordering Information table
*H 499153 See ECN NXR Added Automotive-A Operating Range
Changed tpower value from 1 s to 100 s
Updated Ordering Information table
*I 2104110 See ECN VKN/AESA Added Automotive-E specs for 12 ns speed
Updated Ordering Information table
*J 2897141 03/22/10 AJU/VIVG Removed inactive parts. Updated package diagrams.

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Document Number: 38-05134 Rev. *J Revised March 22, 2010 Page 14 of 14

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