STD1LNK60Z-1

STQ1NK60ZR - STN1NK60Z
N-CHANNEL 600V 13Ω 0.8A TO-92/IPAK/SOT-223
Zener-Protected SuperMESH™MOSFET

Table 1: General Features Figure 1: Package

TYPE VDSS RDS(on) ID Pw
STQ1NK60ZR 600 V < 15 Ω 0.3 A 3W
STD1LNK60Z-1 600 V < 15 Ω 0.8 A 25 W
STN1NK60Z 600 V < 15 Ω 0.3 A 3.3 W
■ TYPICAL RDS(on) = 13Ω
■ EXTREMELY HIGH dv/dt CAPABILITY
■ ESD IMPROVED CAPABILITY TO-92 (Ammopack) TO-92
■ 100% AVALANCHE TESTED
■ NEW HIGH VOLTAGE BENCHMARK 2
■ GATE CHARGE MINIMIZED
3 3
2 2
1 1

DESCRIPTION IPAK SOT-223

The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to Figure 2: Internal Schematic Diagram
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS-
FETs including revolutionary MDmesh™ products.

APPLICATIONS
■ AC ADAPTORS AND BATTERY CHARGERS

■ SWITH MODE POWER SUPPLIES (SMPS)

Table 2: Order Codes

SALES TYPE MARKING PACKAGE PACKAGING
STQ1NK60ZR Q1NK60ZR TO-92 BULK
STQ1NK60ZR-AP Q1NK60ZR TO-92 AMMOPAK
STD1LNK60Z-1 D1LNK60Z IPAK TUBE
STN1NK60Z N1NK60Z SOT-223 TAPE & REEL

Rev. 5
February 2005 1/13
STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

Table 3: Absolute Maximum ratings

Symbol Parameter Value Unit
IPAK TO-92 SOT-223
VDS Drain-source Voltage (VGS = 0) 600 V
VDGR Drain-gate Voltage (RGS = 20 kΩ) 600 V
VGS Gate- source Voltage ± 30 V
ID Drain Current (continuous) at TC = 25°C 0.8 0.3 0.3 A
ID Drain Current (continuous) at TC = 100°C 0.5 0.189 0.189 A
IDM (
) Drain Current (pulsed) 3.2 1.2 1.2 A
PTOT Total Dissipation at TC = 25°C 25 3 3.3 W
Derating Factor 0.24 0.025 0.026 W/°C
VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) 800 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
Tj Operating Junction Temperature
-55 to 150 °C
Tstg Storage Temperature
(
) Pulse width limited by safe operating area
(1) ISD ≤0.3A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.

Table 4: Thermal Data

IPAK TO-92 SOT-223
Rthj-case Thermal Resistance Junction-case Max 5 -- -- °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 100 120 37.87(#) °C/W
Rthj-lead Thermal Resistance Junction-lead Max -- 40 -- °C/W
Tl Maximum Lead Temperature For Soldering Purpose 275 260 260 °C
(#) When mounted on 1 inch² Fr-4 board, 2 Oz Cu
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive 0.8 A
(pulse width limited by Tj max)
EAS Single Pulse Avalanche Energy 60 mJ
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

Table 6: Gate-Source Zener Diode

Symbol Parameter Test Conditions Min. Typ. Max. Unit
BVGSO Gate-Source Breakdown Igs=± 1mA (Open Drain) 30 V
Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.

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ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

Table 7: On /Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source ID = 1 mA, VGS = 0 600 V
Breakdown Voltage
IDSS Zero Gate Voltage VDS = Max Rating
Drain Current (VGS = 0) 1 µA
VDS = Max Rating,
50 µA
TC = 125 °C
IGSS Gate-body Leakage VGS = ± 20V ±10 µA
Current (VDS = 0)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 50 µA 3 3.75 4.5 V
RDS(on) Static Drain-source On VGS = 10V, ID = 0.4 A 13 15 Ω
Resistance

Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (1) Forward Transconductance VDS = V, ID = 0.4 A 0.5 S
Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 94 pF
Coss Output Capacitance 17.6 pF
Crss Reverse Transfer 2.8 pF
Capacitance
Coss eq. (3) Equivalent Output VGS = 0V, VDS = 0V to 480V 11 pF
Capacitance
td(on) Turn-on Delay Time 5.5 ns
Rise Time VDD = 300V, ID = 0.4 A 5 ns
tr
Turn-off-Delay Time RG = 4.7Ω VGS = 10 V 13 ns
td(off)
Fall Time (see Figure 21) 28 ns
tf
Qg Total Gate Charge VDD = 480V, ID = 0.8 A, 4.9 6.9 nC
Qgs Gate-Source Charge VGS = 10V 1 nC
Qgd Gate-Drain Charge (see Figure 25) 2.7 nC

Table 9: Source Drain Diode

Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 0.8 A
ISDM (2) Source-drain Current (pulsed) 2.4 A
VSD (1) Forward On Voltage ISD = 0.8A, VGS = 0 1.6 V
trr Reverse Recovery Time ISD = 0.8 A, di/dt = 100A/µs 135 ns
Qrr Reverse Recovery Charge VDD = 20V, Tj = 25°C 216 nC
IRRM Reverse Recovery Current (see Figure 23) 3.2 A
trr Reverse Recovery Time ISD = 0.8 A, di/dt = 100A/µs 140 ns
Qrr Reverse Recovery Charge VDD = 20V, Tj = 150°C 224 nC
IRRM Reverse Recovery Current (see Figure 23) 3.2 A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80%
VDSS.

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STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

Figure 3: Safe Operating Area for IPAK Figure 6: Thermal Impedance for IPAK

Figure 4: Safe Operating Area for TO-92 Figure 7: Thermal Impedance for TO-92

Figure 5: Safe Operating Area for SOT-223 Figure 8: Thermal Impedance for SOT-223

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Figure 9: Output Characteristics Figure 12: Transfer Characteristics

Figure 10: Transconductance Figure 13: Statis Drain-Source On Resistance

Figure 11: Gate Charge vs Gate-source Voltage Figure 14: Capacitance Variation

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Figure 15: Normalized Gate Thereshold Volt- Figure 18: Normalized On Resistance vs Tem-
age vs Temperature perature

Figure 16: Source-Drain Diode Forward Char- Figure 19: Normalized BVdss vs Temperature
acteristics

Figure 17: Maximum Avalanche Energy vs Figure 20: Max Id Current vs Tc

Temperature

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Figure 21: Unclamped Inductive Load Test Cir- Figure 24: Unclamped Inductive Wafeform
cuit

Figure 22: Switching Times Test Circuit For Figure 25: Gate Charge Test Circuit
Resistive Load

Figure 23: Test Circuit For Inductive Load

Switching and Diode Recovery Times

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STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

TO-251 (IPAK) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A3 0.7 1.3 0.027 0.051
B 0.64 0.9 0.025 0.031
B2 5.2 5.4 0.204 0.212
B3 0.85 0.033
B5 0.3 0.012
B6 0.95 0.037
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 15.9 16.3 0.626 0.641
L 9 9.4 0.354 0.370
L1 0.8 1.2 0.031 0.047
L2 0.8 1 0.031 0.039

H
C
A

A3
C2

A1

L2 D L
B3

B6

B5
B
3
=

=
B2

G
E

2
=

=
1

L1
0068771-E

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 STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

TO-92 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.32 4.95 0.170 0.194
b 0.36 0.51 0.014 0.020
D 4.45 4.95 0.175 0.194
E 3.30 3.94 0.130 0.155
e 2.41 2.67 0.094 0.105
e1 1.14 1.40 0.044 0.055
L 12.70 15.49 0.50 0.610
R 2.16 2.41 0.085 0.094
S1 0.92 1.52 0.036 0.060
W 0.41 0.56 0.016 0.022
V 5° 5°

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STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

TO-92 AMMOPACK

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A1 4.45 4.95 0.170 0.194
T 3.30 3.94 0.130 0.155
T1 1.6 0.06
T2 2.3 0.09
d 0.41 0.56 0.016 0.022
P0 12.5 12.7 12.9 0.49 0.5 0.51
P2 5.65 6.35 7.05 0.22 0.25 0.27
F1, F2 2.44 2.54 2.94 0.09 0.1 0.11
delta H -2 2 -0.08 0.08
W 17.5 18 19 0.69 0.71 0.74
W0 5.7 6 6.3 0.22 0.23 0.24
W1 8.5 9 9.25 0.33 0.35 0.36
W2 0.5 0.02
H 18.5 20.5 0.72 0.80
H0 15.5 16 16.5 0.61 0.63 0.65
H1 25 0.98
D0 3.8 4 4.2 0.15 0.157 0.16
t 0.9 0.035
L 11 0.43
l1 3 0.11
delta P -1 1 -0.04 0.04

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 STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

SOT-223 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 1.80 0.071

B 0.60 0.70 0.80 0.024 0.027 0.031

B1 2.90 3.00 3.10 0.114 0.118 0.122

c 0.24 0.26 0.32 0.009 0.010 0.013

D 6.30 6.50 6.70 0.248 0.256 0.264

e 2.30 0.090

e1 4.60 0.181

E 3.30 3.50 3.70 0.130 0.138 0.146

H 6.70 7.00 7.30 0.264 0.276 0.287

V 10o 10o

A1 0.02

P008B

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Table 10: Revision History

Date Revision Description of Changes

19-Mar-2003 1 First Release
15-May-2003 2 Removed DPAK
09-Jun-2003 3 Final Datasheet
17-Nov-2004 4 Inserted SOT-223.
15-Feb-2005 5 Modified Curve 4

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