Practical 2

Aim: Implementation of basic logic gates and its testing.

Software used: ALTERA MAX+plus II 9.3

Program:

library ieee;
use ieee.std_logic_1164.all;

entity allgates is
port ( a,b : in bit;
c1,c2,c3,c4,c5,c6 : out bit);
end allgates;

architecture all_gates of allgates is

begin
c1<=a and b;
c2<=a or b;
c3<=not a;
c4<=a nor b;
c5<=a nand b;
c6<=not (a nor b);
end all_gates;
 Practical 3

Aim: Implementation of adder circuits and its testing.

Software used: ALTERA MAX+plus II 9.3

Program (Half Adder):

• HALF ADDER WITH DATA FLOW METHOD

library ieee;
use ieee.std_logic_1164.all;

entity half_add is
port ( a,b : in bit;
sum, carry : out bit);
end half_add;

architecture half_adder of half_add is

begin
sum <= (a xor b);
carry <= (a and b);
end half_adder;

• HALF ADDER WITH BEHAVIORAL METHOD

library ieee;
use ieee.std_logic_1164.all;

entity half_add is
port ( a,b : in bit;
sum, carry : out bit);
end half_add;

architecture half_adder of half_add is

begin
process(a,b)
begin
sum <= (a xor b);
 carry <= (a and b);
end process;
end half_adder;

• HALF ADDER WITH STRUCTURAL METHOD (main program)

library ieee;
use ieee.std_logic_1164.all;

entity half_add is
port( a,b:in bit;
sum,carry: out bit);
end half_add;

architecture half_adder of half_add is

component and_1
port( x,y: in bit;
z: out bit);
end component;

component xor_1
port( x1,y1: in bit;
z1: out bit);
end component;

begin
d1:xor_1 port map (a, b, sum);
d2:and_1 port map (a, b, carry);
end half_adder;

• Two input AND gate called from main program

library ieee;
use ieee.std_logic_1164.all;

entity and_1 is
port ( x, y: in bit;
z: out bit);
end and_1;

architecture and1 of and_1 is

begin
z <= x and y;
end and1;
 • Two input XOR gate called from main program

library ieee;
use ieee.std_logic_1164.all;

entity xor_1 is
port ( x1,y1:in bit;
z1 : out bit);
end xor_1;

architecture xor1 of xor_1 is

begin
z1 <= x1 xor y1;
end xor1;

Program (Full Adder):

• FULL ADDER WITH DATA FLOW METHOD

library ieee;
use ieee.std_logic_1164.all;

entity full_add is
port ( a,b,c : in bit;
sum, carry : out bit);
end full_add;

architecture full_adder of full_add is

begin
sum <= (a xor b) xor c;
carry <= (a and b) or ((a xor b) and c);
end full_adder;

• FULL ADDER WITH BEHAVIORAL METHOD

library ieee;
use ieee.std_logic_1164.all;

entity full_add is
 port ( a,b,c : in bit;
sum, cout : out bit);
end full_add;

architecture full_adder of full_add is

begin
process(a,b,c)
variable x,y,z : bit;
begin
x:= (a xor b);
y:= (a and b);
z:= (x and c);
sum <= (x xor c);
cout <= (y or z);
end process;
end full_adder;

• FULL ADDER WITH STRUCTURAL METHOD (main program)

library ieee;
use ieee.std_logic_1164.all;

entity full_add is
port( a,b,c:in bit;
sum,cout:out bit);
end full_add;

architecture full_adder of full_add is

component and_1
port( x,y:in bit;
z:out bit);
end component;

component xor_1
port( x1,y1:in bit;
z1:out bit);
end component;

component or_1
port( x2,y2:in bit;
z2:out bit);
end component;
 signal p1,p2,p3:bit;

begin
d1:xor_1 port map(a,b,p1);
d2:xor_1 port map(p1,c,sum);
d3:and_1 port map(a,b,p2);
d4:and_1 port map(p1,c,p3);
d5:or_1 port map(p2,p3,cout);
end full_adder;

• Two input AND gate called from main program

library ieee;
use ieee.std_logic_1164.all;

entity and_1 is
port ( x, y: in bit;
z: out bit);
end and_1;

architecture and1 of and_1 is

begin
z <= x and y;
end and1;

• Two input XOR gate called from main program----

library ieee;
use ieee.std_logic_1164.all;

entity xor_1 is
port ( x1,y1:in bit;
z1 : out bit);
end xor_1;

architecture xor1 of xor_1 is

begin
z1 <= x1 xor y1;
end xor1;
• Two input OR gate called from main program

library ieee;
use ieee.std_logic_1164.all;

entity or_1 is
port (x2, y2: in bit;
z2: out bit);
end or_1;
architecture or1 of or_1 is
begin
z2 <= x2 or y2;
end or1;
 Practical 4

Aim: Implementation of the 4 to 1 multiplexer and its testing.

Software used: ALTERA MAX+plus II 9.3

Program:

• 4X1 MULTIPLEXER WITH DATA FLOW METHOD

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port( d0,d1,d2,d3,s0,s1 : in bit;
y : out bit);
end mux;

architecture multiplexer of mux is

begin
y <= ((d0 and (not s0) and (not s1)) or (d1 and (not
s0) and s1) or (d2 and s0 and not s1)) or (d3
and s0 and s1));

end multiplexer;

• 4 x 1 MULTIPLEXER WITH STRUCTURAL METHOD (main program)

library ieee;
use ieee.std_logic_1164.all;

entity mux is

port( d0,d1,d2,d3,s0,s1 : in bit;

y : out bit);
end mux;

architecture multiplexer of mux is

 component and_1
port( l,m,n:in bit;
z:out bit);
end component;

component not_1
port( l1:in bit;
z1:out bit);
end component;

component or_1
port( l2,m2,n2,x2:in bit;
z2:out bit);
end component;

signal p1,p2,a,b,c,d: bit;

begin

u1:not_1 port map(s0,p1);

u2:not_1 port map(s1,p2);
u3:and_1 port map(d0,p1,p2,a);
u4:and_1 port map(d1,p1,s1,b);
u5:and_1 port map(d2,s0,p2,c);
u6:and_1 port map(d3,s0,s1,d);
u7:or_1 port map(a,b,c,d,y);

end multiplexer;

• Three input AND gate called from main program

library ieee;
use ieee.std_logic_1164.all;

entity and_1 is
port ( l,m,n: in bit;
z: out bit);
end and_1;

architecture and1 of and_1 is

begin
z <=( l and m and n);
end and1;
• NOT gate called from main program

library ieee;
use ieee.std_logic_1164.all;

entity not_1 is
port ( l1: in bit;
z1: out bit);
end not_1;
architecture not1 of not_1 is
begin
z1 <= (not l1);
end not1;

• Four input OR gate called from main program

library ieee;
use ieee.std_logic_1164.all;

entity or_1 is
port ( l2,m2,n2,x2: in bit;
z2: out bit);
end or_1;
architecture or1 of or_1 is
begin
z2 <= (l2 or m2 or n2 or x2);
end or1;
 • 4X1 MULTIPLEXER WITH BEHAVIORAL METHOD

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port( d0,d1,d2,d3 : in std_logic;
s: in std_logic_vector(1 downto 0);
y : out std_logic);
end mux;

architecture multiplexer of mux is

begin
process (d0,d1,d2,d3,s)
begin
case s is
when "00" => y <= d0;
when "01" => y <= d1;
when "10" => y <= d2;
when "11" => y <= d3;
when others => y <= null;
end case;
end process;
end multiplexer;
 Practical 5

Aim: Implementation of 3 x 8 decoder and its testing.

Software used: ALTERA MAX+plus II 9.3

Program:

• 3X8 DECODER WITH DATA FLOW METHOD

library ieee;
use ieee.std_logic_1164.all;

entity decoder is
port (a,b,c:in std_logic;
d0,d1,d2,d3,d4,d5,d6,d7:out std_logic);
end decoder;

architecture dec of decoder is

signal p1,p2,p3:std_logic;

begin
p1<=(not a);
p2<=(not b);
p3<=(not c);
d0<=(p1 and p2 and p3);
d1<=(p1 and p2 and c);
d2<=(p1 and b and p3);
d3<=(p1 and b and c);
d4<=(a and p2 and p3);
d5<=(a and p2 and c);
d6<=(a and b and p3);
d7<=(a and b and c);
end dec;

• 3X8 DECODER WITH STRUCTURAL METHOD

library ieee;
use ieee.std_logic_1164.all;

entity decoder is
 port(a,b,c:in std_logic;
d0,d1,d2,d3,d4,d5,d6,d7:out std_logic);
end decoder;

architecture dec of decoder is

component and_1
port(l,m,n :in std_logic;
z :out std_logic);
end component;

component not_1
port(l1 :in std_logic;
z1 :out std_logic);
end component;

signal p1,p2,p3 :std_logic;

begin
u1: not_1 port map(a,p1);
u2: not_1 port map(b,p2);
u3: not_1 port map(c,p3);
u4: and_1 port map(p1,p2,p3,d0);
u5: and_1 port map(p1,p2,c,d1);
u6: and_1 port map(p1,b,p3,d2);
u7: and_1 port map(p1,b,c,d3);
u8: and_1 port map(a,p2,p3,d4);
u9: and_1 port map(a,p2,c,d5);
u10: and_1 port map(a,b,p3,d6);
u11: and_1 port map(a,b,c,d7);
end dec;

• 3 input AND gate called from main program

library ieee;
use ieee.std_logic_1164.all;

entity and_1 is
port (l,m,n: in bit;
z: out bit);
end and_1;
architecture and1 of and_1 is
begin
z <= l and m and n;
end and1;
• NOT gate called from main program
library ieee;
use ieee.std_logic_1164.all;

entity not_1 is
port (l1: in bit;
z1: out bit);
end not_1;
architecture not1 of not_1 is
begin
z1 <= (not l1);
end not1;

• 3X8 DECODER WITH BEHAVIOURAL METHOD

library ieee;
use ieee.std_logic_1164.all;

entity decoder is
port (a:in std_logic_vector(0 to 2);
d:out std_logic_vector(0 to 7));
end decoder;

architecture dec of decoder is

begin
process(a)
begin
case a is
when "000"=> d<="10000000";
when "001"=> d<="01000000";
when "010"=> d<="00100000";
when "011"=> d<="00010000";
when "100"=> d<="00001000";
when "101"=> d<="00000100";
when "110"=> d<="00000010";
when "111"=> d<="00000001";
when others=>null;
end case;
end process;
end dec;
 Practical 6

Aim: Implementation of D flipflop, JK flipflop and T flipflop and its testing.

Software used: ALTERA MAX+plus II 9.3

Program (D flipflop) :

library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(clk,d :in bit;
q :out bit);
end dff;

architecture dflipfl of dff is

begin
process(d,clk)
begin
if clk='1' then q<=d;
end if;
end process;
end dflipfl;

Program (JK flipflop) :

library ieee;
use ieee.std_logic_1164.all;

entity jkff is

port (j,k,clk: in std_logic;

q,qn: out std_logic);
end jkff;

architecture jkflipfl of jkff is

begin
process (j,k,clk)
variable temp: std_logic;
begin
if clk='0' and clk'event then
 if j='0'and k='0' then
temp:=temp;
end if;

if j='0'and k='1' then

temp:=j;
end if;

if j='1'and k='0' then

temp:=j;
end if;

if j='1'and k='1' then

temp:=not temp;
end if;

end if;

q<=temp;
qn<=not temp;

end process;
end jkflipfl;

Program (T flipflop) :

library ieee;
use ieee.std_logic_1164.all;

entity tff is

port (t,clk: in std_logic;

q,qn: out std_logic);
end tff;

architecture tflipfl of tff is

begin
process (t,clk)
variable temp: std_logic;
begin
if clk='1' and clk'event then
 if t='1' then
temp:=not temp;
end if;

if t='0' then
temp:=temp;
end if;

end if;
q<=temp;
qn<=not temp;
end process;
end tflipfl;
 Practical 7

Aim: Implementation of BCD counter and its testing.

Software used: ALTERA MAX+plus II 9.3

Program:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port (clk, rst :in std_logic;
out1 :out std_logic_vector(0 to 3));
end counter;

architecture count of counter is

signal temp : std_logic_vector (0 to 3);
begin
process (clk, rst)
begin
if rst = '1' then
temp <= "0000";
elsif ( clk = '1' and clk'event) then
if temp = "1001" then
temp<="0000";
end if;
temp <= temp + 1;
end if;
end process;
out1 <= temp;
end count;
Waveform: