Topic 11:

Interrupts
ISMAIL ARIFFIN
FKE UTM SKUDAI JOHOR
 Objective
• To become familiar with interrupts on the AVR
– Maskable and non-maskable
– Initialization
– Triggers
• To develop interrupt service routines (ISRs) to handle
interrupts
• To understand the sequence of events that occur
when an IRQ occurs
 Interrupts
• Interrupts are asynchronous changes in program
flow that occur as a result of events outside the
running program.
– They are usually hardware related:
Examples: button press, timer expiration,
peripheral device needs data, etc
– Interrupt conditions are independent of the
program. Interrupts can happen at any time
(asynchronous)
Maskable/Non-maskable
• Interrupts in general can be divided into two kinds
• - maskable and non-maskable.
– A maskable interrupt is an interrupt whose
trigger event is not always important:
• The program can decide if the event should
be recognized or ignored and can be
disabled/enabled
– A non-maskable interrupt is so important that it
should never be ignored
• The processor will always jump to this
interrupt when it happens
• The reset button is an example.
 AVR Interrupt
o Interrupt is an event that deviates a microcontroller to run
another program for a short while from the normal program.
o Interrupt requires a request for AVR from an input either it is
an internal or external.
o Each interrupt request has its own program routine referred
as interrupt service routine (in short ISR).
o AVR Atmega32 has allocated three requests for external and
many requests for internal interrupts.
o Interrupts in microcontroller are prioritized and vectored.
Each interrupt has a priority vector number and a vector
location. In AVR, interrupts are declared in program memory
at their own vector locations.
 Interrupt Vector Table
(AVR Atmega32 Interrupt List)

6
Interrupt Vector Table for ATmega32
(ATmega32A)

7
 Interrupt versus Polling
o AVR on input request or command
– Polling
o The AVR inspects all input requests or commands routinely non-
stop. AVR branches to the task program for the requested input.
– Interrupt
o An asynchronous request or command to deviate AVR to run a
special program from running the normal program. The AVR run
the special program after it is being triggered by the input
command.
o Upon receiving the input signal, AVR stops running the main
program, deviate to the special program, finish and back running
the main program.
o The special program that belongs to interrupt request is called an
interrupt service routine (ISR) or an interrupt handler.
 Interrupt vs Polling

Interrupts Polling
• Efficient use of CPU • Not and efficient use of CPU
• Can serve many devices, which each • Cannot assign priority, it checks all
device get attention of the CPU based on devices in a round-robin fashion.
the priority assigned to it.
• The CPU can ignore (mask) a device • Cannot ignore device request.
request for service.
• Avoid tying down the CPU, thus the • Wastes much CPU time by polling device
waste time can be used to perform some that do not need service.
useful tasks.
 Interrupts in ATmega32
• AVR external interrupt requests are the INT2, INT1 INT0 to be
triggered at pin PB2, PD3 and PD2 of AVR respectively.
– Triggering signal option to initiate an interrupt request:
• A high-to-low transition (a falling edge) on one of these
pins
• A low-to-high transition (a rising edge) on one of these
pins
• A low level on one of these pins
– Triggering signal option is initialized in register:
• MCUCR for INT0 and INT1
• MCUCSR for INT2.
 Interrupt Service Routine
o For every interrupt, there must be ISR, since when an interrupt
is invoked, AVR runs the ISR.
o Generally, for every ISR there is a fixed location in memory that
holds the address of its ISR.
o The group of memory locations set aside to hold the addresses
of ISRs s called interrupt vector table.
o Vector interrupt is used to bridge between the triggering
interrupt input and the interrupt’s assigned (software) task.
o All interrupts involved are vectorily initialized at the beginning
of the AVR main program to provide link to its own interrupt
service routine. ISR has its own AVR task. ISR is located before
the AVR main program.
 Steps in executing an interrupt
o Upon activation of an interrupt, the AVR goes through
the following steps:
1. It finishes the instruction it s currently executing
and saves the address of the next instruction (PC)
on the stack.
2. Jumps to a fixed location in memory called the
interrupt vector table. The interrupt vector table
directs the AVR to the address of ISR.
3. AVR starts execute and returns to the place where
it was interrupted – gets the PC address from the
stack.
 Steps in executing an interrupt

Address Code
PB0 1 40 VCC #INCLUDE <avr/interrupt.h>
PB1 2 39 PA0 (ADC0)
0002 0000 jump main
(INT2) PB2 3 38 PA1 (ADC1)
0002
(OC0/AIN0) PB3 4 37 PA2 (ADC2)
0002 jump INT0_vect
(SS) PB4 5 ATmega32 36 PA3 (ADC3) 0004
(MOSI) PB5 6 35 PA4 (ADC4) 0005
(MISO) PB6 7 34 PA5 (ADC5)
0006 int main () {
(SCK) PB7 8 PC: 0016
0015
0014
0013
0012
000A
000D
0009
000B
000C
0008
0006
000F
000E
0004
0007
0005
0000 33 PA6 (ADC6)
0007 DDRC = 1 << PC3 ; //PC.3 = output
0008 PORTD=1 << PD2 ;//pull-up activated
RESET 9 32 PA7 (ADC7) 0009 GICR= 1<<INT0 ;//Enable INT0
VCC 10 31 AGND 000A SEI() ;//Set I (Enable Interrupts)
GND 11 30 AVCC
000B num1= 3 ;
000C num2 = 4 ;
XTAL2 12 29 PC7 (TOSC2)
000D sum = num1 + num2 ;
XTAL1 13 28 PC6 (TOSC1) 000E while (1);
(RXD) PD0 14 27 PC5 (TDI) 000F return 1;
(TXD) PD1 15 SP 26 PC4 (TDO)
0010 }

(INT0) PD2 16 25 PC3 (TMS)

0012 void ISR(iINTO_vect){
(INT1) PD3 17 24 PC2 (TCK) 0013 volatiile unsigned char int0data ;
0014
(OC1B) PD4 18 Stack 23 PC1 (SDA)
0015
int0data=PORTC^0X08;
PORTC = int0data;
(OC1A) PD5 19 22 PC0 (SCL)
0016 }
(ICP) PD6 20 21 PD7 (OC2)
Interrupt Units in AVR
 Enabling and Disabling An Interrupt
o Upon reset, all interrupts are disabled (masked) – none will be
responded to by AVR if they are activated.
o The interrupt must be enabled (unmasked) for AVR to respond to them.
o How? – The D7 bit of SREG responsible to enable and disable the
interrupt globally.

o Bit D7 (I) of SREG must be set HIGH to allow interrupt to happen( enable)
by using SEI instruction (I = 1). To disable use CLI instruction (I = 0).
o But there are some I/O registers holding interrupt enable bits even
though I = 1, i.e. TIMSK register has interrupt enable bit for Timer0,
Timer1 and Timer2.
Enabling and Disabling An Interrupt
External Interrupt Programming
 Programming External Interrupt
o There are three external hardware interrupt:
o INT0 – located on pin PD2, vector table location $2
o INT1 – located on pin PD3, vector table location $4
o INT3 – located on pin PB2, vector table location $6
o The hardware interrupts must be enabled before they can take effect.
o This is done using INTx bit located in the GICR register.
 Programming External Interrupt
o Example: the following instruction enable INT0.

GICR = 0x40 ; // Enable external interrupt INT0 (PD2 – pin 16)

o The INT0 is a low-level-triggered interrupt by default – when a low signal

is applied to pin PD2, the controller will be interrupted and jump to
location $0002 in the vector table to service ISR.
o Example: Assume that the INT0 pin is connected to a switch that is normally high.
Write a program that toggles PORTC.3, whenever the INT0 pin goes low.
#include <avr/io.h>
#include <avr/interrupt.h>
void ISR(INT0_vect)
{
portc = ~portc ; //toggle PC3 Programming
}
void initint(void ) { External Interrupt
ddrd = ddrd & ~ (1 << int0) ; // portd2 as input
portd = portd | 1 << int0 ; // pull-up portd2
gicr = 1 << int0 ; // enable int0
mcucr = 0b00000011 ;// low level input trigger
sei () ; // enable global interrupt
}
int main (void) {
ddrc = ddrc | 1 << portc3 ; // portc3 as output
portc = portc | 1 << portc3 ; // initial PC3 high
initint();
while (1) {
// loop forever wait for INT0 interrupt
What
} happen by time micro-p execute RETI
andreturn
INT0 still
1 ; LOW?
}
 Programming External Interrupt
o Example: Assume that the INT0 pin is connected to a switch that is
normally high. Write a program that toggles PORTC.3, whenever the INT0
pin goes low.

What happen by time micro-p execute RETI

and INT0 still LOW?
 Programming External Interrupt: Edge vs Level Triggered
o There are two types of activation for the external hardware interrupts:
o Level triggered – INT0 & INT1
o Edge triggered – INT0, INT1 & INT2.
o The ISC2 bit of the MCUCSR register indicate whether INT2 is active in
the falling edge or rising edge.
 Programming External Interrupt: Edge vs Level Triggered
o The bits for the MCUCR register indicate the trigger option of INT0 and
INT1.
 Programming External Interrupt: Edge vs Level Triggered
o Example: show the instruction (a) make INT0 falling edge triggered, (b)
make INT1 triggered on any change, and (c) make INT2 rising edge
triggered.

a) MCUCR = 0X02

b) MCUCR = (1<<ISC10) ; //MCUCR = 0x04

c) MCUCR =(1<<ISC2) ; // MCUCR = 0x40

 Programming External Interrupt: Edge vs Level Triggered
o Example: Rewrite previous switch example, so that whenever INT0 goes
low, it toggles PORTC.3 only once.
 Example C codes that initialise External
Interrupt INT0 and INT1 only
//Interrupt.h file declaration

//Enable INT0 and INT1

ddrd = ddrd | ~ (1<< Int0) ; //set INT0 pin as input
portd = portd | 1<< int0 ; //enable pull-up resistor on INT0 pin
ddrd = ddrd | ~ (1 << int1) ; //set INT1 pin as input
portd = portd | 1<<int1 ; //enable pull-up resistor on INT1 pin
gicr = 0b11000000; //enable INT0 and INT1
// Set INT0 and INT1 to detect falling edge
MCUCR = 0b00001010; // mcucr = 0x0A
//Enable Global Interrupt
sei() ;

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Example C/C++ codes that initialised
External Interrupt INT0 and INT1 only
/*The codes to Initialise Stack by default will be generated by the C/C++
compiler.
The following statements will only set DDRD2, PD2, INT0 and ISC01,
and Clear ISC00. Other bits in respective registers are untouched so
setting of other interrupts are not changed.
DDRD=DDRD|(~(1<<PD2)); // PortD2 as input
PORTD=PORTD|(~(1<<PD2)); // Pull-up PortD2
GICR=GICR|1<<INT0 ; // enable INT0
MCUCR = MCUCR|1<<ISC01; // INT0 input falling edge
MCUCR = MCUCR&((1<<ISC00)^0xff);
/*The following statements will only set DDRD3, PD3, INT1, ISC01
and ISC00. Other bits in respective registers are untouched so
setting of other interrupts are not changed.*/
DDRD=DDRD|((1<<PD3)^0xff); //Using Ex-or to NOT (1<<PD3)
PORTD=PORTD|((1<<PD3)^0xff);
GICR=GICR|1<<INT1;
MCUCR = MCUCR|1<<ISC11|1<<ISC10;

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Timer Interrupt Programming
 Programming Timer Interrupt
o There are at two timer interrupts:
o Overflow / Rollover timer flag
o Compare match timer flag
o Basically, in ATmega32 there are three timers: Timer0, Timer1, Timer2.
o Timer0 and Timer2 are 8-bit, while Timer1 is 16-bit. (will cover more
details on how to program timers on the next module)
 Programming Timer Interrupt: Rollover Timer Flag
o If the timer interrupt in the interrupt register is enabled, the timer over
flow flag (TOVx) is raised whenever the timer rolls over and the micro-p
jumps to the interrupt vector to service the ISR.
o To enable the interrupt for a given timer, we must set the TOIEx bit that
held by TIMSK register.

o To enable (unmask) the Timer interrupt let says Timer0, we should write
as follows:

TIMSK = 1 << TOV0 ; // enable Timer 0 overflow interrupt

Sei() ; // enable interrupt globally
 Programming Timer Interrupt: Rollover Timer Flag
o Example: Write a program to (a) enable (unmask) the Timer0 overflow
interrupt, (b) disable (mask) the Timer0 overflow interrupt, and © show
how to disable (mask) all the interrupts with a single instruction.

a) TIMSK = (1<<TOIE0) ; //set TOE0=1

SEI() ;//allow interrupt to come in

b) TMASK = TIMSK ; // Read TIMSK

TIMSK=(1<<TOIE0) ;//clear TOIE0=0 ->mask (disable) Timer0
//interrupt
c) CLI () ;//mask all interrupt globally
 Programming Timer Interrupt: Compare Match Timer Flag
o Sometimes a task should be done periodically.
o The program can be written using the CTC mode and compare match
(OCF) flag.
o To do so, load the OCR register with the proper value and initialize the
number to the CTC mode.
o When the content of TNCT matches with OCR, the OCF flag is set. Which
cause the compare interrupt to occur. (See next module for detail)
 Programming Timer Interrupt: Compare Match Timer Flag
o Example: Using Timer0, write a program that toggles pin PORTB.5 every
40μs, while at the same time transferring data from PORTC to PORTD.
Assume XTAL = 1MHz.
 Interrupt Priority
& Interrupt inside Interrupt
 Interrupt Priority
o What will happen when two interrupts are activated at same time?
Which one will responds first?
o Answer: Interrupt Priority!

o If two interrupts are activated at the same time, the interrupt with the
higher priority is served first.
o The priority of interrupt is related to the address of that interrupt in the
interrupt vector.
o Example: Address of INT0 = $2 and INT2 = $6. thus INT0 has higher
priority.
 Interrupt inside Interrupt
o What happen if AVR is executing an ISR
belonging to an interrupt and another interrupt
is activated?
o Answer:
When AVR begins to execute an ISR, it disables
the I bit in SREG causing all the interrupts to be
disabled, thus no other interrupt occurs while
serving the interrupt.
When AVR enables I bit in SREG, causing the
other interrupts to be served.
 Context Saving in Task Switching
o In multitasking system, the CPU serve one task at a time and then moves
to the next one. For example:
(1) Copying the contents of PORTC to PORTD
(2) Toggling PORTC.2 every 5μs
o To write a program of multitasking system, we should manage resource
carefully so that its not conflict with each other.
 Context Saving in Task Switching
o Example: thy system
performs (1) increasing
contents of PORTC
continuously and (2)
increasing content of
PORTD once every 5μs.

o DOES THE PROGRAM

WORKS?
o Not working: they have
resource conflict and
they interfere with each
other!!!
 Context Saving in Task Switching
o How to overcome such situation?
1) Using different registers for different tasks.

2) Context saving – we can save the contents of registers on the stack

before execution of each task, and reload the registers at the end of
the task.
 Saving Flag of SREG Register
o The flags of SREG are important especially when there are conditional
jumps in our program.
o Thus, we should save the SREG register if the flags are changed in a
task, especially those who involves with ISR.
Interrupt Programming In C
: Refers AVR ebook for details.
(Section 10.5, pg:385)
 Atmel Studio C/C++ Interrupt Service Routine
Keywords for the ATmega32/ATmega32A
Vector Address Source ATmel Studio C/C++ Interrupt Definition
No. Name Event Keywords
1 $000 Reset No needed since it is External Pin, Power -
Changes from High
by default assigned on Reset, Brown -out
to Low at On Chip’s
by C/C++ compiler Reset, Watchdog
RESET Pin
referencing to main() Reset, and JTAG AVR
function Reset
2 $002 INT0 Status at On Chip’s INT0_vect External Interrupt
INT0 Pin as defined Request 0
by ISC01:ISC00 bits
of the MCUCR
register
3 $004 INT1 Status at On Chip’s INT1_vect External Interrupt
INT1 Pin as defined Request 1
by ISC11:ISC10 bits
of the MCUCR
register
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Atmel Studio C/C++ Interrupt Service Routine
Keywords for the ATmega32/ATmega32A
Vector Address Source ATmel Studio Interrupt
No. Name Event C/C++ Keywords Definition
4 $006 INT2 Status at on INT2_vect External
Chip’s INT1 Pin Interrupt
as defined by Request 2
ISC2 bit of the
MCUCSR register
5 $008 TIMER1 OCF1A bit of TIMER1_COMPA_ve Timer/Counter
COMPA TIFR register is ct 1 Compare
set Match A
6 $00A TIMER2 OVF OCF2 bit of TIFR TIMER2_OVF_vect Timer/Counter
register is set 2 Overflow
7 $00C TIMER1 CAPT TIMER1_CAPT_vect Timer/Counter
ICF1 bit of TIFR
1 Capture
register is set
Event
8 $00E TIMER2 COMP TIMER2_COMP_vect Timer/Counter
OCF2 bit of TIFR
2 Compare
register is set
Match
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Atmel Studio C/C++ Interrupt Service Routine
Keywords for the ATmega32/ATmega32A
Vector Address Source ATmel Studio C/C++ Interrupt
No. Name Event Keywords Definition
9 $010 TIMER1 OCF1B bit of TIMER1_COMPB_vect Timer/Counter
COMPB TIFR register 1 Compare
is set Match B
10 $012 TIMER1 OVF T0V1 bit of TIMER1_OVF_vect TIMER1 OVF
TIFR register Timer/Counter
is set 1 Overflow
11 $014 TIMER0 COMP OCF0 bit of TIMER0_COMP_vect Timer/Counter
TIFR register 0 Compare
is set Match
12 $016 TIMER0 OVF T0V0 bit of TIMER0_OVF_vect Timer/Counter
TIFR register 0 Overflow
is set
13 $018 SPI, STC SPIF bit of SPSR SPI_STC_vect Serial Transfer
Register is set Complete
14 $01A USART, RXC RXCIE of USART_RXC_vect USART Rx
UCSRB bit is Complete
set 47
Atmel Studio C/C++ Interrupt Service Routine
Keywords for the ATmega32/ATmega32A
Vector Address Source ATmel Studio Interrupt
No. Name Event C/C++ Keywords Definition
15 $01C USART, UDRIE bit of UCSRB USART_UDRE_vect USART Data
UDRE register is set Register Empty
16 $01E USART, TXC TXC bit of UCSRB USART_TXC_vect USART, Tx
register is set Complete
17 $020 ADC ADC_vect ADC
ACIE bit is ACSR
Conversion
register is set
Complete
18 $022 EE_ RDY EEWE bit EECR EE_RDY_vect EEPROM Ready
register is cleared
19 $024 ANA_COMP ACI bit is ACSR ANA_COMP_vect Analog
register is set Comparator
20 $026 TWI activated TWI_vect Two -wire
for as long as the
Serial Interface
TWINT Flag of TWCR
is high
21 $028 SPM_ RDY executed as long as SPM_RDY_vect Store Program
the SPMEN Memory Ready
bit in the SPMCR 48
Register is cleared.
 Interrupt Vector Table
• Location of information to tell CPU where to find the service routine of
the respective interrupt.
• When source of Interrupt is generated (after it has been enabled and
Global Interrupt Enabled bit is set), PC (program Counter) will be
initialised with value Vector Address defined under the “Program Address”
column of the interrupt generated.
– The event of interrupt is given under the “Interrupt Definition” column.
• If RESET occur, PC will be initialised with $0000 (though the number is
3 hex digit under “Program Address”, a 4 hex digit number will be
stored to PC because PC is a 16 bit register).
• If INT2 interrupt occurs, PC will be initialised with $0006.
• Except RESET that does not have a “current” instruction that it is
executing, when an interrupt occur, the CPU will complete the “current”
instruction that it is executing and save the address of PC (next
instruction to be executed) to the STACK before PC is initialised with
interrupt vector Address.

49
 C Language Example in Setting Up INT0, INT1
and INT2 ISR
//Interrupt Service Routine for trigger on Pin INT0
ISR(INT0_vect)
{
// Codes here;
}
//Interrupt Service Routine for trigger on Pin INT1
ISR(INT1_vect)
{
// Codes here;
}
//Interrupt Service Routine for trigger on Pin INT2
ISR(INT2_vect)
{
// Codes here;
}

• In C language programming, when the Interrupt Service Routine Keywords

is used as the name of the function, the RETI instruction will be inserted
by default by the Atmel Studio C/C++ (GCC) compiler.
50
 Interrupt Flags and Interrupt Enabled bits
The interrupt flag bit is set whenever the interrupt event occurs,
whether or not the interrupt is enabled.
The interrupt enabled bit is used to enable or disable a specific
interrupt. Basically is tells the microcontroller whether or not it should
respond to the interrupt if it is triggered.

51
 Global Interrupt Enabled Bit
• Tell CPU to service all interrupts are enabled
• Apart from the enabled bits for the specific interrupts the global interrupt
enabled bit MUST be enabled for interrupts to be activated in the
microcontroller.
• For the AVR 8-bits microcontroller this bit is located in the Status I/O
Register (SREG). The Global Interrupt Enabled is bit 7, the I bit, in the
SREG.

• In assembly language the SEI instruction set the I bit and the CLI
instruction clear the bit.
• In C/C++ language the sei() function set the I bit and the cli() function
clears the bit.
– The functions are declared in AVR/interrupt.h which must be included
in the C program.

52
 Interrupt Request sources provided
with the AVR microcontroller
• The AVR 8-bits microcontroller provides both internal and external
interrupt sources.
• The internal interrupts are associated with the microcontroller's
peripherals which are the Timer/Counter, Analog Comparator, etc.
• The external interrupts are triggered via external pins.
• When an Interrupt is triggered, the CPU will execute its service
routine whose starting address is defined in the Interrupt vector
table. On ATmega32/ATmega32A microcontroller there are four (4)
external interrupts:
• The RESET interrupt - Triggered from pin 9 (executed like an
interrupt but does not operate as an interrupt because RETI
instruction cannot be used in RESET “Interrupt service routine”.
– External Interrupt 0 (INT0) - Triggered from pin 16.
– External Interrupt 1 (INT1) - Triggered from pin 17.
– External Interrupt 2 (INT2) - Triggered from pin 3.

53
Location of External Interrupt pins in
ATmega32/ATmega32A

54
 Writing Assembly Codes Utilizing the
Interrupt Feature
• The Global Interrupt bit in the General Interrupt Control Register (GICR), the I bit,
in the microcontroller's status register (SREG) MUST also be enabled by using the
SEI instruction.
• The stack MUST be initialized (Normally at the beginning of the Main Program).
• When an interrupt is being service the microcontroller needs to store critical
information on the stack.
• The Triggering Condition (in MCUCR for INT0 and INT1 and in MCUSCR for INT2)
must be specifically set to suit hardware wiring configuration of the interrupt pin.
• Enable internal pull-up resistor if external pull-up resistor is not wired for active
low interrupt input.
• The Interrupt Service Routine (ISR) MUST end with the RETI instruction, which
indicates the end of the ISR. The microcontroller needs to know when it reaches
the end of the ISR so it can return to its previous task.
• RETI will also set I bit is so that Global interrupt is enabled because I bit is cleared
when CPU service any interrupt.

55
Writing C Codes Utilizing the Interrupt
Feature
 The Global Interrupt bit, the I bit, in the microcontroller's status
register (SREG) MUST also be enabled by using the sei() function.
• The stack NEED NOT be initialized (C compiler initialised stack by
default).
• NEED NOT store critical information on the stack when an interrupt
is being service the microcontroller needs to (C compiler does this
by default).
 The Triggering Condition (in MCUCR for INT0 and INT1 and in
MCUSCR for INT2) must be specifically set to suit hardware wiring
configuration of the interrupt pin.
 Switch ON internal pull-up resistor if external pull-up resistor is not
wired for active low interrupt input.
• NEED NOT end The Interrupt Service Routine (ISR) the RETI
instruction (C compiler does this by default).

56
 The ATMEga32/ATMEga32A External
Interrupts Pins
• The INT2, INT1 and INT3 can be programmed to generate
external interrupt for the ATmega32
• The interrupts can detect four different types of pin
changes:
1. pin goes low
2. any logical change in pin
3. falling edge (pin goes from high to low)
4. rising edge (pin goes from low to high)
• These interrupts are controlled by the following registers.
1. GICR
2. MCUCR (INT1 and INT2)
3. MCUCSR (INT2 only)

57
 GICR
• To enable INTn we need to set the INTn bit of the GICR register.

58
 MCUCR and MCUCSR
• To set detection (interrupt sense control) of pin changes we need to set
the MCUCR (for INT1 and INT0) or MCUCSR (for INT1)

ICS2 Description
0 A falling edge on INT2 activates the interrupt
1 A rising edge on INT2 activates the interrupt 59
General Interrupt Flag Register (GIFR)

– INTF1: When ‘1’ on this bit trigger INT1 Interrupt when INT1 bit of GICR and I bit of SREG
is one.
– INTF0: When ‘1’ on this bit trigger INT0 Interrupt when INT0 bit of GICR and I bit of
SREG is one.
– INTF2: When ‘1’ on this bit trigger INT2 Interrupt when INT2 bit of GICR and I bit of
SREG is one.

60
Example C/C++ codes that initialised
External Interrupt INT0 and INT1 only
/*The codes to Initialise Stack by default will be generated by the C/C++
compiler.
The following statements will only set DDRD2, PD2, INT0 and ISC01,
and Clear ISC00. Other bits in respective registers are untouched so
setting of other interrupts are not changed.
DDRD=DDRD|(~(1<<PD2));
PORTD=PORTD|(~(1<<PD2));
GICR=GICR|1<<INT0;
MCUCR = MCUCR|1<<ISC01;
MCUCR = MCUCR&((1<<ISC00)^0xff);
/*The following statements will only set DDRD3, PD3, INT1, ISC01
and ISC00. Other bits in respective registers are untouched so
setting of other interrupts are not changed.*/
DDRD=DDRD|((1<<PD3)^0xff); //Using Ex-or to NOT (1<<PD3)
PORTD=PORTD|((1<<PD3)^0xff);
GICR=GICR|1<<INT1;
MCUCR = MCUCR|1<<ISC11|1<<ISC10;
61
 C Interrupt: Example of Interrupt
Request at INT0 to toggle display @ PORT B
#include <avr/io.h> int main(void)
#include <avr/interrupt.h> {
ISR(INT0_vect) initInterrupt();
{
DDRB=0xff; // Port B as output
PORTB =~PORTB; toggle
} PORTB=0x55; // data @ PortB
void initInterrupt(void) while(1)
{ {
DDRD=0b01000000;//pin PD2 /*If interrupt INT0 is triggered,
//(INTO) output here PORTB will be complemented
(toggle) in background when INT0
GICR=0x40; // enable INT0 is serviced*/
MCUCR=0x03; // falling edge trig
}
sei();
}
}

ISMAIL FKE UTM 2018

ISMAIL FKE UTM 2017 62
 SUMMARY
• Learn interrupts in AVR
• Learn interrupt requirement
• Understand the sequence of events that occur when
an IRQ occurs
• Learn to develop interrupt service routines (ISRs) to
handle interrupts
• Understand interrupt application sample