PCB Layout for SMPS

High Voltage Controllers (HVC)

Colin Gillmor, Michael O’Loughlin
Agenda

• Introduction
• The Schematic
• Parasitic Components
• SMPS Characteristics
• PCB Layout – General
• PCB Layout – Effect on EMI
• PCB Layout – An Example
• PCB Layout – Review
• PCB Layout – Things you don’t have to worry about
• PCB Layout – Summary

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Introduction

PCB Layout for SMPS

Introduction:

I would suggest that

• The PCB is usually the
single most complex custom
component in the design

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Introduction:
What issues must be considered when laying out a PCB for
a Switched Mode Power Supply (SMPS) ?
• A high proportion of the PCB layouts I see have critical
defects
• The best controller in the world cannot work well if How to translate a
embedded in a poor layout schematic into working
• PCB layout for SMPS is difficult hardware
• The same general principles govern low and high power
layouts –
• The difficulty is how to apply the principles in practice

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The Schematic

PCB Layout for SMPS

The Schematic:
Typical schematic of a CCM boost converter

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The Schematic:
Typical schematic of a CCM boost converter – Shows about 1/3 of the components !
Does NOT include component or PCB parasitics !

Component parasitics.
• ESR in capacitors
• Coss in MOSFETs
• Leakage inductances
Layout parasitics
• Track resistance
• Stray capacitances
• Stray inductances
Key to a successful layout is understanding the circuit, including the parasitic components
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Parasitic Components

PCB Layout for SMPS

Parasitics: Know their Effects

You get parasitic components for free,

but you have to pay a performance penalty for them.
Ideal components DO NOT EXIST
• Capacitors have ESR, ESL, C varies with Temp and V
• Inductors have inter-winding C
• Leakage inductance in transformers
• Stray capacitances around MOSFETs
• Even Resistors have parasitic L and C
• PCB tracks have R, L and C

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• This is NOT an exhaustive list

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Parasitics: Capacitance

Building a capacitor is easy – two conductors separated by an insulator.

No simple formula for the general case – (non standard geometries)
𝐴
For a flat plate capacitor 𝐶 = ε 0ε 𝑟
𝑑

Permittivity of free space ε 0 = 8.85 𝑥10−12 𝐹 𝑚−1

Relative permittivity ε 𝑟 ≈ 4.4 (Fiberglass)

Stray capacitance should be minimized

V(t)

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Parasitics: Inductance

Building an inductor is even easier – inductance is a measure of the energy contained in the
magnetic field set up by an electric current – all you need is a conductor with a current in it.

Simple formulae exist for specific geometries – toroids, E cores etc.

In general no simple formula for stray inductance. ‘Shorter is better’ 1nH per mm – rule of
thumb.
Wider tracks = lower parasitic L
i(t)

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Parasitics: Resistance

All conductors exhibit resistance – (except

superconductors).
• Simple formulae exist for specific geometries
𝑙
• Sheet Resistivity: 𝑅𝑠ℎ𝑒𝑒𝑡 = ρ
𝐴
RCS is comparable to RSHEET
• ≈ 500μΩ per square for 1oz (34μm) cu 4*500μΩ = 2mΩ
Must provide
This is important where currents are high quality return path in presence of
large currents
Current sensing resistors – 20 mΩ typical • Use Kelvin (4 wire) connections
Copper has a large temperature co-efficient of resistance
𝑇𝐶𝑅𝑐𝑢 ≈ 4000 𝑝𝑝𝑚 °𝐶 −1 (+40% for 100°C rise)

Blog: Why should I count squares

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SMPS – Characteristics

PCB Layout for SMPS

Understand the operation of the circuit:

Identify the loops with high di/dt

• Especially the paths where the current is switched on and off
• Stray inductance here will cause voltage spikes
Identify the nodes with high dv/dt, (switched nodes)
• Stray capacitance will couple noise currents into other nodes
Identify the lines with high DC (or low frequency AC) currents.
• Resistance causes voltage drops and control errors
Identify the signal connections
• These are susceptible to having noise coupled onto them (Victims)
• Noise can cause control upsets – jitter, instability etc.

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PCB Layout: Switched Loops (High di/dt)
High di/dt
Low di/dt
Inductor current is switched alternately
between MOSFET and Diode paths
• Pulsating currents in Diode and I_Ind I_MOS I_Dio
MOSFET paths – o/p Loop
(Red/Blue)
• Inductance in the high di/dt paths will
cause voltage spikes
i/p loop inductance less critical
• di/dt rates much lower

i/p loop o/p loop

Cin provides local low impedance
source
Simplified schematic of a CCM boost converter 16
PCB Layout: Switched Nodes (High dv/dt)
High dv/dt at switched node (Blue)
Minimise total conductor area at this node. Short
Switched between 0V and VOUT
narrow tracks. Inductor, MOSFET and Diode terminals
• High dv/dt rates imply node as close together as possible.
capacitance MUST be minimised Low C much more important than low R.
• Currents proportional to the stray I_Ind V_sw
capacitance between switched node 𝑑𝑣
and other circuit nodes 𝑖 = 𝑐 𝑑𝑡
• Implies unwanted noise pickup
MOSFET Heatsink adds
capacitance
Floating heatsink => high EMI
Ground the heatsink !
• Other nodes are at DC or AC ground
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PCB Layout: Reverse Recovery Effects (High di/dt)
MOSFET Turns ON Use rectifiers with low QRR –
Diode Reverse Recovery Charge flows in SiC for high Vout.
yellow Loop Schottky Diodes
Ultra fast diodes
Stray inductance in this loop => Large Sync rectifiers with low QRR
di/dt when diode stops conducting
Minimise Loop Inductance
Result is large voltage spikes

Seen in all non ZCS topologies

Boost
Buck (incl Sync Buck)

Reinforces the need to understand the switching paths in the topology you are using
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PCB Layout: Switched Nodes: Gate Drives

High dv/dt at switched node (blue)

Hi di/dt in gate drive loop (yellow)
• High peak currents
I_gate V_gate
• Minimise loop inductance

Study your schematic

• Know the paths with high di/dt –
minimise INDUCTANCE
• Know the nodes with high dv/dt –
minimise CAPACITANCE

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PCB Layout: Switched Nodes: Snubbers

Snubbers absorb unclamped

inductive energy
• High di/dt rates with high
instantaneous currents
• High dv/dt rates
• High Temperatures due to power
dissipation

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PCB Layout: Phase Shifted Full Bridge

• Minimise inductance in loops

(Red, Green)
• Minimise size of switched nodes – I_QA I_QC
red dots

I_QB I_QD

I_Pri

I_Lout I_QE I_QF

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PCB Layout: Flyback

Low power but often used in off line High dv/dt

applications where Vin is high I_Dio

Input and Output currents are

pulsating

Gate drive currents as before

High dv/dt rates at the MOSFET I_MOS

drain – red dot (& Vcs)

I_gate 22
PCB Layout - General

PCB Layout for SMPS

PCB Layout: Layer assignment
How many layers ?
• Single Layer: Lowest cost – consumer goods,
TV, domestic appliances etc.
• Two Layer: One signal and one power, ground
planes are possible
• Four Layer: Medium complexity digital/mixed
signal boards. Two signal and two ground
layers. > 4 layers: Luxury !
• Spacing between layers is potentially important
• What process is to be used to build the product
– reflow + wave or wave only etc.
• Many constraints on component placement,
spacing, orientation etc. etc.
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Ground Planes:

Ground Plane – an infinite, equipotential surface Currents flow in the lowest impedance path –
black is outward current on a top side track,
red is the return current in the ground plane
When is a ground plane not a ground plane ?
• When it has a slot in it – current has to flow around
the slot – increased loop area, increased
Inductance and impedance
• When the currents flowing cause significant voltage
drops (Significant depends on context)
Use under ICs to provide E field screening and clean
GND reference

Yellow is a better top side routing around a slot

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Ground Planes:

Don’t put slots in the ground plane

• Or if you do be careful
Ground planes are not possible on a single sided
board
• Take extra care to minimise the impedance in the
ground connections in a Single Sided Board 
• Low impedance from AGND to PGND is desirable
• Place as much grounded copper under the IC as
possible
• Remember that DC tracks are an AC Ground

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PCB Layout: Noise Pickup
Cstray couples to long track Cstray couples to long track
RF, CF ineffective Noise signal is filtered
Stray Capacitance couples noise onto Large, noise signal at IC Lower noise signal at IC
sensitive nodes –
• V and I sensing inputs, FB pins, Slope
Comp, Ramp, Timing Cap etc.
Example – CS signal
• Place RF and CF AT the IC pins
• Good ground connection from CF
Ground connections are ALWAYS
important and often neglected
• Minimise the unfiltered track length Bad Good
• Maximise the separation
– Move the source, Reduce Cstray
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PCB Layout: Noise Pickup
Cstray couples to long track Cstray couples to long track
R3, CF ineffective Repositioned R3, CF effective
Stray Capacitance couples noise onto Some noise signal at IC Lower noise signal at IC
sensitive nodes –
• V and I sensing inputs, FB pins, Slope
Comp, Ramp, Timing Cap etc.
3 x 3MΩ 2 x 3MΩ
Example – CS signal
• Place RF and CF AT the IC pins
• Good ground connection from CF
Move R3
Ground connections are ALWAYS
important and often neglected
• Minimise the unfiltered track length Bad Good
• Maximise the separation
– Move the source, Reduce Cstray
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Parasitics: Trading off L & C
• Capacitance is proportional to the area of the plates
supporting the electric field
• Inductance is proportional to the area of the loop
enclosed by the current

• There is an INHERENT trade-off

Low capacitance tracks will have high inductance

• Long, thin tracks with large signal to ground separation

Low inductance paths will have high capacitance

• Short, wide tracks with minimum area enclosed
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PCB Layout: Tracking

Take a ‘Walk’ around the pins 30

PCB Layout: Tracking
VREF pin. Keep VREF PCB tracks as far away as
possible from sources of switching noise and
decouple it to GND with a good quality ceramic
capacitor.

EA+ and EA- pins. High impedance pins,

susceptible to noise pickup. Keep tracks as short as
possible.

COMP pin. Keep tracks as short as possible

SS/EN pin. Keep tracks as short as possible, avoid

running it close to any source of high dv/dt and add
a simple RC filter at the pin.

The components connected to these pins set

operating parameters. Keep them close to the IC
and provide low impedance return paths to GND
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PCB Layout: Tracking
GND pin. Use a Ground Plane to minimize the
impedance of the connection here.

VDD pin. Decouple to GND. Keep the capacitor as

close to the VDD and GND pins as possible.

These pins are the gate drive and SYNC output

pins and will have a high dv/dt. Keep the tracks
from these pins as far away from noise sensitive
input pins as possible.

CS pin. This connection is arguably the most

important single connection in the entire PSU
system. Avoid running the CS signal traces near to
sources of high dv/dt. Put a RC filter at (not close
to) the pin

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PCB Layout: Tracking

Vias used to connect the blue

and red ground planes

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PCB Layout: Regulatory requirements
• Safety Agencies will control:
– The PCB material used
– Creepage distances – shortest path between two parts along the SURFACE
• Grooves don’t count if less than a certain width
– Clearance distances – shortest path between two parts through air
• PCB slots can be used to increase creepage – but not always clearance
– The use of Basic, Reinforced and Supplementary Insulation
• The Standard is the ultimate reference
• Usually UL60950 / EN60950 / EN 62368-1 or similar, depends on the application

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PCB Layout – Effect on EMI

PCB Layout for SMPS

Transformer:
The transformer is the second most complex custom component in the design
– after the PCB
Magnetics design has a BIG influence on EMI and performance – Efficiency etc.
Leakage inductance
Some tips for transformers
Wire size and type
Safety Isolation • Cancellation windings
• Study skin and proximity losses
Physical construction of windings • Internal Screens from pri to sec
Core Gapping • Grounded ‘Belly Bands’
• Quiet ends of windings at outside
Internal Screens between primary and secondary
• Swap pins to make layout easier
More information at
http://www.ti.com/ww/en/power-
training/login.shtml?DCMP=psdslibrary&HQS=tlead-power-
psdslibrary-apec2015-pwrhouse-20150312-lp-en 36
Transformer Design:
‘Belly’ band to reduce
Transformer is much, much more than external E and H field
simply its turns ratio and magnetizing
inductance

Get a DETAILED construction

diagram from the manufacturer
Or
Disassemble a sample and STUDY
its construction !

Additional information at https://www.ti.com/seclit/ml/slup338/slup338.pdf 37

Conducted EMI: Common Mode and Differential Mode

CM sources Common mode noise:

• Transformer (mainly) • Three wire system (at least), Out L1, L2 return via GND
• Transformer is main source of CM currents
DM sources
• Switched currents, high di/dt Good Layout can SIGNIFICANTLY
• Reduce the generated signal
• Switched nodes, high dv/dt
• Improve the Filter performance

Strategy –
• Minimise the source
– Cheap, but requires thought
• Maximise the filtering
– Expensive, requires lots of work
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Conducted EMI: Common Mode and Differential Mode
Avoid creating parasitic capacitances across the inductors
– Separate the input and output tracks
– Avoid unwanted mutual inductances – eg between LCM and LDM or LPFC
Avoid creating parasitic inductances in series with the capacitors
– Keep leads short
Try to lay the filter out ‘in a straight line’ Route tracks directly
to pins of Ls & Cs
• CX , CY must have safety approvals
• CF is a filter capacitor
• LCM is a common mode choke
– ( BALUN)
• LDM is a differential mode choke
• CIN is the PFC input cap
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Conducted EMI: Common Mode and Differential Mode

Conducted EMI Radiated EMI

LISN provides standard line impedance Bi-Conic antenna feeds receiver.
L1 and L2 are measured, AVG and QP* 30MHz to 1GHz
150kHz to 30 MHz Vert and Horiz
SMPS in all orientations

3m in Anechoic Chamber
Or
10m Open Air Test Site
*Avg and QP limits are specified.
Mfrs often test AVG and PK
because it is much faster and
if pass PK then pass QP is assured 40
PCB Layout – An Example

PCB Layout for SMPS

 PCB Layout – An
PCB Layout: Givens Example
PCB size (Too small, but no point in complaining !)
PCB type – layers, layer spacing, material DC out
Position and type of Inlet and Outlet connections
Manufacturing Process – constraints
Standards to be met – IEC60950 / IEC62638-1 etc.
Know which parts are ‘important’ – write down the list

AC in
Know which loops and nodes are ‘important’
Know the creepage and clearance requirements
Know the heatsinking and other mechanical constraints
Imagine a general ‘Flow’ and begin to place the large
components - Trunk Packing Algorithm
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PCB Layout: Component Placement

Place the large parts in the power circuit first

• Trunk Packing Algorithm

Where should the controller go ?

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PCB Layout: Component Placement
Place the large parts in the power circuit first
Reserve a ‘quiet’ location for the controller
• NOT under transformer or node with high
SR Controller
dv/dt
• Place its associated parts nearby

Reserve an area for the input filter

• Keep filter input away from output
Use ‘rats nest’ to simplify connections
• Rotate, Reposition, Reassign pins,
Repeat
This is a typical small Flyback layout PWM Controller
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PCB Layout: Tracking

Typical small flyback – 2 layers

Gnd Plane in White
SR Drive GND in GRN
Minimise area of current loops SR Controller IC in Blue

Minimise area of switched nodes

Ground planes under ICs Output Loop
CS signal and return paths, short
and low noise

Gnd Plane in White

Controller GND in GRN
Controller in Blue PWM Controller
Input Loop
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PCB Layout – A Review

PCB Layout for SMPS

PCB Layout: Review – PMP8740, 2kW PSFB, UCC28950
Use of Ground planes reduces loop impedance Yellow and Green loops
are as small as possible
Controller

QF QF

QA QB Input
Capacitor
(green
outline)
located as
QC QD close to
bridge as QE QE
possible

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PCB Layout: Review – PMP8740, 2kW PSFB, UCC28950

Two layer PCB

Ground plane under controller and associated components

Ground plane Ground plane

under controller under controller

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PCB Layout: Review – PMP8740, 2kW PSFB, UCC28950
AC Ground trace
Ground plane under controller under IC (VCC)
Two layer PCB
• Bottom Layer

Current Transformer signal,

Away from noisy lines

CS Filtering at CS pin

Programming
parts* tied into
Gate drives kept away ground plane,
from input signals VCC Decoupling short connections
*used to set up Fsw etc. AT IC to IC Pins
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PCB Layout – Things you don’t have to worry about

PCB Layout for SMPS

Transmission Lines and Controlled Impedance

Transmission line:
• Length of line is more than about 10% of the
wavelength of the highest frequency of interest.

Assume a gate driver with a rise time of 10ns, the

highest frequency component is about 30MHz with
a wavelength of 10m. Transmission line effects
won’t be important unless the path is more than
about 1m.

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PCB Layout: Other considerations

Transmission Line effects

Controlled Impedance
Delay matching
Propagation delay
Speed of Light (30 cm per ns)

None of these are especially important

in SMPS layouts but it’s worthwhile
knowing that they exist.

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PCB Layout – Summary

PCB Layout for SMPS

PCB Layout

FINISHED ?

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PCB Layout

FINISHED ? NO – a PCB layout is NEVER finished !

Take at least a half a day to review and rework the layout

Reviews ALWAYS improve the board

Use an INDEPENDENT reviewer –

one who can criticise, complain, compliment and help correct the layout.
If you take only one idea from this talk – take this one.

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PCB Layout

FINISHED ? NO – a PCB layout is NEVER finished !

Take at least a half a day to review and rework the layout

Reviews ALWAYS improve the board

Use an INDEPENDENT reviewer –

one who can criticise, complain, compliment and help correct the layout.
If you take only one idea from this talk – take this one.

(You can always get your revenge return the compliment at a later date !)
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Conclusions & Key Take-Aways

• The Schematic shows only some of the components

– You need to know where the others are

• A full understanding of circuit operation is necessary

• Knowledge of parasitic elements in components AND in PCB tracks is key

• PCB Layout must take account of parasitic Inductance, Capacitance, Resistance

• EMI results are significantly affected by:

– Transformer design, power circuit and input filter layout

• REVIEW, RELAYOUT, REPEAT – Before you build the board

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References:

• PMP8740 design review at: https://www.ti.com/seclit/ml/slup349/slup349.pdf

• Ground Planes: http://www.ti.com/lit/an/slyt499/slyt499.pdf and

http://www.ti.com/lit/an/slyt512/slyt512.pdf

• PCB Design Guidelines for Reduced EMI: http://www.ti.com/lit/an/szza009/szza009.pdf

• The PCB is a component of op amp design: http://www.ti.com/lit/an/slyt166/slyt166.pdf

• Blog: http://e2e.ti.com/blogs_/b/powerhouse/archive/2016/10/03/why-should-i-count-
squares

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Thank You

Colin Gillmor, Michael O’Loughlin

TI Information – Selective Disclosure