COMPUTER ARCHITECTURE

ASSIGNMENT: 80x86 FAMILY

The term x86 refers to a family of instruction set architectures based on the Intel

8086 CPU. The 8086 was launched in 1978 as a fully 16-bit extension of Intel's 8-bit
based 8080 microprocessor and also introduced segmentation to overcome the 16-bit
addressing barrier of such designs. The term x86 derived from the fact that early
successors to the 8086 also had names ending in "86". Many additions and extensions
have been added to the x86 instruction set over the years, almost consistently with
full backward compatibility.[3] The architecture has been implemented in processors
from Intel, Cyrix, AMD, VIA, and many others.

The term is not synonymous with IBM PC compatibility as this implies a multitude

of other hardware; embedded systems as well as computers used x86
chips before the PC-compatible market started,[4] some of them before the IBM
PC itself.

As the term became common after the introduction of the 80386, it usually implies

binary compatibility with the 32-bit instruction set of the 80386. This may
sometimes be emphasized as x86-32 to distinguish it either from the original 16-
bit "x86-16" or from the 64-bit x86-64. Although most x86 processors used in new
personal computers and servers have 64-bit capabilities, to avoid compatibility
problems with older computers or systems, the term x86-64 (orx64) is often used
to denote 64-bit software, with the term x86 implying only 32-bit.

INTEL 80186
Features and performance
The 80186 and 80188 series was generally intended for embedded systems,
as microcontrollers with external memory. Therefore, to reduce the number of chips
required, it included features such as clock generator, interrupt controller, timers, wait
state generator, DMA channels, and external chip select lines.
The initial clock rate of the 80186 and 80188 was 6 MHz, but due to more hardware
available for the microcode to use, especially for address calculation, many individual
instructions ran faster than on an 8086 at the same clock frequency. For instance, the
common register immediate addressing mode was significantly faster than on the 8086,
especially when a memory location was both (one of the) operand(s) and the
destination. Multiply and divide also showed great improvement being several times as
fast as on the original 8086 and multi-bit shifts were done almost four times as fast than
in the 8086.

A few new instructions were introduced with the 80186 (referred to as the 8086-2
instruction set in some datasheets): enter/leave (replacing several instructions when
handling stack frames), pusha/popa (push/pop all general registers), bound (check
array index against bounds), ins/outs (input/output of string). A useful immediate mode
was added for the push, imul, and multi-bit shift instructions. These instructions were
included in the 80286 and successor chips.

The (redesigned) CMOS version, 80C186, introduced DRAM refresh, a power-save

mode, and a direct interface to the 8087 or 80287 floating point numeric coprocessor

In personal computers

The 80186 would have been a natural successor to the 8086 in personal computers.
However, because its integrated hardware was incompatible with the hardware used in
the original IBM PC, the 80286 was used as the successor instead in the IBM PC/AT.

Few personal computers used the 80186, with some notable exceptions: the

Australian Dulmont Magnum laptop, one of the first laptops; theWang Office Assistant,
marketed as a PC-like stand-alone word processor; the Mindset; the Siemens PC-D
(not 100% IBM PC-compatible but using MS-DOS 2.11 de:Siemens PC-D);
the Compis (a Swedish school computer); the RM Nimbus (a British school computer);
the Unisys ICON (a Canadian school computer); ORB Computer by ABS; the HP 200lx;
the Tandy 2000 desktop (a somewhat PC-compatible workstation with sharp graphics
for its day); the Philips :YES. Acorn created a plug-in for the BBC Master range of
computers containing a 80186-10 with 512 KB of RAM, the Master 512 system. In May
2006 Intel announced that production of the 186 would cease at the end of September
2007. Pin- and instruction-compatible replacements might still be manufactured by
various 3rd party sources.
PROCESSORS SUPPORTED:

80186EA/XL 3V and 5V to 20 MHz,

80186EB 5V to 16 MHz,
80188EA/XL 3V and 5V to 20 MHz,
80188EB 5V to 16 MHz

Memory

Program, data and stack memories occupy the same memory space. The total
addressable memory size is 1MB KB. As the most of the processor instructions use 16-
bit pointers the processor can effectively address only 64 KB of memory. To access
memory outside of 64 KB the CPU uses special segment registers to specify where the
code, stack and data 64 KB segments are positioned within 1 MB of memory (see the
"Registers" section below).
16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
32-bit addresses are stored in "segment offset" format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
Physical memory address pointed by segment offset pair is calculated as:
address = (<segment> * 16) + <offset>
Program memory - program can be located anywhere in memory. Jump and call
instructions can be used for short jumps within currently selected 64 KB code segment,
as well as for far jumps anywhere within 1 MB of memory. All conditional jump
instructions can be used to jump within approximately +127 - -127 bytes from current
instruction.
Data memory - the processor can access data in any one out of 4 available segments,
which limits the size of accessible memory to 256 KB (if all four segments point to
different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments
can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some
registers and instructions by default may use the ES or SS segments instead of DS
segment).
Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading word
data from even byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd
memory addresses, but it is not recommended for performance reasons (see "Data
Memory" above).
Reserved locations:

 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit
pointer in format segment:offset.
 FFFF0h - FFFFFh - after RESET the processor always starts program execution
at the FFFF0h address.

Interrupts
The processor has the following interrupts:
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using
STI/CLI instructions or using more complicated method of updating the FLAGS register
with the help of the POPF instruction. When an interrupt occurs, the processor stores
FLAGS register into stack, disables further interrupts, fetches from the bus one byte
representing interrupt type, and jumps to interrupt processing routine address of which
is stored in location 4 * <interrupt type>. Interrupt processing routine should return with
the IRET instruction.
Integrated 80186 peripherals generate the following hardware interrupts (higher priority
interrupts are listed first):

 Timer 0 - type 8
 Timer 1 - type 18
 Timer 2 - type 19
 DMA 0 - type 10
 DMA 1 - type 11
 INT0 - type 12
 INT1 - type 13
 INT2 - type 14
 INT3 - type 15.

Interrupt types 9, 16 (on 80186), 17, and 20 - 31 are reserved.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority then the maskable interrupt.
Software interrupts are non-maskable interrupts. They can be caused by:

 INT instruction - breakpoint interrupt. This is a type 3 interrupt.

 INT <interrupt number> instruction - any one interrupt from available 256
interrupts.
 INTO instruction - interrupt on overflow. This is a type 4 interrupt.
  Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt.
When the CPU processes this interrupt it clears TF flag before calling the
interrupt processing routine.
 Processor exceptions: divide error (type 0), array bounds exception (type 5),
unused opcode (type 6), escape opcode (type 7), and numeric co-processor
exception (type 16, 80C186 only).

Software interrupt processing is the same as for the hardware interrupts. Software
interrupts have the same priority as the NMI interrupt.

I/O ports
65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.
Reserved ports:

 00F8h - 00FFh
 FF00h - FFFFh: 256-byte control block. This is a default block location after
RESET. If necessary, the block can be remapped to different place in I/O or
memory space. For description of the control block please see "Control registers"
in the "Registers" section below.

Registers

Most of the registers contain data/instruction offsets within 64 KB memory segment.

There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the
processor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers is located in the stack segment. SS
register can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually
with program data. By default, the processor assumes that the DI register references
the ES segment in string manipulation instructions. ES register can be changed directly
using POP and LES instructions.
It is possible to change default segments used by general and index registers by
prefixing instructions with a CS, SS, DS or ES prefix.
All general registers of the 80186 microprocessor can be used for arithmetic and logic
operations. The general registers are:
Accumulator register consists of 2 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte
of the word, and AH contains the high-order byte. Accumulator can be used for I/O
operations and string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the
word, and BH contains the high-order byte. BX register usually contains a data pointer
used for based, based indexed or register indirect addressing.
Count register consists of 2 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. When combined, CL register contains the
low-order byte of the word, and CH contains the high-order byte. Count register can be
used as a counter in string manipulation and shift/rotate instructions.
Data register consists of 2 8-bit registers DL and DH, which can be combined together
and used as a 16-bit register DX. When combined, DL register contains the low-order
byte of the word, and DH contains the high-order byte. Data register can be used as a
port number in I/O operations. In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number.
The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is
usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data address in string manipulation
instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string
manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags is a 16-bit register containing 9 1-bit flags:
  Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
 Direction Flag (DF) - if set then string manipulation instructions will auto-
decrement index registers. If cleared then the index registers will be auto-
incremented.
 Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
 Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.
 Sign Flag (SF) - set if the most significant bit of the result is set.
 Zero Flag (ZF) - set if the result is zero.
 Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the
AL register.
 Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even.
 Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
during last result calculation.

Control registers are used to control 80186 integrated peripherals. These 16-bit

registers are part of 256-byte control block that can be mapped into system RAM or I/O
space. The control block includes the following registers:

 Interrupt control - 20h - 3Eh

 Time 0 control - 50h (counter), 52h (max count A), 54h (max count B), and 56h
(control word)
 Time 1 control - 58h (counter), 5Ah (max count A), 5Ch (max count B), and 5Eh
(control word)
 Time 2 control - 60h (counter), 62h (max count A), and 66h (control word)
 Chip-select control - A0h (upper memory), A2h (lower memory), A4h (peripheral),
A6h and A8h (mid-range memory)
 DMA descriptors channel 0 - C0h and C2h (source pointer), C4h and C6h
(destination pointer), C8h (transfer count) and CAh (control word).
 DMA descriptors channel 1 - D0h and D2h (source pointer), D4h and D6h
(destination pointer), D8h (transfer count) and DAh (control word).
 Refresh Control Unit registers (80C186 in Enhanced mode only) - E0h - E4h
 Power-Saving control (80C186 only) - F0h
 Relocation register - FEh

After reset the control block is mapped at address FF00h in I/O space.

Instruction Set

80186 instruction set consists of the following instructions:

  Data moving instructions.
 Arithmetic - add, subtract, increment, decrement, convert byte/word and
compare.
 Logic - AND, OR, exclusive OR, shift/rotate and test.
 String manipulation - load, store, move, compare and scan for byte/word.
 Control transfer - conditional, unconditional, call subroutine and return from
subroutine.
 Input/Output instructions.
 Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes

Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is located.
Register indirect - instruction specifies a register containing an address, where data is
located. This addressing mode works with SI, DI, BX and BP registers.
Based - 8-bit or 16-bit instruction operand is added to the contents of a base register
(BX or BP), the resulting value is a pointer to location where data resides.
Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index
register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed - the contents of a base register (BX or BP) is added to the contents of
an index register (SI or DI), the resulting value is a pointer to location where data
resides.
Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the
contents of a base register (BX or BP) and index register (SI or DI), the resulting value
is a pointer to location where data resides.
INTEL 80826
 The 80286 microprocessor is an advanced version of the 8086 microprocessor
that is designed for multiuser and multitasking environments.

 The 80286 addresses 16 M Byte of physical memory and 1G Bytes of virtual

memory by using its memory-management system.

 The 80286 is basically an 8086 that is optimized to execute instructions in fewer

clocking periods than the 8086.

 Like the 80186, the 80286 doesn’t incorporate internal peripherals; instead it
contains a memory management unit (MMU)
 The 80286 operates in both the real and protected modes In the real mode, the
80286 addresses a 1MByte memory address space and is virtually identical to
8086.

 In the protected mode, the 80286 addresses a 16MByte memory space.

 The clock is provided by the 82284 clock generator, and the system control
signals are provided by the 82288 system bus controller
 The 80286 contains the same instructions except for a handful of additional
instructions that control the memory-management nit.
INTEL 80836
 The 80386 microprocessor is an enhanced version of the 80286 microprocessor
and includes a memory-management unit is enhanced to provide memory paging

 The 80386 also includes 32-bit extended registers and a 32-bit address and data
bus.

 The 80386 has a physical memory size of 4GBytes that can be addressed as a
virtual memory with up to 64 T Bytes. .

 The 80386 is operated in the pipelined mode, it sends the address of the next
instruction or memory data to the memory system prior to completing the
execution of the current instruction

 This allows the memory system to begin fetching the next instruction or data
before the current is completed

 This increases access time, thus reducing the speed of the memory

 The I/O structure of the 80386 is almost identical to the 80286, except that I/O
can be inhibited when the 80386 is operated in the protected mode through the
I/O bit protection map.

 The register set of the 80386 contains extended versions of the registers
introduced on the 80286 microprocessor. These extended registers include EAX,
EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and EFLAGS

 The instruction set of the 80386 is enhanced to include instructions that address
the 32-bit extended register set

 Interrupts, in the 80386 microprocessor, have been expanded to include

additional predefined interrupts in the interrupt vector table

 The 80386 memory manager is similar to the 80286, except the physical
addresses generated by the MMU are 32 bits wide instead of 24-bits

 The 80386 is also capable of paging. The 80386 is operated in the real mode
(i.e. 8086 mode) when it is reset.

 The real mode allows the microprocessor to address data in the first 1MByte of
memory.

 In the protected mode, 80386 addresses any location in its 4G bytes of physical
address space
INTEL 80486
 The 80486 microprocessor is an improved version of the 80386 microprocessor
that contains an 8K-byte cache and an 80387 arithmetic coprocessor; it executes
many instructions in one clocking period.

 The 80486 microprocessor executes a few new instructions that control the
internal cache memory

 A new feature found in the 80486 in the BIST (built in self-test) that tests the
microprocessor, coprocessor, and cache at reset time

 If the 80486 passes the test, EAX contains a zero.

 Additional test registers are added to the 80486 to allow the cache memory to be
tested.
  These new test registers are TR3 (cache data), TR4(cache status), and TR5
(cache control).

Pentium Processor basic features

 The Pentium microprocessor is almost identical to the earlier 80386 and 80486
microprocessors.

 The main difference is that the Pentium has been modified internally to contain a
dual cache (instruction and data) and a dual integer unit

 The Pentium also operates at a higher clock speed of 66 MHz

 The data bus on the Pentium is 64 – bits wide and contains eight byte-wide
memory banks selected with bank enable signals
 Memory access time, without wait states, is only about 18 ns in the 66 MHz
Pentium.

 The superscalar structure of the Pentium contains three independent processing

units a floating point processor and two integer processing units

 A new mode of operation called the System Memory Management (SMM) mode
has been added to the Pentium. It is intended for high-level system functions
such as power management and security.

 The Built-in Self-test (BIST) allows the Pentium to be tested when power is first
applied to the system.

 Allows 4MByte memory pages instead of the 4Kbyte pages Pentium Pro
Processor basic features.

 The Pentium Pro is an enhanced version of the Pentium microprocessor that

contains not only the level 1 caches found inside the Pentium, but the level 2
cache of 256 K or 512K found on most main boards.

 The Pentium Pro operates using the same 66 MHz bus speed as the Pentium
and the 80486.

 It uses an internal clock generator to multiply the bus speed by various factors to
obtain higher internal execution speeds

 The only significant software difference between the Pentium Pro and earlier
microprocessors is the addition of FCMOV and CMOV instructions.

 The only hardware difference between the Pentium Pro and earlier
microprocessors is the addition of 2M paging and four extra address lines that
allow access to a memory address space of 64G Bytes.