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Encore Computer  32/6705, 32/6750, 32/6780

MULTISel

CONCEPT
32/6705, 32/6750, 32/6780  Computer Product Line
Features

High-performance.
Distributed Processing. 
systems Closely Coupled via Reflective memory

Processing
Range of 1.7 to 27 MWhets
Designed
with VLSI Technology
Hardware
and Software Compatible with CONCEPT-32 Systems

   
General  
MULTISel offers a system-level solution for tightly-coupled, 
distributed processing by providing up to four CPU/IPU 
computational elements (nodes) in a single, com-pact 
cabinet. Up to nine nodes can function as a single multi-
processing system with one node designated as the system 
host.

MULTISel enables the user to apply the right amount of 

processing power to individual application areas by as-
signing them to independent, but closely coupled, MULTISel 
nodes. Gould’s unique Reflective Memory system links these 
nodes TO provide each with a common address range for data 
needed by all nodes in the system.
This distributed design enables the user to:
•
Virtually eliminate contention among nodes for improved 
    application response time
• Provide optimal power to each functional area of an
   application
• Independently develop each node’s function
• Incrementally enhance the performance of each node
• Easily expand a system with the addition of new nodes for new
application functions
Description
MULTISel configurations with
various hosts allow hardware and software support for up to nine
nodes
forming a single system.
High-density packaging and
internal cabling enable two connected MIJLTISe1 cabinets with up
to
eight nodes to provide up to 24 MWhets of distributed power in a space
only three feet,
eight inches wide. The controlling host node can be a
CONCEPT 32/97, 32/87. Se1PAC ‘ or
another MULTISel, depending on
application requirements. With a CONCEPT 32/97 or 32/87.
The
system-level processing range increases to 34 MWhets.
The MULTISel Host/Node
Peripheral Cabinet differs from the standard node cabinet in that it is
designed to accommodate peripheral devices in the upper half Each node
supports standard
CONCEPT/32 hardware and software and runs its own copy
of the MPX-32 Operating System,
which is downloaded from the host node,
Nodes are available in eight- and 16-SelBUS slot
versions
MULTISel
nodes contain:
• Vertically
cooled, eight- or 16- lot Se1BUS chassis with power supply 
          (16-slot nodes
include two power supplies)
• Power sequencing module
• CMOS CPU
• Floating-point Coprocessor
• Multi-Function Processor (MFP)
• 2MB or 8MB Dual-Port Integrated Memory Module (DPIMM)
• Reflective Memory port

Each of these components is

implemented on a single circuit
board. MULTISel nodes also can contain
an Internal Processing
Unit (IPU) a secondary computational processor
— with its own
Floating-point Coprocessor.
CMOS
CPU
The single-board CMOS CPU
uses the latest in advanced gate
array technology to perform at levels
equivalent to the
CONCEPT 32/67 CPU while maintaining complete hardware
compatibility.
Floating-point Coprocessor
Surface mourn chips and
FAST-logic technology enable Gould to produce a single-board,
floating-point accelerator that can be used as a coprocessor with the
CMOS CPU and IPU.
The Floating-point Coprocessor performs floating-point
arithmetic operations and fixed-point
multiplication in a fraction of
the time required by firmware and software implementations. Both
32-bit
single precision and 64-bit double precision operands are supported.

Multi-Function Processor
Several SelBUS and Multipurpose
Bus boards are consolidated on the Multi-Function
Processor (MFP) board.
This board encompasses the following functions:
 • Console port Seven asynchronous ports
• Line printer port
• Real-time clock and interval timer
• 12 external interrupts
• Two Small Computer Systems Interface (SCSI) buses — one dedicated
to a fixed disk 
     drive the other for a magnetic tape drive and
future devices
The MFP supports these functions without an expansion chassis. As an
option, a second
device interface card supports two 5 1/4inch floppy
disk drives and is capable of generating an
MP Bus
Memory
Dual-Port Integrated Memory Modules (DPIMMs) provide
2MB or 8MB of memory, DPIMMs
feature two-way, on-board interleaving,
which alleviates memory busy problems and improves
memory access times
in various applications. The second port of the DPIMM supports
Reflective Memory DPIMMs can provide 16MB of memory and use only two
Slots
Reflective Memory
With Reflective Memory, Nodes retain their own private memory while
taking advantage of a
common, logically linked reflective memory
partition This partition contains data required by all
nodes in the
system, in effect providing each with its own copy of the data base. Any
node
writing to this partition causes that write to be immediately
transferred to other nodes reflective
memory partitions. Thus, each node
has free access to its own constantly- updated copy of the
application
data base
Reflective Memory relies on the following components
• DPIMMs
• Reflective Memory Port: Read Sense Controller (RSC) and Write Sense
Controller
(WSC)          
device interface card sets — Reflective Memory Bus (RMB)
The RSC monitors the RMB and the WSC monitors the SelBUS for
addresses soft-
programmed to specify the reflective portion of memory
The RSC and WSC contain buffers for
queuing requests to or from the RMB.
which eliminates additional processing time The RMB is
a high-speed bus
that transfers data at the SelBUS rate of 26.67MB/second

Reflective Memory System

Software is an optional. MPX-32-based package consisting of six
application tasks which
provide the necessary tools to configure,
download control, and monitor up to eight nodes from
a single host
Model Numbers
6744A - MULTISel COMPUTER SYSTEMS — Real-time,
distributed processing systems with
one eight-slot or 16-slot node.

6744B - MULTISel COMPUTER

SYSTEMS — Real-time distributed processing systems with
four
eight-slot or two
16-slot nodes
6744C - MULTISel
EXPANSION NODE — Includes 2MB or 8MB DPIMM

6744E - MULTISel HOST/NODE

PERIPHERAL CABINET — Includes 2MB or 8MB DPIMM,
eight- or 16-slot chassis, and
power strip for  the
peripheral equipment.

8921 MULTISel EXPANSION CHASSIS —

Includes eight-slot chassis, fan assembly, power
sequencer, and
universal power supply.
 Product
Specifications
   
Physical
   
Dimensions  
55 in. (1397 cm)
 
Height
22 in. (559 cm)  
Width  
38 in. (965 cm)
 
Depth
   
Weight
650 lbs. (294 8 kg) International
Minimum (single
1,250 lbs (567.0 kg) 240 VAC +/-
node)
10%
Domestic 50 Amps
Maximum (four
nodes) 208 VAC +/- 10%
50Hz
50Amps
Electrical not
2
supplied!
Voltage 60Hz
Current not supplied/none specified none
Phases (hardwired-
none (hardwired-use
AWG #8
Frequency use
85C wire mm)
AC Plug AWG#885C
  wire mm,)
AC Receptacle  

 
1000 Watts 1,000 Watts
4,000 Watts 4,000 Watts
Power Dissipation
 
Minimum (single
node) 50F to 104F (100C to 400C)
Maximum (four -8F to 117F (-22C to 47C)
nodes) -40F to 144F (-40C to 62C)

Environmental  

Temperature 20% to 80%

(ambient air)
10% to 90/o
Operating
Storage  
Transport
Humidity (non- 5,115 BTUs
condensing)
20,450 BTU5
Operating
62 DBA (approx)
Storage/transport
 
Heat Dissipation  

Minimum (single 32 bits

node)
1.8, 16, 32, 64bits
Maximum (tour
16MB
nodes)
16MB
Noise
8
Performance
8
Processor (per
node) 214 instructions
Word Length Standard firmware and
hardware unit
Data Sizes
Memory protect, power fail
Logical Address
sfae, memory ECC, arithmetic
Space
exception.
Physical Address
privilege violation, non-present
Space
memory
General Purpose
112 maximum
Registers
60/120 Hz or 501100 Hz (line
Base Registers
frequency dependent)
Instruction
32-bit, 600 ns resolution, 300
Repertoire
ns resolution
Floating-point
with optional RTOM
Arithmetic
 
Integrity Features
Two 1MB or 4MB DRAM SIP
 
banks, four-way sliced
Interrupts
32 data bits plus 7 ECC bits
Priority levels
150 ns effective
Real-time clock
16MB
 
Standard two-way, on-board:
Interval timer optional two- or

Memory four-way external

Standard
Technology 16KB instruction cache
Word Size
16KB operand cache
Cycle Time
Two-way set associative
Capacity
Least Recently Used (LRU)
Interleaving
 

Overlapping
26.67MB/second
Cache
150 ns, 300ns
Size
 

Organization

Replacement
algorithm

Reflective Memory

Throughput

Transfer cycle
period

(selectable)
General Information: CompanyEmail

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  Last modified: June 23, 2014

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