Design and Optimization of EMI

Filter for Interleaved PFC

Converters with Phase-Shedding
Control

Mohamad Yamen Ahmed Munzer Saad

Department of Energy Technology, PED4-1040, 2019-05-31

Master Project

T REPORT
EN
D
U
ST
Copyright © Aalborg University 2019
 Department of Energy technology
Aalborg University
Pontoppidanstræde 111, 9220 Aalborg
http://www.et.aau.dk

Title: Abstract:
Design and Optimization of EMI Filter for
Interleaved PFC Converters with Phase- The research shows a continuous growth
Shedding Control of the DC power supplies demand world-
wide, those power supplies must comply
Theme: with standards for low and high frequency
Master’s thesis noise emissions. PFC boost converter with
EMI filter is used for that purpose. Re-
Project Period: cently, the demand on using PFC con-
Spring semester 2019 verters into many applications has been
increased, the power capability demand
Project Group: has also increased. Operating the single-
PED4-1040 switch PFC at higher power can impair its
efficiency, thereby interleaving techniques
Participant(s): have been employed to improve the effi-
Mohamad Yamen Ahmad Munzer Saad ciency and reduce the volume, in this re-
port an investigation for designing both
Supervisor(s): high efficiency and power density PFC
Associate Prof. Pooya Davari converter will be conducted
Industry supervisor Prof. Eckart Hoene

Copies: 1

Page Numbers: 69

Date of Completion:
July 11, 2019

The content of this report is freely available, but publication (with reference) may only be pursued due to
agreement with the author.
Contents

Preface vii

Summary ix

1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Need for power factor correction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.1 Power factor definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.2 Full bridge rectifier harmonics . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Harmonic Emission Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 State of the art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Problem formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Main objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.8 Project outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Power factor correction (PFC) Converter operation 7

2.1 PFC boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Current operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 CCM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 DCM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3 BCM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4 QCM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Control of Boost PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Boost inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 CCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.2 DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.3 QCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Interleaved Boost PFC 23

3.1 Interleaved configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Input current ripple reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 Cancellation factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

v
vi Contents

3.2.2 Amplitude factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.3 Constant energy storage . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.4 Simulation validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4 EMI filter design 29

4.1 EMI measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.1 LISN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.2 EMI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 DM filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.1 Calculate the required attenuation . . . . . . . . . . . . . . . . . . . . . 32
4.2.2 Filter Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3 EMI filter optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.1 Filter corner frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.2 Filter component size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 Analytical estimation of DM noise . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5 Experimental test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5 Energy efficiency 51
5.1 Components selection and losses . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1.1 Rectifier bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1.2 Boost Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1.3 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1.4 Boost Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.1.5 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.1.6 Total losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6 Phase-shedding control 57
6.1 EMI filter design in phase-shedding . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1.1 Two Units interleaved . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7 Conclusion and future work 61

Bibliography 63

A PLECS Model schematic 67

A.1 Full diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
A.2 LISN circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Preface

This project about Design and Optimization of EMI Filter for Interleaved PFC Converters
with Phase- Shedding Control are written as a Master’s thesis for the master program in
Power electronics and drives at the Department of Energy technology, Aalborg University.
The project report is written in LATEX and all simulations are conducted in Matlab and
PLECS.
The references are made according to the IEEE standard and they can be found at the
Bibliography.

I would like thank my Associate Professor Pooya Davari for giving me the chance to
make a research in EMI filter which is very interesting topic and for his extensive support
during this semester. I would like also thanks Professor Eckart Hoene for his advises.
Finally, I would like to thank my wife for supporting me and understand my stress this
period.

Aalborg University, July 11, 2019

Mohamad Yamen Saad

<[email protected]>

vii
Summary

The main objective of this project is analyze different influencing factors on PFC converters
in order to develop optimized EMI filter design methodology based on interleaving and
phase-shadding technology
This project will test the the PFC converter operation in different current operating
modes and will determining the boost inductor size different current operating modes by
using an analytical calculations then will validate it in the simulation.
It will explain the EMI filter design for the differential-mode (DM) noise. An investi-
gation about finding the optimal filter corner frequencies in operating different scenarios
will conducted.
The relation between the required attenuation and the switching frequency has the
same pattern in CCM, QCM and DCM, the difference only in the amplitude where in
CCM it is lower than it in QCM and DCM because it has a bigger boost inductor.
This project will show that interleaving with conventional phase shift is not efficient at
all the switching frequency ranges.
It will show the benefits of the using non-standard phase-shift in interleaving which
will improve the filter corner at some switching frequency ranges.
An investigation about EMI filter design in Band A (9-150kHz) and finding a generic
formula to find the phase shift angles which give the optimal corner frequency are the
most important contribution in this project.
The Components selection and losses calculation will be used in order to get the effi-
ciency curves which will be used to understand the concept of phase-shedding.
It will show the benefits of Phase-shedding control in boost PFC, and will design EMI
filter in phase-shedding by using Two Units interleaved as study case.

ix
Chapter 1

Introduction

1.1 Background
In today’s modern world, electronic devices become part of human life, those devices need
to be supplied by power supplies.
The research shows a continuous growth of power supplies demand worldwide, ac-
cording to MarketsandMarkets™ research about the power supplies market, "The overall
power supply market is expected to grow from USD 25.20 billion in 2018 to USD 34.92
billion by 2023, at a CAGR1 of 6.7% from 2018 to 2023 where the AC-to-DC power supply
is the fastest-growing type of due to its wide usage in lighting, industrial, and consumer
electronics applications"[1][2].
Those AC-to-DC power supplies or any grid-connected power system must comply
with both the low- and high-frequency harmonics standards [3].
The low-frequency harmonics in the traditional AC-to-DC conversion occurs due to
the diode rectifier followed by a large capacitor acts as a nonlinear load to the power line
which is resulting in a low power factor. Therefore, a power factor correction (PFC) circuit
must be used to ensure sinusoidally shaped input currents.[4]
While the high-frequency conducted emissions (harmonics) will appear because of
the high-frequency switched current in the PFC circuit, thus electromagnetic interference
(EMI) filters should be used to limit those emissions from being injected into the utility
(means) and comply with standards .[5] [3]

1.2 Need for power factor correction

1.2.1 Power factor definition
Power factor is defined as the ratio between the real power, P, and the apparent power, S:

P Vs · Is · cos(φ1 )
PF = = 1 1 (1.1)
S Vs · Is ·
1 Compound Annual Growth Rate

1
2 Chapter 1. Introduction

Where P is equal to the product of the first order harmonics of the source voltage, Vs1 , the
first order harmonics of current, Is1 and cos(φ1 ). While S is equal to the product of the rms
voltage, Vs and the rms current, Is .
By assuming that Vs has no high order harmonics, Vs = Vs1 . And in the linear loads,
Is = Is1 , then the displacement Power Factor can be defined as following:

DPF = cos(φ1 ) (1.2)

But in nonlinear loads, the drawn currents is not a pure sinusoidal and it has high
distortion then the ratio Is1 /Is will be the distortion power factor[6]:

Is1 1 1
= q = p (1.3)
Is ∞ 2 1 + ( THD )2
∑i Isi

Finally the total power Factor can be written as following:

1
PF = p · DPF (1.4)
1 + ( THD )2

1
PF = p · cos(φ) (1.5)
1 + ( THD )2

1.2.2 Full bridge rectifier harmonics

The classical approach for rectification is using bridge diode followed by large capacitor
filter to maintain a stable voltage as shown in Figure 1.1a.
Input voltage

100 v_in

-100
Input current

i_in
2
0
-2

0.18 0.20 0.22 0.24 0.26 0.28 0.30

(b) Input voltage and current waveforms in the

(a) The full bridge rectifier circuit full bridge rectifier

Figure 1.1: The full bridge rectifier circuit and the input voltage and current waveforms

The line current will flow from the source to the load only when the input voltage, vin
is higher than the voltage across the capacitor. Therefore, the line current waveform will
be non-sinusoidal unlike the sinusoidal input voltage waveform as shown in Figure 1.1b.
Figure 1.2 shows the harmonics contact of this non-sinusoidal current waveform where
the high order harmonics have high values. Thus PFC circuit must be use to reduce those
harmonics and comply with the harmonics standards such as IEC 61000-3-2 [7].
1.3. Harmonic Emission Standard 3

0.5
i_in

0.4

0.3

0.2

0.1

0.0
0 200 400 600 800 1000
Frequency

Figure 1.2: Low frequency harmonics

1.3 Harmonic Emission Standard

The International Electrotechnical Commission (IEC) is an international standards orga-
nization which is responsible for publishes International Standards for all electrical, elec-
tronic and related technologies including the power electronics system emission Standard
where any power electronics device must comply with these standards [8].
The emission standard in power electronics system covers the range from 50 Hz up to
2/3 GHz, and it is split into two main frequency ranges the harmonic range and the EMI
range as shown in Figure 1.3 [9]:

The harmonic range starts from the grid fundamental frequency 50/60 Hz up to the 40th
or 50th order of it which equals to around 2 kHz, the main concern of this range is the grid
power quality, it is for example covered by IEC 61000-3-2 and IEC 61000-3-12 [9] [10].

The EMI range starts from the end of the harmonic range up to 2/3 GHz or higher which
is [10] which divided into three main frequency ranges LF range, Conducted emission
range and Radiated emission range [9]:
• LF range (2 kHz to 9kHz) is currently not regulated.
• Conducted emission range (9 kHz to 30MHz) in this range the noise signal is not
high enough to radiate from the equipment, it is just travel along lines. The standers
in this range generally set the from 150 kHz to 30 MHz such as CISPR 11 and
CISPR 12. And recently, with the increase in use of the pulse-width modulated
(PWM) converters, some standards also start at 9 kHz to 150 kHz such as CISPR 14
(Induction hobs) and CISPR 15 (Lighting equipment) [9] [10].
• Radiated emission range (30 kHz to 2/3 GHz), the frequency here is sufficient to
radiate by using the device as an antenna
4 Chapter 1. Introduction

50 Hz 2 kHz 9 kHz 30 MHz 3 GHz

Harmonics LF range Conducted emission Radiated emission

Covered by: No Covered by: Covered by:

IEC 61000-3-2 Standards CISPR 14 CISPR 11
IEC 61000-3-12 CISPR 15 150 kHz CISPR 12

Switching frequency 
EMI

Figure 1.3: Harmonic Emission Standard [9]

1.4 State of the art

It is necessary PFC in full bridge rectifier comply with harmonics standards as explained
section 1.2.
The passive solution can be used In PFC circuit but it required huge inductors and
capacitors with huge volume. Thus, the active PFC were developed to reduce the volume
and increase the efficiency [11].
The boost PFC converter is is one of the most popular converter used in practice which
provides a smooth continuous input, in compare to buck or buck-boost topology where the
input current is discontinuous which may decrease the power factor and increase harmonic
distortion [12].
Recently, the demand on using PFC converters into many applications has been in-
creased, the power capability demand has also increased. Operating the single-switch PFC
at higher power can impair its efficiency, thereby interleaving techniques have been em-
ployed to improve the efficiency for high power application and to reduce the switching
frequency and the total volume of the circuit due to the input current ripple cancellation
effect in interleaving [13]

1.5 Problem formulation

Nowadays, improving the efficiency and power density of PFC converters with the EMI
filter which is can take up to 23% of the total converter size [14] has gained a lot of interest.
However, it is a challenge to achieve both high efficiency and power density in a system
at the same time [15], especially that there are many degrees of freedom for designing the
PFC such as the switching frequency, the topology (single or interleaved), the current
operating modes (CCM, DCM..) and the type of the controller.

1.6 Main objective

"Analyze different influencing factors on PFC converters in order to develop optimized EMI filter
design methodology"
1.7. Functional requirements 5

1.6.1 Objectives
• Finding the effect of different current operating modes on component sizing
• Finding the an optimal design and sizing for EMI filter in single and interleaved
topologies based on CISPR 15 for band A and CISPR 11 for band B
• Finding the effect of the phase-shedding on the converter efficiency and power den-
sity
• Practical implementation, measurement and loss comparison

1.7 Functional requirements

Input Voltage, Vin 85 - 265 VAC (RMS)

Line frequency, f 1 50 Hz
Output voltage, Vo 400 VDC
Output voltage ripple, ∆uo 10
Output power , Pout 100 - 1000 W

Table 1.1: Specifications of the power stage

1.8 Project outline

• Chapter 2: Explanation of the PFC converter operation in different current operating
modes, determining the boost inductor size different current operating modes by
using an analytical calculations then validate the design in the simulation.
• Chapter 3: Showing the interleaving technique benefits in boost PFC by reducing the
input current ripple and determining the boost inductor size in interleaved PFC by
using an analytical calculations then validate it in the simulation.
• Chapter 4: Explanation of the EMI filter design for the differential-mode (DM) noise,
An investigation about finding the optimal filter corner frequencies in operating
different scenarios, showing the benefits of the using non-standard phase-shift in
interleaving, finding a generic formula to find the phase shift angles which give
the optimal corner frequency, designing the filter with a minimal volume and using
analytical estimation of DM noise and compare it the simulation.
• Chapter 5: Boost PFC components selection and calculating the loss, Efficiency
curves of interleaved PFC converter in CCM up to 3 units
• Chapter 6: Showing the Phase-shedding control benefits in boost PFC, designing
EMI filter in phase-shedding by using Two Units interleaved as study case.
Chapter 2

Power factor correction (PFC) Con-

verter operation

2.1 PFC boost Converter

PFC boost Converter

vin EMI Filter Rectifier Boost PFC RL

Figure 2.1: The block diagram of PFC converter with the EMI filter (the PFC boost converter is
colored in orange)

The PFC boost converter circuit is shown in Figure 2.2a where a boost dc-dc converter is
located in between the bridge rectifier and the filtering capacitor which contains a switch
Q, a diode D and Boost inductor L.
The boost converter is controlled by switching the switch by switching frequency f sw
such that the average current of boost inductor forced to have full-wave-rectified waveform
i Lavg , hence the input current iin will have a sinusoidal waveform as shown in Figure 4.5,
where i Lavg = |iin | = Îin · |sin(ωt)| [6]. More details about controlling the Boost PFC will
be explained in section 2.3

2.2 Current operating modes

Depending on the inductor current, the boost PFC converter can operate in different
modes: continuous conduction mode (CCM), boundary conduction mode (BCM), dis-
continuous conduction mode (DCM) and Quasi-conduction mode (QCM) as shown in
Figure 2.3

7
8 Chapter 2. Power factor correction (PFC) Converter operation

+ +

(b) Boost inductor current,

- - input voltage and current
(a) PFC boost converter circuit waveforms

Figure 2.2: The PFC boost converter circuit with the corresponding voltage and current waveforms

(a) CCM (b) QCM

(c) BCM (d) DCM

Figure 2.3: Boost-inductor current waveform for different operating modes

2.2.1 CCM Operation

Figure 2.3a shows that CCM has the lowest current ripple in compare to the other modes.
Therefore, a relatively big boost inductor will be used in CCM which will also reduce HF
ripple leading to smaller EMI filter [3].
CCM has a relatively high switching loss because the switch always operates at hard
switching, and the diode has reverse recovery loss. While CCM has lower conduction
losses due to low RMS currents on the inductor and the switch and by using SiC Schot-
tky diodes which they have no reverse recovery behavior, the switching losses will be
reduced[16].

2.2.1.1 Boost inductor size in CCM

By assuming that the switching frequency f s is much high than the mains frequency f 1 , the
inductor average current i L,avg change over one switching cycle can be neglected as shown
2.2. Current operating modes 9

in Figure 2.4

Figure 2.4: Boost-inductor current and voltage waveform

The inductor current ripples depends on the voltage across it VL as the following equa-
tion:
1
Z
i L,ripple = v L dt (2.1)
L
In steady state, the current ripple average value over one switching period Ts is equal to
zero, then the peak-peak ripple current ∆IL can be calculated either when the inductor
charge or discharge as the following equation [6]:

1 1
∆IL = · Vin · ( DTs ) = · (Vo − Vin ) · (1 − D ) · Ts (2.2)
L L
Where D is the duty cycle which is in the boost converter is given by:

Vin
D = 1− (2.3)
Vo
By using Equation 2.2 and Equation 2.3 and solving for L, a formula for the inductor
size can be derived:

Vo · (1 − D ) · D
L= (2.4)
∆IL · f s
In boost PFC, D is not constant because the input voltage is AC.
The boost inductor in CCN LCCM will have its maximum value when D = 0.5 :
Vo
LCCM = (2.5)
4 · ∆IL,max · f s

Thus, L should be designed based on the maximum allowable current ripples ∆IL,max
which occur when D = 0.5 or when Vin = 12 · Vo according to Equation 2.3.
10 Chapter 2. Power factor correction (PFC) Converter operation

∆IL,max is set in relation to the average inductor current value when the maximum
current ripples occur IL,avg(D=0.5) by using the ripple factor kripple :

∆IL,max = kripple · IL,avg(D=0.5) (2.6)

kripple is in the range of 20% to 40% in CCM mode[12].
i L,avg is the inductor average current and it has full-wave-rectified waveform:

i Lavg = |iin | = Îin · |sin(ωt)| (2.7)

IL,avg(D=0.5) can be determined by finding the corresponding phase angle ωt when D =

0.5 .
The input voltage for the boost circuit is the rectified voltage vrec which is equal to half
of Vo when D = 0.5:
vrec = |vin | = V̂in · |sin(ωt)| = 0.5 · Vo (2.8)
By solving Equation 2.8 for |sin(ωt)| and substitute it in Equation 2.7, IL,avg(D=0.5) can be
determined:
Vo Po · Vo
IL,avg(D=0.5) = |iin | = Îin · 0.5 · = 2
(2.9)
V̂in V̂in
Finally ∆IL,Max in Equation 2.6 can be written in terms of kripple as in Equation 2.10:

Po · Vo
∆IL,max = kripple · ( 2
) (2.10)
V̂in

It is worth mentioning that Equation 2.10 is not accurate if (V̂in < 0.5 · Vo ) because D will
not be equal to 0.5 at any point.
When (V̂in < 0.5 · Vo ), the maximum current ripples occur at the peak of the average
inductor current which is equal to the the amplitude of the input current:

2 · Po
∆IL,max = kripple · Îin = kripple · (2.11)
V̂in

Po · Vo
∆IL,max =kripple · ( 2
) if V̂in > 0.5Vo (2.12a)
V̂in
2 · Po
∆IL,max =kripple · ( ) if V̂in < 0.5Vo (2.12b)
V̂in

2.2.2 DCM Operation

DCM has the highest ripple in comparison to other modes as shown in Figure 2.3d, thus
the boost inductor will be smaller, but on the other hand, bigger EMI filter is needed due
to high input ripple current[16].
Regarding the losses in DCM, the switching losses are lower because there is no reverse
recovery of the diode and zero-current turn-on for the switch [3].
2.2. Current operating modes 11

2.2.2.1 Boost inductor size in DCM

In DCM, the inductor current waveform i L at the peak of its average waveform ÎL,avg should
reach zero at the end of the turn-off switching interval as shown in Figure 2.5, at this point,
ÎL,avg will be half of the peak to peak current ripple ∆IL [3] [6]:

1
ÎL,avg = · ∆IL (2.13)
2
In the boost converter the input current is the same as the inductor current ÎL,avg = Îin :

1
Îin = · ∆IL (2.14)
2

Figure 2.5: Boost-inductor current and voltage waveform

As mentioned in subsection 2.2.1 that in steady state, the current ripple average value
over one switching period Ts is equal to zero, therefore the peak-peak ripple current ∆IL
can be calculated either when the inductor charge or discharge:

1
∆IL = · V̂ · ( DTs ) (2.15)
L in
The duty cycle relation in CCM is still valid because of the inductor current still con-
tinuous, it is just on the boundary [9].:

V̂in
D = 1− (2.16)
Vo
By substituting Equation 2.14 and Equation 2.16 in Equation 2.15 then isolating it for
L, a relation for inductor size in DCM can be derived which is considered as the maximum
value for L DCM . And in order to guarantee discontinuous operation, the inductor value
should be at at least equal or lower than it [3]:

V̂in
V̂in · (1 − Vout )
L DCM ≤ (2.17)
2 · f s · Îin

And when L DCM is lower than the this value the inductor current waveform became
discontinuous even in midpoint operation as shown Figure 2.6.
12 Chapter 2. Power factor correction (PFC) Converter operation

Figure 2.6: Boost-inductor current and voltage waveform

By assuming a no less in the system, the output power Po will be equal to the input
power Pin :

1
Po = Pin = · V̂ · Î (2.18)
2 in in
Equation 2.17 can be written in terms of Po by substituting Equation 2.18 in Equa-
tion 2.17:
2 · (1 − V̂in )
V̂in Vout
L DCM ≤ (2.19)
4 · f s · Po
And to ensure operating in DCM at any load , the design should be based on the load
should be in its maximum value Po,max [9]:

2 · (1 − V̂in
V̂in Vout )
L DCM ≤ (2.20)
4 · f s · Po,max

2.2.3 BCM Operation

BCM which is also called critical current mode (CRM) shown in Figure 2.3c, it has the
same DCM features in low switching losses because of switching at zero current.
The controller in BCM should be designed to keep the ripples in the inductor current on
the boundary where the start of the next switching cycle will be when the inductor current
cross zero[12]. Therefore, the switching frequency will not constant leading to difficulty
in the design of the boost inductor and EMI filter [17], thus BCM will be excluded in this
project.

2.2.4 QCM Operation

QCM is an operation mode in between CCM and DCM where the current waveform is
not fully continues or discontinues. Figure 2.3b shows the inductor current waveform in
QCM where the ripples at the midpoint of the average current are in CCM then they start
gradually crossing zero until they become fully in DCM away from the midpoint.
2.3. Control of Boost PFC 13

2.2.4.1 Boost inductor size in QCM

Equation 2.17 can be used to determine the inductor size in QCM by replacing V̂in by vin
as shown in Equation 2.21 :

V̂in
V̂in · (1 − Vout )
LQCM = (2.21a)
2 · f s · Îin
vin =V̂in · |sin(ωt)| (2.21b)

Equation 2.17 is originally used to determine the inductor size in DCM where it is
derived based on the current ripples should be hit zero at V̂in or when ωt = 90◦ by using
Equation 2.21b. But in QCM a different angle can be used to make the current ripples hit
the zero away from ωt = 90◦ .

2.3 Control of Boost PFC

The purpose of controlling the PFC converter is regulating the line current to be sinusoidal
and in phase with the line voltage, that done by there are different types of PFC controllers.

2.3.1 Current control

The current control has a high performance and it is used in CCM operation [9]. It is
consist of two control loops: inner current control loop and outer voltage control loop as
illustrated in Figure 2.8.

Current controller

LPF -
+ PI +

+
- PI

Voltage controller

Figure 2.7: Current control block diagram [9]

The voltage control loop is responsible for regulating the output voltage by comparing
the measured output voltage Vo with the desired output voltage Vo∗ then the output of
the proportional integrator (PI) controller will provide a suitable reference current for the
∗
current controller by determining the amplitude of the inductor current IˆL .
The current control loop regulates the inductor current i L to ensure that it has a full-
wave-rectified waveform by measuring it..
14 Chapter 2. Power factor correction (PFC) Converter operation

By comparing i L with a reference which is coming from measuring the rectified voltage
vrec to get its shape |sin(ωt)| after low pass filter LPF to get rid of the high frequency noises
∗
multiplied by the output of the voltage controller IˆL .
The output of the current controller is compared with a high switching frequency to
generate the switch gate pulses

2.3.2 Voltage control

This controller has only control loop which is the voltage control loop as shown in Fig-
ure 2.8 , therefore it is less stable and has lower performance in compare to the current
control[9].

Voltage controller

+
- PI

LPF -+ +

Figure 2.8: Voltage control block diagram [9]

It compares the measured output voltage Vo,meas with a set voltage value Vo ∗ , then the
output of the (PI) controller will be the duty cycle D. This duty cycle is almost fixed, it
is not affected by vrec full-wave-rectified waveform changes which the input of the boost
circuit, it is only changed if there is an error between Vo,meas and Vo ∗ . Therefore, "it does
not result in a high-quality sinusoidal input current [9]".
In order to solve this issue, the duty cycle should be variable d(t) as shown in the
following relation [9]: q
d(t) = D · (1 − M|sin(ωt)|) (2.22)

Where M = V̂in /Vout is the voltage ratio and |sin(ωt)| will be obtained by measuring the
rectified voltage vrec,meas in order to synchronize the duty cycle with vrec waveform.
Finally, d(t) will be compared with a high switching frequency to generate the switch
gate pulses.
2.4. Boost inductor design 15

2.4 Boost inductor design

The design will be based on the functional requirements which are given in Table 1.1 with
fixed switching frequency f s = 60 kHz in the different operation modes.
Then it will be validate in simulation by using PLECS, the simulation file in PLECS
contains the PFC circuit model with the controller, the schematic for it can be found in
Appendix A.

2.4.1 CCM
2.4.1.1 - kripple = 0.22 at the minimum load Po , min = 100 W and the maximum
input voltage Vin , max = 265 V :
In this design kripple will not exceed 0.22 at any load and input voltage, where the max-
imum allowable current ripples in this case is very small ∆IL,Max = 0.0626 A according
to Equation 2.10, thus a very big inductor is needed LCCM = 26.6 mH according to Equa-
tion 2.5 and this is not a realistic design.
Therefore, another approach will be used for designing the inductor in subsubsec-
tion 2.4.1.2 which is less restricted regarding the ripple factor.

2.4.1.2 - kripple = 0.22 at the full load Po , max = 1000 W and the maximum input
voltage Vin , max = 265 V :
The inductor size here will be LCCM = 2.66 mH which is calculated based on Equation 2.5
and Equation 2.10, kripple will be 0.22 only in this operation condition (the full load and the
maximum line voltage) and it will be changed by changing the operation conditions.
Figure 2.9 shows kripple values in different operation conditions, where kripple is a func-
tion of the output power Po in different input voltage based on Equation 2.23, the black
line is the boundary of kripple = 0.22, above this line kripple is higher than 0.22.

∆IL,max · V̂in
2
kripple ( Po ) = if V̂in > 0.5Vo (2.23a)
Po · Vo
∆IL,max · V̂in
kripple ( Po ) = if V̂in < 0.5Vo (2.23b)
2 · Po
16 Chapter 2. Power factor correction (PFC) Converter operation

Figure 2.9: kripple is a function of the output power Po when LCCM = 2.66 mH and f s = 60 kHz, the
black line is the boundary of kripple = 0.22

The design will be validated in PLECS by checking the ripples values in marked points
in Figure 2.9 and compare it with the calculation results, the comparison in Table 2.1.

• Point 1 (Po = 1000 W, Vin = 265 V):

The average inductor current value when the maximum current ripples occur IL,avg(D=0.5)
can be calculated by using Equation 2.9:

Po · Vo 1000 · 400
IL,avg(D=0.5) = 2
= √ = 2.84 A (2.24)
V̂in (265 2)2

And the maximum allowable current ripples will be according to Equation 2.7:

Po · Vo
∆IL,max = kripple · ( 2
) = 0.22 · 2.84 = 0.62 A (2.25)
V̂in

Figure 2.10 shows the simulation results for vrec , i L , i Lavg and v L waveforms at point
1, where Figure 2.10a shows the waveforms in the full cycle and Figure 2.10b shows
the same waveforms but zoomed in where the maximum ripples which occur (vrec =
1
2 Vo = 200 V).
2.4. Boost inductor design 17

400
vrec
200

0
502 504 506 508 510 512 514 516 518
5
iL
2.5 iL,avg
0
502 504 506 508 510 512 514 516 518
400
vL
0
-400
502 504 506 508 510 512 514 516 518
Time [ms]
(a) The waveforms in the full cycle

210
vrec
200

190
501.74 501.76 501.78 501.8 501.82 501.84 501.86
3.5
iL
3
iL,avg
2.5
501.74 501.76 501.78 501.8 501.82 501.84 501.86
200
vL
0

-200
501.74 501.76 501.78 501.8 501.82 501.84 501.86
Time [ms]
(b) Figure 2.10a zoomed around the red rectangle
where the maximum ripples which occur (vrec =
1
2 Vo = 200 V)

Figure 2.10: vrec , i L , i Lavg and v L waveforms in point 1 operation condition

It shows that the inductor is charging and discharging with D = 0.5 and the voltage
across the it v L changes from +200V to −200V every switching period.
• Point 2 (Po = 220.9 W, Vin = 110 V):
√
Since here 110 2 < 0.5Vo , the maximum current ripples occur at the peak of the
average inductor current Îin = ÎL,avg :
2 · Po 2 · 220.9
Îin = = √ = 2.84 A (2.26)
V̂in 110 2
Then the maximum allowable current ripples will be calculated by using Equa-
tion 2.27:
18 Chapter 2. Power factor correction (PFC) Converter operation

∆IL,max = kripple · Îin = 0.22 · 2.84 = 0.62 A (2.27)

Figure 2.11 shows the simulation results for vrec , i L , i Lavg and v L waveforms at point
2, where Figure 2.11a shows the waveforms in half cycle and Figure 2.11b shows the
same waveforms but zoomed in at the peak of the average inductor current ÎL,avg .

100 vrec

0
831 832 833 834 835 836 837 838 839

2.5 iL
iL,avg
0
831 832 833 834 835 836 837 838 839

0 vL
-200
-400
831 832 833 834 835 836 837 838 839
Time [ms]
(a) The waveforms in the half cycle

155.6
vrec
155.5
155.4

834.85 834.9 834.95 835 835.05

3 iL
iL,avg
2.5
834.85 834.9 834.95 835 835.05

vL
0

-200
834.85 834.9 834.95 835 835.05
Time [ms]
(b) Figure 2.11a zoomed around the red rectangle at
the peak of the average inductor current ÎL,avg

Figure 2.11: vrec , i L , i Lavg and v L waveforms at point 2 operation condition

Figure 2.11b shows the voltage across the inductor v L changes with duty cycle D =
0.61 .
2.4. Boost inductor design 19

Point 1 Point 2
Calculation Simulation Calculation Simulation
kripple 0.22 0.2 0.22 0.2
∆IL,Max 0.62 A 0.59 A 0.62 A 0.58 A
i Lavg 2.84 A 2.94 A 2.84 A 2.82 A

Table 2.1: Comparison between the calculation and the simulation results for the operation condi-
tions at the marked points in Figure 2.9

Table 2.1 shows that there is no significant variation between the simulation and calcu-
lation

2.4.2 DCM
In order to calculate the inductor size in DCM Equation 2.20 is used where it determines
the maximum value for L DCM .
According to the functional requirements in Table 1.1 the input voltage can vary from
minimum value Vin,min = 85 V up to maximum value Vin,max = 265 V
In order to ensure operating in DCM at any input voltage, Equation 2.28 is used which
is L DCM as a function of the input voltage Vin then it is plotted in Figure 2.12

2 · (1 − V̂in
V̂in Vo )
L DCM (V̂in ) = (2.28)
4 · f s · Po,max

100

90

80
L DCM [uH]

70

60

50
X 264.6
Y 37.62
40

30
80 100 120 140 160 180 200 220 240 260 280
vin (RMS) [V]

Figure 2.12: L DCM as a function of the input voltage Vin based on Equation 2.28 where Vo = 400 V,
Po,max = 1000 W and f s = 60 kHz

Equation 2.28 shows that Vin,max = 265 V requires a minimum inductor size L DCM =
37.62 uH. Therefore, L DCM ≤ 37.62 uH to ensure operating in DCM at any input voltage.
20 Chapter 2. Power factor correction (PFC) Converter operation

400
vrec

200

0
922 924 926 928 930

20
iL
iL,avg
10

0
922 924 926 928 930

(a) The waveforms in the half cycle

374.76
vrec
374.74

374.72

374.7
924.95 925 925.05

10 iL
iL,avg
5

0
924.95 925 925.05

(b) Figure 2.13a zoomed around the green rectangle at

the peak of the rectified voltage waveform v̂rec

330
vrec

325

320
923.24923.26923.28 923.3 923.32923.34923.36923.38 923.4

20
iL
iL,avg
10

0
923.24923.26923.28 923.3 923.32923.34923.36923.38 923.4

(c) Figure 2.13a zoomed the red rectangle away from

the peak of the rectified voltage voltage waveform v̂rec

Figure 2.13: i L , i Lavg and vrec waveforms when L DCM = 37.62 uH, Po,max = 1000 W, Vin,max = 265 V
and f s = 60 kHz
2.4. Boost inductor design 21

Figure 2.13 shows the simulation results for i L , i Lavg and vrec when L DCM = 37.62 uH,
Po,max = 1000 W, Vin,max = 265 V and f s = 60 kHz.
Figure 2.13a shows in the half cycle, where the i L envelope is not sinusoidal due to the
variable duty cycle in the voltage control which is used to control the PFC in DCM. i L is
on the boundary to be in DCM as shown in Figure 2.13b, while it becomes in DCM when
it is away from the midpoint as shown in Figure 2.13c.

2.4.3 QCM
The inductor size in QCM can be calculated by using Equation 2.21.
If the angle (where the current will be DCM) is selected to be ωt = 45◦ and when
Po,max = 1000 W, Vin = 230 V and f s = 60 kHz, the inductor will be equal to LQCM =
165 uH.
Figure 2.14 shows the simulated i L and i L,avg waveforms in half cycle, i L is CCM at the
midpoint and it becomes in DCM around ωt = 45◦ .

10
iL
iL,avg
8

6
[A]

0
0° 45 ° 90 ° 135 ° 180 °
[Degree]

Figure 2.14: i L and i L,avg waveforms when LQCM = 165 uH, Po,max = 1000 W, Vin = 230 V and
f s = 60 kHz
Chapter 3

Interleaved Boost PFC

3.1 Interleaved configuration

PFC boost Converter

vin EMI Filter Rectifier Boost PFC RL

Figure 3.1: The block diagram of PFC converter with the EMI filter

Interleaving technique is not new in power electronics, it has been employed in many
applications especially in high power rating applications where the components capability
is not enough to handle the high current stress, thus paralleling the components is the
solution by making the components sharing the current [18].
In boost PFC, it has been found that it is more beneficial to parallel PFC units instead
of the paralleling components [18] as shown in Figure 3.2, each unit consist of a switch, a
diode and inductor.
Interleaved configuration provides a lot of benefits such as having more efficient and
flexible system, and the ability to reduce the switching frequency and the total volume of
the circuit due to the input current ripple cancellation effect in interleaving [13]. Further-
more it can reduce the EMI filter volume as will be shown in chapter 4.

3.2 Input current ripple reduction

This section will show the affect of interleaving on the input current ripples.

23
24 Chapter 3. Interleaved Boost PFC

Figure 3.2: Parallel-Interleaving of Boost PFC circuit

3.2.1 Cancellation factor

For simplicity, just two units interleaved boost converter is considered in Figure 3.3, where
the switch in the second unit Q2 is delayed by half of a switching period from Q1 , since
that the inductor currents waveforms i L1 and i L2 are out of phase, the input current iin
ripple will be cancelled, this maximum ripple cancellation occurs when the duty cycle D
is equal to 0.5. [11].

ON

ON

Figure 3.3: Two units interleaved boost converter waveforms in CCM

But in PFC boost converter, D is not constant. Therefore, the ripple cancellation will
3.2. Input current ripple reduction 25

vary as a function of D.
KC ( D ) is defended as a cancellation factor, which is the ratio between the input current
ripple after interleaving ∆Iin(inter) and the inductor current ripple in one of the interleaved
units ∆IL1 [11]:
∆Iin(inter)
Kc ( D ) = (3.1)
∆IL1
This factor varies with the number of the units N, the phase shift angle between the
units, the shape of the current waveform and the current operating modes (CCM, DCM..)
[13].
Figure 3.4 shows D vs. Kc ( D ) plot up to 4 units in CCM, the phase shift between the
units is 360°/N. It shows that the cancellation will be minimum at D = 0 and D = 1 and
by increasing the number of units, the points where there is maximum cancellation will be
increased. For example in N = 2, the maximum ripple cancellation occurs at D = 0.5, but
in N = 3, it is at D = 0.333 and D = 0.667 [13].

1
n=2
n=3
0.8 n=4

0.6
Kc

0.4

0.2

0
0 0.1 0.3 0.5 0.7 0.9 1
D

Figure 3.4: Kc ( D ) plot for 2, 3 and 4 units interleaved in CCM

Figure 3.4 is plotted by using the following equation [19]:

N · (D − m m +1
N ) · ( N − D)
Kc ( D ) = (3.2)
D · (1 − D )
Where, N is the number of the interleaved units and m=floor(n.D).
In DCM and QCM, the interval when the inductor current is zero will add an extra
dimension, thus it is very complicated to derive an analytical expression for Kc ( D ) [13].

3.2.2 Amplitude factor

The amplitude of the inductor current ripple in one of the interleaved unit ∆IL1 varies as a
function of the duty cycle as shown in Equation 3.3 [13]:

Vo · (1 − D ) · D
∆IL1 ( D ) = (3.3)
L · fs
26 Chapter 3. Interleaved Boost PFC

∆IL1 can be normalized by dividing it by the maximum the inductor current ripple
in non-interleaved PFC ∆Iin(non,inter) in order to make it not be affected by Vo , L, and f s
changes as in Equation 3.4

∆IL1 ( D )
Ka ( D) = = 4 · (1 − D ) · D (3.4a)
∆Iin(non,inter)
Vo
∆Iin(non,inter) = (3.4b)
4 · L · fs

Where Ka ( D ) is defined as the amplitude factor which is the ratio between ∆IL1 and
∆Iin(non,inter) .

1
0.9 N=2
1 N=3
N=4
0.7
0.8

K c*Ka 0.5
0.6
Ka

0.4 0.25

0.1
0.2
0
0 0.1 0.3 0.5 0.7 0.9 1
0 D
0 0.1 0.3 0.5 0.7 0.9 1
D
(b) Kc ( D ) · Ka ( D ) plot for 2, 3 and 4 units
(a) Ka ( D ) plot interleaved

Figure 3.5

Figure 3.5a shows the plot for D vs. Ka ( D ) based on Equation 3.4. It shows that ∆IL1
will be minimum at D = 0 and D = 1 while it will be maximum at D = 0.5.
Finally, a relation between the ∆Iin(inter) and ∆Iin(non,inter) can be found by multiplying
Kc ( D ) and Ka ( D ):

∆Iin(inter)
Kc ( D ) · K a ( D ) = (3.5)
∆Iin(non,inter)
By plotting Equation 3.5 in Figure 3.5b, it can be observed that Kc ( D ) · Ka ( D ) ranges
only up to 1/N, which means that the maximum value of ∆Iin(inter) is reduced by 1/N, so
it can be written as:

1 1 Vo
∆Iin(inter,max) = · ∆Iin(non,inter) = · (3.6)
N N 4 · L · fs

3.2.3 Constant energy storage

In order to ensure a constant power rating after interleaving, the inductor in each unit
interleaved L1 should be equal to inductance in non-interleaved Lin(non,inter) multiplied by
N as shown in Equation 3.8
3.2. Input current ripple reduction 27

I
1 1 in(non,inter ) 2

2
· L(non,inter) · Iin ( non,inter ) = N · [ · L1 · ] (3.7)
2 2 N
Equation 3.8 can be reduced:
L1 = N · L(non,inter) (3.8)
which means that an extra 1/N can be added elation between the ∆Iin(inter) and ∆Iin(non,inter)
in Equation 3.6 leads to:

1 1 Vo
∆Iin(inter,max) = · ∆Iin(non,inter) = 2 · (3.9)
N2 N 4 · L · fs

1
0.9 N=2
N=3
N=4
0.7
K c*Ka*1/N

0.5

0.25

0.1
0
0 0.1 0.3 0.5 0.7 0.9 1
D

Figure 3.6: Kc ( D ) · Ka ( D ) · 1/N plot for 2, 3 and 4 units interleaved

3.2.4 Simulation validation

Figure 3.7 shows the simulation results for the input current up to 4 units interleaved with
constant energy storage. Where,LCCM = 0.665mH , Vin = 230 V f s = 60kHz.
Figure 3.7a shows the input current ripple in single unit (non-interleaved) where ∆Iin(non,inter) =
2.5 Aand by interleaving 2 units with (constant energy storage) , the current ripple is re-
duced by 4 then it will be ∆Iin(unit,max) = 0.625 A, Iin(unit,max) = 0.277 A in 3 units and
Iin(unit,max) = 0.1562 A in 4 units
28 Chapter 3. Interleaved Boost PFC

8 8
iL iL

6 iL,avg 6 iL,avg
[A]

[A]
4 4

2 2

0 0
470 472 474 476 478 480 472 474 476 478 480
Time [ms] Time [ms]

(a) 1 Unit (b) 2 Units

8
6
iL iL
iL,avg 5 iL,avg
6
4
[A]

[A]
4 3

2
2
1

0 0
472 474 476 478 480 472 474 476 478 480
Time [ms] Time [ms]

(c) 3 units (d) 4 units

Figure 3.7: the simulation results for the input current up to 4 units interleaved with constant energy
storage. Where, LCCM = 0.665mH , Vin = 230 V f s = 60kHz
Chapter 4

EMI filter design

PFC boost Converter

vin EMI Filter Rectifier Boost PFC RL

Figure 4.1: Block diagram of the PFC boost converter with EMI filter including the EMI filter

The electromagnetic interference (EMI) filter is used to protect the utility from the high-
frequency conducted emissions noise which it should be comply with electromagnetic
compatibility (EMC) standards, more details about the emission standard can be found in
section 1.3.
Figure 4.1 shows that EMI filter is inserted at the input of the PFC converter, which is
also called the input filter. The EMI filter volume can take up to 23% of the total converter
size [14], the current operating modes in boost inductor size has an influence on the volume
because by allowing a small current ripple as in CCM, the amount of high-frequency noise
will decrease leading to smaller EMI filter [3]. While increasing the switching frequency
will not necessarily reduce the EMI filter volume according to some studies [14] and this
will be validated in this chapter.
An investigating about the optimal volume EMI filter design based on number of the
filter stages, different current operating modes(CCM, DCM ...) and different switching
frequencies, will be conducted on this chapter.

4.1 EMI measurement

In order to design the EMI filter, the emission noise which is generated by the converter
should be measured. In the beginning, the measurement will be without any EMI filter
in order to determine the required attenuation in the filter to comply with the standard
requirements [20].

29
30 Chapter 4. EMI filter design

In order to reduce the product time-to-market, the emission noise measurement should
be obtained by using simulation or calculation which is modelling the conducted EMI noise
[21].

4.1.1 LISN
The line impedance stabilization network (LISN) is used in measuring the emission noise
with EMI receiver as shown in Figure 5.1, LISN isolates the line voltage vin from the PFC
converter for high frequencies to provide a clean and stable power supply for the EMI
receiver[22], it is also provides a fixed impedance for the EMI receiver independently of
the changeable grid impedance to ensure repeatable measurements[23] [3].

vin
PFC boost
LISN RL
Converter

EMI Receiver

Figure 4.2: Block diagram of the PFC boost converter EMI measurement by using LISN

LISN circuits are defined by CISPR standards, Figure 4.3a shows equivalent circuit of
the LISN for band B, the PFC converter is replaced by current source idm , and umeas is the
LISN output where the EMI receiver is connected (The EMI receiver impedance will be in
parallel with R LISN ) [20].

50
Impedance [ ]

10

1
100

50

(50Ω || 1 Ω)
1

0.5
10k 100k 1M 30M
Frequency [Hz]

(a) Simplified high-frequency model of (b) LISN in Figure 4.3a impedance fre-
LISN for Band B [20]. quency response

Figure 4.3

CLISN couples the noise generated by the PFC converter to the EMI receiver, where the
measured voltage umeas is determined by multiplying the the LISN transfer function to idm
4.2. DM filter design 31

[20]:  
Umeas ( f )
umeas ( f ) = idm ( f ) · (4.1)
Idm ( f )
Figure 4.5b shows the impedance frequency response for the LISN circuit in Figure 4.3a,
where at high frequencies, the input resistance of the EMI receiver will be 50 Ω.
The Single-phase LISN circuit which is used in the simulation can be found in the
appendix which is can be used for both Band A and Band B

4.1.2 EMI Receiver

In the EMI receiver, the LISN output voltage will be transferred from the time domain
umeas (t) into the frequency domain Umeas ( f ) by Fourier analysis, then Umeas ( f ) will filtered
around a sweeping frequency f sweep by using a bandpass filter as shown in Figure 4.4, the
filter bandwidth which is also called the resolution bandwidth (RBW) is defined in the
standards as 200 Hz for Band A (9-150kHz) and 9 kHz for Band B (150kHz-30MHz) [3],
[21].

150

U QP,max(f sweep )

100
U meas(f)
Level in [dB V]

50

RBW filter
Frequency sweep
envelope
-50
9k 50k 150k 500k
Frequency [Hz]

Figure 4.4

By using Equation 4.3, a quasi-peak (QP) of Umeas ( f ) can be calculated [3].

 f = f sweep + RBW
2

1
UQP,max ( f sweep )[dBµV ] = 20 · log
1µV ∑ Umeas ( f ) (4.2)
f = f sweep − RBW
2

Where UQP,max is the QP voltage.

4.2 DM filter design

There are two different noise sources, the differential-mode (DM) noise and the common-
mode noise (CM) [3], where the DM noise requires a larger filter in compare to the CM
noise. Therefore, in this project, the focus will be on the DM filter design because the
power density of the EMI filter is mainly determined by it [23].
32 Chapter 4. EMI filter design

4.2.1 Calculate the required attenuation

The filter design is depending on the required filter attenuation Attreq which is can be
found by comparing the detected QP voltage UQP,max with the CISPR QP Limits as shown
in the following equation[5]:

Attreq ( f sweep )[dB] = UQP,max ( f sweep )[dBµV ] − CISPR Limit ( f sweep )[dBµV ] + Margin[dB]
(4.3)
where a margin is included to compensate the parameter tolerances [5].
This project will consider the DM emission noise from 9 kHz to 500 kHz, Figure 4.5a
shows the CISPR QP limits for that range which can be divided into bands: Band A from 9
kHz to 150 kHz which is covered by CISPR 15 while band B (150 kHz-30 MHz) is covered
by CISPR 11 which has two classes, class A for industrial use and class B for home use [8],
( For this project class A will be used).

140 140
First peak in Band A First peak in Band B
Band A Band B
120
120
Level in [dB V]
Level in [dB V]

100
100
U QP,max(f sweep)
80
CISPR 15
80
CISPR 11 60
Class A

60
CISPR 11 40
Class B

40 20
9k 50k 150k 500k 9k 50k 150k 500k
Frequency [Hz] Frequency [Hz]

(a) CISPR QP Limits 9 kHz - 500 kHz (b) EMI Measurement 9 kHz - 500 kHz

Figure 4.5

Figure 4.5b shows the first noise peak in each band where each peak should be com-
pared with the corresponding CISPR QP limit at the design frequency f D in order to calcu-
lated the required attenuation for each filter according to Equation 4.3 where f D = f sweep
[3].

4.2.2 Filter Topology

The required attenuation Attreq is calculated based on the noise magnitude above the limits.
And the filter should be damping this noise and make lower than limits in order to fulfill
the standards.
The EMI filter can be passive or active, the EMI passive filter is made up of two basic
types of passive components:capacitors and inductors. The simplest filter consist of just a
single component, so it can be L-filter or C-filter which called first order filters, but this
type is not efficient because it requires a large value of L or C to obtain the the required
damping leading to increasing the losses [9].
LC-filter with one or more stages is usually used as shown in Figure 4.6 where the
filter is located between the PFC converter and the utility input voltage.
4.2. DM filter design 33

It is not recommended to use more than three stages filter even though it will provide
higher damping because it is an uneconomical selection [9].

Figure 4.6: Block diagram of two stages DM filter for PFC boost converter without damping stage

The component size in n-stage LC-filter should be the same component size ( L DM1 =
L DM2 = L DMn = L DMn and CDM1 = CDM2 = CDMn = CDM ) in order to get a minimum
volume design [24].
The attenuation of the n-stage filter Att LC ( f D )ns has to equal or greater than Attreq ( f D )
to ensure the filtering[5] .
The attenuation of the one stage filter Att LC ( f D )1s and the two stages filter Att LC ( f D )2s
is given by Equation 4.4 and Equation 4.6 respectively [5] .

• One stage filter:

 
Att LC ( f D )1s =  ( j2π f D )2 · L DM · CDM + 1  (4.4)
 

By solving Equation 4.4 for L DM · CDM :

Att LC ( f D )1s + 1
LC1s = 2
(4.5)
4π 2 f D

• Two stages filter:

 2 
Att LC ( f D )2s =  ( j2π f D )2 · L DM · CDM + 1 + ( j2π f D )2 · L DM · CDM  (4.6)
 

By solving Equation 4.4 for L DM · CDM :

q
3π 2 f D
2 + 4 + 5π 4 f 4
Att LC ( f D )2s · 4π 4 f D D
LC2s = 4
(4.7)
8π 4 f D

The filter corner frequency for the one stage f c(1s) and the two stages f c(1s) can be
calculated as following:

1
f c(1s) = √ (4.8a)
2 · π LC1s
1
f c(2s) = √ (4.8b)
2 · π LC2s
34 Chapter 4. EMI filter design

4.3 EMI filter optimization

In this section, an investigation about finding the optimal filter corner frequencies in oper-
ating different scenarios will be conducted, then the filter will be designed with a minimal
volume

4.3.1 Filter corner frequency

In this subsection, based on simulation, the PFC boost converter will run at different
switching frequencies to predict the EMI noise, then the required attenuation can be calcu-
lated based on Equation 4.3, after that a relation between the switching frequency and the
filter corner frequency will be found based on Equation 4.4-Equation 4.8.
That will be done in interleaved and non-interleaved PFC with different current oper-
ating modes (CCM, DCM and QCM) in Band A and B.

4.3.1.1 Non-interleaving 1 Unit

Here, one unit (Non-interleaving ) PFC boost converter will be run at different switching
frequencies in Band A and B for different modes :CCM, DCM and QCM.
The inductor size varies as a function of the switching frequency f s as shown in the
following equations for different current modes:

Vo
LCCM ( f s ) = (4.9)
4 · ∆IL,max · f s

2 · (1 − V̂in
V̂in Vout )
L DCM ( f s ) = (4.10)
4 · f s · Po,max

V̂in
V̂in · (1 − Vout )
LQCM ( f s ) = (4.11a)
2 · f s · Îin
vin =V̂in · |sin(ωt)| (4.11b)

Where, the parameters values

√ are:
Vo = 400 V, V̂in = 230 2V Po,max = 1000 W, ∆IL,max = 0.62 A and ωt = 45◦

Band A (9 kHz - 500 kHz)

The relation between the required attenuation and the switching frequency has the
same pattern in CCM, QCM and DCM, the difference only in the amplitude where in
CCM it is lower than it in QCM and DCM as Figure 4.7c shows because the big inductor
size in CCM allows a small current ripple which decreases the amount of high-frequency
noise and leads to a smaller required attenuation.
In band A, the first noise peak will be appeared at the switching frequency f s ( by
assuming that f s > 9kHz ), thus the required attenuation Attreq will be calculated based
on magnitude of the noise at f s .
4.3. EMI filter optimization 35

Figure 4.7c shows that the Attreq in (CCM, DCM and QCM ) significantly increases at
f s = 50 kHz because the standard limit (CISPR 15) gets more restricted beyond = 50 kHz.
Figure 4.7c shows also that Attreq generally increases when the switching frequency
gets higher, the reason behind this is that the LISN impedance is gradually increased up
to fixed impedance at the high frequencies as shown in Figure 4.5b and that will increase
the height of the noise peak.

CCM 25 CCM
10
DCM DCM
Corner frequency [kHz]

Corner frequency [kHz]

QCM 20 QCM

5 15

10

1
25 50 75 150 25 50 75 150
Switching frequency [kHz] Switching frequency [kHz]

(a) One stage filter (b) Two stages filter

80
CCM
DCM
QCM
60
Req Att [dB uV]

40

20

0
25 50 75 150
One-stage filter Switching frequency [kHz]

(c) Required attenuation

Figure 4.7: The relation between the filter corner frequency and the switching frequency in Band A
for different modes :CCM, DCM and QCM based on the required attenuation ( The squares are the
simulated points)

Figure 4.7a and Figure 4.7b show the filter corner frequency f c in 1 stage and 2 stages
filter respectively
At the switching frequency range (20-50kHz), f c is increasing although Attreq is in-
creasing as shown in Figure 4.7c. It is because the noise frequency f D becomes higher by
increasing f s . At f s = 50 kHz, f c drops due to the change in the limit then it continues
increasing up to f s = 150 kHz the end of band A, and if f s higher than Band A range, there
is no need to a filter.
By comparing Figure 4.7a and Figure 4.7b, it can be observed that the 2-stages filter f c
is higher than in 1 stage, because it provides higher damping. The low f c in 1-stage will
require using very big filter components.
36 Chapter 4. EMI filter design

The best f s selection is to be higher that 150 kHz. But if f s has to be less 150 kHz,
then two or higher stages filter should use with avoiding switching at the range from
= 50 kHz up to the switching frequency that gives corner frequency lower than the corner
frequencies at the at switching frequency below 50 kHz.

Band B (150 kHz - 500 kHz)

The first noise peak appears in Band B is the kth multiple of the switching frequency f s
appearing first beyond 150 kHz [5].
It can be observed from both Figure 4.8a and Figure 4.8b, that the the filter corner
frequency f c is significantly decreased at the divisors of f s = 150 kHz (30, 37.5, 50 ...150
kHz), there are two reasons behind that.
First, at those mentioned switching frequencies, the first noise peak will be appeared
at f s = 150 kHz where the Band B begins, while if the switching frequency a bit lower, the
first noise peak f D will be moved to frequency much higher that 150 kHz.
The second reason is due to the fact the decay of the amplitudes of the switching
frequency harmonics with increasing frequency [5].
For example at f s = 75 kHz, the first noise peak will be appeared at f s = 150 kHz
which is the second harmonics of f s = 75 kHz while if f s = 70 kHz, the first noise peak
will be appeared at f s = 210 kHz which is the third harmonics of f s = 70 kHz which
has lower height in compare to the noise peak at f s = 150 kHz as the second multiple of
f s = 75 kHz.
Therefore, it is not efficient to switch at the previous mentioned critical frequencies and
use a switching frequency just a bit lower than them which will increase the filter corner
frequency without affecting the boost inductor size.
4.3. EMI filter optimization 37

80
CCM 70 CCM
20
DCM DCM
Corner frequency [kHz]

Corner frequency [kHz]

60
QCM QCM
10 50

40
5
30

20

1
30 37.5 50 75 150 500 30 37.5 50 75 150 500
Switching frequency [kHz] Switching frequency [kHz]

(a) One stage filter (b) Two stages filter

90
CCM
80 DCM
QCM
Req Att [dB uV]

70

60

50

40

30
30 37.5 50 75 150 500
Switching frequency [kHz]

(c) Required attenuation

Figure 4.8: The relation between the filter corner frequency and the switching frequency in Band B
for different current operation modes :CCM, DCM and QCM based on the required attenuation (
The squares are the simulated points)

4.3.1.2 Conventional Interleaved

Here,the PFC boost converter up to four units interleaved will be run at different switching
frequencies in Band A and B in CCM and DCM and QCM. The typical phase shift 360°/N
is used here between the interleaved units.
The inductor size also varies as a function of the switching frequency f s as explained
in subsubsection 4.3.1.1, and by interleaving, the inductor size will be L1 = N · L(non,inter)
to ensure a constant energy storage as explained in subsection 3.2.3

Band A
As previously mentioned that, in band A, the first noise peak will be appeared at the
switching frequency f s . By interleaving, the effective switching frequency will be N · f s ,
where N is the number of the interleaved units.
For example in two units interleaved at f s = 25 kHz, the effective switching frequency
will be 50 kHz. Thus, the required attenuation at this frequency will be increased due to
the change in the standard limits (CISPR 15), in compare to one unit interleaved where that
38 Chapter 4. EMI filter design

increase in the required attenuation occurs at f s = 50 kHz as Figure 4.9a and Figure 4.9c
show.
The increasing in required attenuation leads to decrease the filter corner frequency, it
can be seen in Figure 4.9b and Figure 4.9d that there is a drop in the filter corner frequency
at f s = 50 kHz and f s = 25 kHz for one and two units respectively .
Since that the effective switching frequency is N · f s , then there is no need to use a
filter if the switching frequency higher than 75 kHz in two units, 50 kHz in three units and
37.5 kHz in four units because there will no peak noise in Band A.
Figure 4.10 shows as an example, the EMI measurement at f s = 35 kHz in non-
interleaving (one unit) and in two units interleaved, the first noise peak is appeared at
f s = 70 kHz after interleaving while it is at f s = 35 kHz before interleaving.

60
1 Unit 50 1 Unit
2 Unit 2 Unit

Corner frequency [kHz]

50
3 Unit 40 3 Unit
Req Att [dB uV]

4 Unit 4 Unit
40
30

30
20
20

10

0 10
25 50 75 150 25 50 75 150
Switching frequency [kHz] Switching frequency [kHz]

(a) CCM (b) CCM

90 25
1 Unit 1 Unit
2 Unit 20 2 Unit
Corner frequency [kHz]

80
3 Unit 3 Unit
Req Att [dB uV]

4 Unit 4 Unit
70 15

60

10
50

40

30
25 50 75 150 25 50 75 150
Switching frequency [kHz] Switching frequency [kHz]

(c) DCM (d) DCM

Figure 4.9: The relation between the 2-stages filter corner frequency and the switching frequency
up to four units interleaved in Band A for CCM and DCM based on the required attenuation (The
squares are the simulated points)
4.3. EMI filter optimization 39

EMI Measurement 9 kHz - 500 kHz EMI Measurement 9 kHz - 500 kHz
140 120 X 2.085e+05
Y 102.5
X 7.01e+04
120 X 3.5e+04 X 1.77e+05 100 Y 112.5
Y 104.4

Level in [dB V]
Level in [dB V]

Y 123

100 80

80 60

60 40

40 20

20 0
104 105 104 105
Frequency [Hz] Frequency [Hz]

(a) EMI measurement of one unit inter- (b) EMI measurement of two units inter-
leaved CCM at f s = 35 kHz leaved CCM at f s = 35 kHz

Figure 4.10

Band B

In two units interleaved, the odd order of the switching frequency harmonics is can-
celed out, while it has no affect on the even harmonic [18].
The filter corner frequency in two units interleaved in both Figure 4.11b and Fig-
ure 4.11d is increasing at a specific switching frequency ranges ( 30-37.5kHz, 50-75kHz
and > 150 kHz ). Because at those ranges, for one unit (non-interleaved) the first noise
peak beyond 150 kHz will be odd order of the switching frequency harmonics, but by in-
terleaving two units this odd order noise will be eliminated, then the filter will be designed
based on the next even harmonics which has higher frequency and lower amplitude as can
be seen in Figure 4.11a and Figure 4.11c, where the required attenuation is lower in those
ranges.
While at the remaining switching frequency ranges, interleaving two units is not effi-
cient, because the first noise peak in both one unit and two units will be the same even
harmonics.
For example if f s = 35 kHz, the first noise peak in one unit (non-interleaved) will be at
f s = 175 kHz, which is the 5th harmonic. But by interleaving two units the noise peak will
be at f s = 210 kHz ( 6th harmonic) as Figure 4.10 shows.
40 Chapter 4. EMI filter design

70
120
1 Unit 1 Unit
2 Unit 100 2 Unit

Corner frequency [kHz]

60 3 Unit 3 Unit
Req Att [dB uV]

4 Unit 80 4 Unit

50
60

40

40
30

20
30 37.5 50 75 150 500 30 37.5 50 75 150 500
Switching frequency [kHz] Switching frequency [kHz]

(a) CCM (b) CCM

90 60
1 Unit 1 Unit
2 Unit 50 2 Unit

Corner frequency [kHz]

3 Unit 3 Unit
80
Req Att [dB uV]

4 Unit 40 4 Unit

70 30

60 20

50
30 37.5 50 75 150 500 30 37.5 50 75 150 500
Switching frequency [kHz] Switching frequency [kHz]

(c) DCM (d) DCM

Figure 4.11: The relation between the 2-stages filter corner frequency and the switching frequency
up to four units interleaved in Band B for CCM and DCM based on the required attenuation (The
squares are the simulated points)

Three units interleaved which eliminates all the harmonics except the multiples of the
3rd order harmonic noise as Figure 4.11b and Figure 4.11d show, where it can be seen that
at switching frequency range (50kHz-75kHz), the filer corner frequency is the same in both
one unit and three units interleaved.
The same phenomenon in four units interleaved which eliminates all the harmonics
except the multiples of the 4th order harmonic noise.

4.3.1.3 Interleaved using non-standard phase-shift

As shown in subsubsection 4.3.1.2 that in band B, the conventional interleaving with typical
phase-shift does not give any benefits at some switching frequency ranges.
In this subsection a different phase-shift angle will be used, in order to target the
cancellation effect to occur at any order of harmonics [18].

Two units interleaved

As shown in subsubsection 4.3.1.2 that, if the switching frequency at the range (75kHz-
4.3. EMI filter optimization 41

150kHz), the filter corner frequency in two interleaved units will be the same as one unit
(non-interleaved).
But by using 90◦ angle as a phase-shift between the units, the filter corner frequency
will be increased in compare to the conventional interleaving (180◦ ) [18], as shown in
Figure 4.12b
The reason behind selecting 90◦ as a phase shift is because it is able to eliminate the
nd
2 harmonic of the switching frequency which is the first noise will be appeared if the
switching frequency at the range (75kHz- 150kHz).

70 120
1 Unit 1 Unit
° 100
2 Unit (180 ) 2 Unit (180°)

Corner frequency [kHz]

60 °
2 Unit (90 ) 2 Unit (90°)
Req Att [dB uV]

80
50
60

40

40
30

20
30 37.5 50 75 150 500 30 37.5 50 75 150 500
Switching frequency [kHz] Switching frequency [kHz]

(a) Switching frequency vs. Required attenu- (b) Switching frequency vs. Corner fre-
ation quency[18]

Figure 4.12: The relation between the 2-stages filter corner frequency and the switching in two units
interleaved in Band B for CCM based on the required attenuation (The squares are the simulated
points)

Using the noise phasor diagram can explain that as shown in Figure 4.13. At the
1st order harmonics of the switching frequency, there will 90◦ phase shift between the
noise from the first and the second unit, thus the total noise will be reduced without fully
cancellation, but at 2st , the noise will out of phase, thus they will cancel each other and the
total noise will be zero.
The total noise at the 3rd harmonics will be reduced is as the 1st harmonics, but at the
th
4 harmonics, the noise will be in phase, so the total noise magnitude will be the same
as the noise in one unit interleaved (non-interleaved). At the 5th harmonics, it will be the
same as the 1st and so on.
Figure 4.12a shows that the required attenuation is reduced at switching frequencies
ranges where the first noise peak appears at 3rd and 5th harmonics order of the switching
frequency.
42 Chapter 4. EMI filter design

1st 2nd 3rd 4th

90°
180°

90°

Figure 4.13: Noise phasor diagram for two units interleaved with 90° phase shift [18]

Three units interleaved

The conventional three unit interleaved does not improve the filter corner frequency at
the switching frequency range (50kHz- 150kHz). Therefore, 40° angle as phase shift will
be used here to eliminated 3rd harmonics order of the switching frequency as illustrated
at the noise phasor diagram in Figure 4.14, it shows that at the 1st order harmonics of
the switching frequency, the phase shift between noise sources is 40°, total noise will be
reduced and the same at the 2nd order harmonics but with more reduction, while at 3rd
order harmonics, the total noise is fully reduced.
By doing the same analysis for the higher order harmonics, it has been found that the
multiple of 3rd order harmonics will be cancelled, and the other harmonics will be just
reduced.

1st 2nd 3rd

80° 120°
40°

Figure 4.14: Noise phasor diagram for three units interleaved with 40° phase shift
4.3. EMI filter optimization 43

CCM, fixed ripple (Band B)

70 120
1 Unit 1 Unit
3 Unit (120°) 100 3 Unit (120°)

Corner frequency [kHz]

60
3 Unit (40°) 3 Unit (40°)
80
Req Att [dB uV]

50

60
40

30
40
20

10
30 37.5 50 75 150 500 30 37.5 50 75 150 500
Switching frequency [kHz] Switching frequency [kHz]

(a) Switching frequency vs. Required attenu- (b) Switching frequency vs. Corner fre-
ation quency

Figure 4.15: The relation between the filter corner frequency and the switching in three units inter-
leaved in Band B for CCM based on the required attenuation (The squares are the simulated points)

Four units interleaved

Here, the noise cancellation will be targeted to occur at switching frequency range (
37.5kHz, 50kHz) which is not affected by the noise cancellation in the conventional four
units interleaved.
40° is used as phase shift between the units to eliminate the 4th harmonics order of the
switching frequency as illustrated at the noise phasor diagram in Figure 4.16 which only
up to the the 4th . However, by doing the same analysis for the higher order harmonics, it
has been found that the even harmonics will be cancelled, while the odd harmonics will
be just reduced.

1st 2nd 3rd 4th

45°

Figure 4.16: Noise phasor diagram for four units interleaved with 45° phase shift
44 Chapter 4. EMI filter design

70
1 Unit
140 1 Unit
4 Unit (90°) 120 4 Unit (90°)

Corner frequency [kHz]

60
4 Unit (45°) 100 4 Unit (45°)
Req Att [dB uV]

50
80

40
60

30
40
20

10
30 37.5 50 75 150 500 30 37.5 50 75 150 500
Switching frequency [kHz] Switching frequency [kHz]

(a) Switching frequency vs. Required attenu- (b) Switching frequency vs. Corner fre-
ation quency

Figure 4.17: The relation between the filter corner frequency and the switching in four units inter-
leaved in Band B for CCM based on the required attenuation (The squares are the simulated points)

Figure 4.17 shows that the filter corner frequency in four units (45°) is lower than the
filter corner frequency in four units (90°) at some switching frequency ranges although
the four units (45°) required attenuation is lower, it is because the noise peak appears at
higher frequency in four units (90°) at those ranges which is increasing the filter corner
frequency. For example at f s = 35 kHz in four units (45°), the first noise peak appears at
177 kHz which is the 5th with reduced magnitude. But in four units (90°), it appears at the
8th , because in four units (90°) eliminates all the harmonics expect the multiples of the 4th
order harmonics of the switching frequency.

EMI Measurement 9 kHz - 500 kHz EMI Measurement 9 kHz - 500 kHz
120 120
X 2.805e+05 X 3.5e+04
Y 98.39 Y 118.6 X 1.77e+05
100 100 Y 92.74
Level in [dB V]

Level in [dB V]

80 80

60 60

40 40

20 20

0 0
104 105 104 105
Frequency [Hz] Frequency [Hz]

(a) EMI measurement of four units (90°) in- (b) EMI measurement of four units (45°) in-
terleaved CCM at f s = 35 kHz terleaved CCM at f s = 35 kHz

Figure 4.18

4.3.1.4 Summary
• In band A, the interleaved configuration provides high benefits which is the possi-
bility of not using the filter if the switching frequency higher than 75 kHz in two
4.3. EMI filter optimization 45

units, 50 kHz in three units and 37.5 kHz in four units.

• In band B, it has been observed that using the typical phase-shift between the units is
not efficient at all the switching frequency ranges. Therefore, a different phase-shift
is used in order to achieve a high corner frequency.
Equation 4.12 can be used as a a generic formula to find the phase shift angles which
give the optimal corner frequency

1
α =360° · if k Not a multiple of N (4.12a)
N
1
α =360° · if k a multiple of N (4.12b)
min( f actor ( N ) · k)

Where, N is the number of the interleaved units.

k is the harmonic order of the frequency switching kth which will be appeared as a
first noise peak in Band B.
Figure 4.19 shows the phase shift angles which give the optimal corner frequency
at the switching frequency range (30-150kHz) up to four units interleaved based on
Equation 4.12.

30kHz 37.5kHz 50kHz 75kHz 150kHz

th th rd nd st
Harm. order: 5 4 3 2 1

∘ ∘ ∘ ∘ ∘
2 Units 180 45 180 90 180

∘ ∘ ∘ ∘ ∘
3 Units 120 120 40 120 120

∘ ∘ ∘ ∘ ∘
4 Units 90 45 90 90 90

Figure 4.19: phase shift angles which give the optimal corner frequency at the switching frequency
range (30-150kHz) up to four units interleaved based on Equation 4.12

4.3.2 Filter component size

In this subsection, the filter will be designed with a minimal volume. The filter corner
frequency f c can be translate to the boxed volume by using the needed inductor and
capacitor volume. The total filter volume Vtot for 1 stage filter without damping is equal to
the inductor volume VL and the capacitor volume VC :

Vtot = VL + VC (4.13)
2 according
The inductor volume VL is proportional to the stored energy EL = 1/2 · L · Iin
to [5]. But by assuming that Iin is constant, then VL will be proportional to the inductor
46 Chapter 4. EMI filter design

value L. And this is also applied for the relation between capacitor volume VC and the
capacitor value C if assumed that Vin is constant , where the stored energy in the capacitor
2.
is EL = 1/2 · C · Vin

70 20
Boxed inductance volume [cm 3 ]

Boxed capacitor volume [cm3 ]

Po = 1000W Vin = 305V
60 Po = 2000W Vin = 275V
Po = 500W 15
50

40
10
30

20 5
10

0 0
0 100 200 300 400 500 0 0.5 1 1.5 2 2.5
L[uH] C[uF]

(a) Inductor boxed-volume approxima- (b) Capacitor boxed-volume approxima-

tion using kool mu cores, in 230V for dif- tion using polypropylene dielectric, X2
ferent power rates class in different voltage rates

Figure 4.20

The relations between VL and L and also the relation between VC and C can be derived
analogously from the manufacturer’s data [5]
Figure 4.20a shows the relations between VL and L using kool mu cores in different
power rates and Figure 4.20b shows the relations between VC and C using kool using
polypropylene dielectric, X2 class in different voltage rates:

VL =k L1 · L + k L2 (4.14a)
VC =k C1 · C + k C2 (4.14b)

Where k L1 is a constant which is the linear equation slope that describes the propor-
tionality between L and VL while k L2 is the intercept and the same for k C1 and k C2 .
Table 4.1 and Table 4.2 shows those constant values based on Figure 4.20a and Fig-
ure 4.20b data.

Po = 1000 W Po = 2000 W Po = 500 W

k L1 0.102 0.0839 0.0495
k L2 2.28 25.3017 -0.3423

Table 4.1: k L1 and k L2 values for the linear equations in Figure 4.20a

Vin = 275 V Vin = 305 V

k C1 4.84 7.06
k C2 0.78 0.47

Table 4.2: k C1 and k C2 values for the linear equations in Figure 4.20b
4.4. Analytical estimation of DM noise 47

By using the k L1 , k L2 , k C1 , and k C2 for specific power rated for the inductor and input
voltage for the capacitor, the total filter volume can can be minimized [25] :

Vtot = k L1 · L + k L2 + k C1 · C + k C2 −→ min (4.15)

By solving Equation 4.8 for C:

a 1
C= , a= (4.16)
L 4 · π 2 · f c2
Then by differentiation of Equation 4.15 with respect to L and equating with zero:

∂Vtot
=0 (4.17)
∂L
Finally, by solving Equation 4.17 for L and C gives the optimal values of L and C [25]:

s
a · k C1
L= (4.18a)
k L1
s
a · k L1
C= (4.18b)
k C1

4.4 Analytical estimation of DM noise

In the previous section, the EMI filter optimization was based on running simulation at
each the noise point as shown in the figures, which was a time-consuming process. There-
fore, it will much faster to use an analytical estimation of DM noise .
[5] proposed a method to estimation of for DM noise in the single unit PFC boost
converter at CCM based on an analytical calculation.
This method based on assuming that, the total high frequency rms noise current
Inoise,RMS is accurate enough for estimating the UQP,max at the EMI receiver.
The converter input rms current Iconv,RMS which is equal to Iin,RMS consists of the
mains rms current Imains,RMS and Inoise,RMS :
2 2 2
Inoise,RMS = Iin,RMS − Imains,RMS (4.19)

Inoise,RMS in the single unit PFC boost converter at CCM is given by [5]:

2 −64 · +12 · π + 9 · α2 π 2
Inoise,rms = · α · ∆IL,max (4.20)
18π
Where, α = V̂in 2 /V and ∆I
o L,max can be calculated from Equation 2.5
After that Inoise,RMS will be multiplied by the LISN impedance, in order to calculate
ULISN which is the LISN voltage in time domain.
Finally, the estimated voltage peak in frequency domain Uest can be calculated by using
the following equation [5]:
 
ULISN 1
Uest ( f D )[dBµV ] = 20 · log · (4.21)
k2 µV
48 Chapter 4. EMI filter design

Where, k is the harmonic order of the frequency switching kth which will be appeared
as a first noise peak in Band B and it is added to the equation in order to take into consid-
eration that noise peak is decreased by increasing the frequency.

70
80
Simulation Simulation
Estimation 70 Estimation

Corner frequency [kHz]

60
Req Att [dB uV]

60

50
50

40
40

30
30
30 37.5 50 75 150 500 30 37.5 50 75 150 500
Switching frequency [kHz] Switching frequency [kHz]

(a) Switching frequency vs. Required attenu-(b) Switching frequency vs. Corner fre-
ation quency

Figure 4.21: The relation between the filter corner frequency and the switching for single unit PFC
boost converter at CCM in Band B for CCM based on the required attenuation (The blue squares are
the simulated points and orange squares are the estimated points )

Figure 4.21 shows that, there is not a significant variation between simulation (in blue)
and the estimation (in orange) especially at the low switching frequency.

4.5 Experimental test

The experimental test is conducted in order to validate the EMI noise simulation results
and to test the non-conventional interleaved
√ in the Lab
Where, Vo = 400 V, V̂in = 230 2V, Po,max = 2000 W, L = 180 uH , f s = 20 kHz where
three test cases are considered as shown in Figure 4.22.
The first test case is 2-unit interleaved with phase shift α = 0° and this the same as
using 1-unit(Non-interleaved) but the different is that total boost inductor will be half
of L = 180 uH, then it can be compared with the second test (α = 180°) and third test
(α = 90°) to ensure a constant energy storage in the inductor.
Figure 4.22 there is no significant variation between the simulation and the experimen-
tal results
4.5. Experimental test 49

140
X 1.59e+05
X 4.006e+04
140 Y 129.3 120
X 4.006e+04 Y 116
X 1.998e+04 Y 129.3
X 1.59e+05
Y 137.3 Y 115.7
Level in [dB V]

120

Level in [dB V]
100
100
80
80
60
60
Simulation 40
Experimental Simulation
40 Experimental
4 5 20
10 10
Frequency [Hz] 104 105

(a) α = 0° (b) α = 180°

X 1.998e+04
140 Y 134.4

X 1.59e+05
Y 116
Level in [dB V]

120

100

80

60
Simulation
Experimental
40
104 105
Frequency [Hz]

(c) α = 90°

Figure 4.22: The EMI√measurement for 2-unit interleaved in simulation and experimental where
Vo = 400 V, V̂in = 230 2V, Po,max = 2000 W, L = 180 uH , f s = 20 kHz
Chapter 5

Energy efficiency

The components selection will be based on the current and voltage rating according to
functional requirements which can be found in Table 1.1

5.1 Components selection and losses

5.1.1 Rectifier bridge
The input rectifier bridge can use a slow recovery diodes [26] and the current rating should
be higher than the peak of the input current.
The maximum possible input current occurs at the low line input voltage with maxi-
mum load:

Pout,max √
Îin,max = · 2 (5.1)
Vin,min
"GBPC3506W" (VR =600 V, IF =35 A) is used as rectifier bridge, the peak reverse
√ voltage
VR is selected to be higher than the maximum input voltage Vin,max = 265 · 2V in order
to provide a margin against line surges [17].
The diode bridge forward current IF is selected to be much higher than Îin,max to take
into the account the current ripple which is DCM can reach up to half the peak current.

5.1.1.1 Rectifier bridge Losses

The power dissipation in the rectifier bridge Pbridge is given by [26]:

2
Pbridge = 4(VF · Ibridge,avg + Ibridge,RMS · Rdiode ) (5.2)
Equation 5.19 shows that Pbridge is made up of two types of loss, one due to the diode
forward voltage drop VF and the other due to the diode dynamic resistance Rdiode .
Ibridge,avg is the average input current flowing through one of the bridge rectifying
diodes:
√ √
1 2 2 Pout
Z π
Ibridge,avg = Î · sin(ωt)d(ωt) = · Iin,RMS = · (5.3)
2π 0 in π π Vin

51
52 Chapter 5. Energy efficiency

Ibridge,RMS is the RMS input current flowing through one of the bridge rectifying diodes:
r √ √
1 2 2 Pout
Z π
Ibridge,RMS = Îin · · 2
sin(ωt) d(ωt) = · Iin,RMS = · (5.4)
2π 0 2 2 Vin

5.1.2 Boost Inductor

The Boost inductor selection can be found section 2.2.
The DC resistance DCR in the inductor dissipates power which is called the inductor
copper loss:

2
PL = IL,RMS · DCR (5.5)
IL,RMS is the inductor RMS current which is equal to the input RMS current Iin,RMS :

Po
IL,RMS = (5.6)
Vin,min

5.1.3 Switch
The MOSFET will be used as switch because it is more efficient in in low-voltage, low
power and high frequency applications in compare to IGBT [27].
Mosfet selection main considerations are Small R to reduce the conduction loss and
fast turn-on/off time to reduce the switching loss [12].
CoolMOS CP Mosfet series is recommend by Infineon (Semiconductor manufacturing
company) to use for boost applications [12], "IPP60R250CP" will be used in this project,
this Mosfet is used also in the test setup

5.1.3.1 Mosfet Losses

The power dissipation in the MOSFET can be considered as losses, which are conduction
losses and switching losses :

PMos f et = Pcon + Psw (5.7)

Conduction losses Pcon :
When the MOSFET switch ON, the MOSFET RMS current IQ,RMS is conducting across
the drain-source on-resistance R DS,on resulting in the conduction losses which can be cal-
culated by using the following equation:

2
Pcon = R DS,on · IQ,RMS (5.8)

• MOSFET RMS current calculation in CCM :

Since the switching frequency is much higher than the line frequency, the Mosfet
RMS current con be derived by calculating the mean square current in one switching
cycle i2Q (ωt) then integrate it over the half of the line period and take the square root
[28]:
5.1. Components selection and losses 53

1
Z t+ Tsw
i2Q (ωt) = Is,avg i2Q (t)dt (5.9a)
Tsw t
r Z
1 π 2
IQ,RMS = i (ωt)d(ωt) (5.9b)
π 0 Q

Figure 5.1: The Mosfet current waveform in one switching period

When the Mosfet is switched ON, the Mosfet current i2Q will be equal to the input
current iin (t) and zero when the Mosfet is switched OFF. Therefore, i2Q will be [28]:

i2Q (ωt) = d(t) · iin

2
= d(t) · ( Îin · sin(ωt))2 (5.10)

Where, d(t) is the duty cycle as function of the time, and by assuming that the
converter controller dynamics are fast compared to the line frequency d(t) can be
written as [28]:

Vˆin
d(t) = 1 − · |sin(ωt)| (5.11)
Vout
By Substituting Equation 5.10 and Equation 5.11 into Equation 5.9b, an expression
for IQ,RMS can be found:
s
1 Vˆin
Z π
IQ,RMS = (1 − · |sin(ωt)|) · ( Îin · sin(ωt))2 d(ωt) (5.12)
π 0 Vout

which can be simplified :

s
1 Vˆin
Z π 
IQ,RMS = · Î sin2 (ωt) − · sin3 (ωt) d(ωt) (5.13)
π in 0 Vout

Which can be solved and give the final expression for IQ,RMS [28]:
s √
8 · 2 · Vin
Is,RMS = Iin,RMS · 1− (5.14)
3 · π · Vout
54 Chapter 5. Energy efficiency

• MOSFET RMS current calculation in interleaved CCM :

The interleaved units which they are in parallel will share the input current, so by re-
placing Iin,RMS in Equation 5.14 by Iin,RMS /n an expression for IQ,RMS in interleaved
CCM can be derived[29]:
s √
Iin,RMS 8 · 2 · Vin
Is,RMS = · 1− (5.15)
N 3 · π · Vout

Where, N is the number of the interleaved units

• MOSFET RMS current calculation in DCM and QCM :
In this project, the simulation will be used to estimate the MOSFET RMS current
because it is complex to get an expression for it by means of the analytical calculation
[30].

Switching losses Pcon :

The Mosfet will experience both voltage and current during the turn-on time ton and
the turn-off time to f f resulting in energy loss at each switching cycle , the switching losses
in PFC converter can be calculated as following [12]:

Psw = 0.5 · Iin,avg · Vout · (ton + to f f ) · f sw (5.16)

Where Iin,avg is the average input current which is used to estimate the losses over the
line cycle [12]:
√ √
1 π 2 2 2 2 Pout
Z
Iin,avg = Î · sin(ωt)d(ωt) = · Iin,RMS = · (5.17)
π 0 in π π Vin
and the turn-on time and turn-off time can be calculated as following [12]:
V − V  V − V 
g th ds pl
ton = Ciss · R g · ln + Crss · R g · (5.18)
Vg − Vpl Vg − Vpl
V  V − V 
pl ds pl
to f f = Ciss · R g · ln + Crss · R g · (5.19)
Vth Vpl
Where,
Vth is the Mosfet gate threshold voltage
Vg is the Mosfet gate plateau voltage
Ciss is the Mosfet input capacitance
Crss = Q gd /Vds is the Mosfet reverse transfer capacitance
Q gd is the Mosfet gate-drain charge
Vds is the Mosfet drain-source voltage which is equal to the output voltage Vout
R g is the Mosfet gate resistor

5.1.4 Boost Diode

Silicon Carbide (SiC) Schottky diodes is recommended to use as a boost diode because they
have no reverse recovery losses can be neglected due to the very small capacitive charge
Qc and that is a benefit especially in CCM[12], "IDH16G65C5" is selected as a boost diode.
5.1. Components selection and losses 55

5.1.4.1 Boost Diode Losses

As mentioned in the bridge loss that the conduction loss in the diode is made up of two
types of loss, one due to the diode forward voltage drop VF and the other due to the diode
dynamic resistance Rdiode :

2
PDiode = VF · ID,avg + ID,RMS · Rdiode (5.20)
• Boost diode average current The Boost diode average current ID,avg is equal to the
output current:

Po
ID,avg = (5.21)
Vout
• Boost diode RMS current By using the same analysis which is used to derive the
MOSFET RMS current for the diode RMS current ID,RMS , the following equation can
be found:
s √
Po 8 · 2 · Vin
ID,RMS = · (5.22)
Vin 3 · π · Vout

5.1.5 Output Capacitor

The output voltage ripples ∆uo can be filter by using the output capacitor Co

uo = Vo ± ∆uo (5.23)
s
1
∆uo = Iout · )2 + ESR2 (5.24)
(2 · π · 2 · f 1 · Co
Where the ripple frequency is twice the line frequency 2 · f 1 , and by assuming that the
ESR capacitor is low in compare to the capacitive reactance then the ESR can be omitted,
by solving Equation 5.24 for Co , the following equation can be used to select the output
capacitor:

Iout
Co > (5.25)
2 · π · f 1 · ∆uo,pp · Vout
Where ∆uo,pp = 2 · ∆uo is the peak to peak voltage ripples which is usually selected to
be around 1.5% of Vo [26], furthermore it should fulfill ∆uo,pp < Vo − Vin,max in order to
ensure the boost PFC functionality [3].
Despite that ESR does not has an affect on the ∆uo , it should be taken into consideration
for the capacitor loss which is given by the following equation [26]
2
PC = IC,RMS · ESR (5.26)

Where IC,RMS is the output capacitor current RMS current.

The ripple component of the diode current will be filtered in the output capacitor
because it offers smaller impedance in comapre to the load resistance [6], then IC,RMS can
be calucalted by using the following equation:
56 Chapter 5. Energy efficiency

s √ 2
8 · 2 · Pout P2
IC,RMS = − out
2
(5.27)
3 · π · Vout · Vin Vout

5.1.6 Total losses

The total losses is equal to the sum of the components loss:

Ptot,loss = Pbridge + PL + PMos f et + PDiode + PC (5.28)

The converter efficiency can be calculated by using Equation 5.29 which is written as a
function of the output power Ptot,loss in order to get the efficiency curve as shown Figure 5.2

Po
η= (5.29)
Po + Ptot,loss

Efficiency curve for v in =230 volt

98.8

98.7

98.6
Efficiency [%]

98.5

98.4

98.3

98.2
1 Unit
98.1 2 Unit
3 Unit

98
100 200 300 400 500 600 700 800 900 1000
P out [W]

Figure 5.2: Efficiency curves of interleaved PFC converter in CCM up to 3 units

Chapter 6

Phase-shedding control

Phase-shedding technique has been developed to improve the efficiency at the light load
in the multiphase converter such as interleaved PFC which contains N units in parallel,
the process of the phase shedding is by disconnecting some units when the load decreases
below a certain limit , and it can be in opposite way by adding some units when the load
increases [31].

Efficiency curve for v in =230 volt

98.8

98.7

98.6
Efficiency [%]

98.5

98.4

98.3

98.2 1 Unit
2 Unit
98.1 3 Unit
Phase-shedding

98
100 200 300 400 500 600 700 800 900 1000
P out [W]

Figure 6.1: Efficiency curves of interleaved PFC converter in CCM up to 3 units which is derived in
chapter 5, the black dashed line shows the converter efficiency after applying phase-shedding

Figure 6.1 shows the efficiency curves of interleaved PFC converter up to 3 units, the
efficiency of 1 unit deteriorates when at the maximum load, thus it is more efficient to
connect the 3 units at that load as the figure shows, the load can be divided into three
ranges, the first range (100 W- 361 W) where only one unit must be inserted, (361 W- 641 W)
for 2 units and (641 W- 1000 W) for 3 units.

57
58 Chapter 6. Phase-shedding control

6.1 EMI filter design in phase-shedding

The EMI noise in phase-shedding is not constant, it varies with the load changes which
will change the number of the connected units, and changing the number of the connected
units will change the boost inductor equivalent value which affects the amount of noise.
Therefore, the EMI filter should be designed based on the worst case which requires the
lowest corner frequency to ensure that is capable to filter any possible noise.

6.1.1 Two Units interleaved

In the following subsection an example for designing EMI filter in Two Units interleaved
and it will be compared with
√ a single unit (Non-interleaved) Where, the parameters values
are: Vo = 400 V, V̂in = 230 2V Po,max = 1000 W, ∆IL,max = 0.62 A
And the switching frequency is selected to be f s = 70 kHz, based on what has been
explained in subsubsection 4.3.1.1
Table 6.1 shows a comparison between Two Units interleaved and single unit (non-
interleaved) EMI design, where the first column is showing shows the results for the single
unit (non-interleaved) operating with the full load, the second column is showing the
results for the two unit interleaved also operating with the full load with phase shift 180◦
which the optimal phase shift angle when f s = 70 kHz according to subsubsection 4.3.1.4.
The third column is showing the results for one unit out of two unit interleaved because of
using the phase-shedding when the load is decreased (half load)

Single unit (Non-inter.) 2 unit (180◦ ), full load 1 unit, half load
Ltot [mH] 2.3 2.3 4.6
∆IL,max 0.62 0.115 0.31
Attreq [dB] 41.7 36.5 35.8
f D [kHz] 210 280 210
2-satge f c [kHz] 58.77 89.67 74.4
L DM [uH] 22.53 - 17.8
CDM [nF] 325.5 - 257
Vtot [cm3 ] 15 - 12.76

Table 6.1: Comparison between Two Units interleaved and single unit (non-interleaved) EMI design

Ltot in (1 unit,half load) is the double of Ltot in (Single unit (Non-inter.) to ensure a
constant energy storage as explained in subsection 3.2.3. f c = 74.4 kHz in (1 unit,half load)
is lower than f c = 89.67 kHz in (2 unit , full load) which is before phase-shedding. Thus,
f c = 74.4 kHz will be used for designing the EMI filter.
L DM , CDM and Vtot are calculated based on minimal volume as explained in subsec-
tion 4.3.2.
The total volume of EMI filter in interleaving is lower than it in single unit (Non-inter.)
as Table 6.1.
6.1. EMI filter design in phase-shedding 59

EMI Measurement 9 kHz - 500 kHz

140 EMI Measurement 9 kHz - 500 kHz
120
X 2.085e+05
120 Y 108.8
Level in [dB V]

100

Level in [dB V]
100
80
80

60 60

40 40
20
104 105 20
Frequency [Hz] 104 105
Frequency [Hz]
(a) EMI measurement of (1 unit, half load)
(b) EMI measurement of (1 unit, half load)
at f s = 70 kHz before applying the EMI fil-
at f s = 70 kHz after applying the EMI filter
ter

Figure 6.2

Figure 6.2 shows the EMI measurement of (1 unit, half load) before and after applying
the EMI filter (L DM = 17.8 uH,CDM = 257 nF), where it can be seen that there is no noise
peak appearing in band B after applying the EMI filter.
Chapter 7

Conclusion and future work

• It has been shown that the boost inductor size has an affect on the input current
ripple, the inductor size in current operating modes CCM,DCM and QCM has been
calculated analytically and validate in simulation, in future the boundary conduction
mode (BCM) can be taken into consideration by using a variable switching frequency.
• The boost inductor size in interleaved CCM has been derived analytically, deriving
an expression for the boost inductor size in interleaved in DCM and QCM can be as
future work.
• The relation between the filter corner frequency and the switching frequency in Band
A and B for different modes :CCM, DCM and QCM based on the required attenua-
tion in single and interleaved PFC has been found.
• A generic formula to find the phase shift angles which give the optimal corner fre-
quency in interleaved PFC has been found.
• A straightforward way for designing of the EMI filter with a minimal volume has
been derived. Finding a relation between the boost inductor with its volume can be
as a future work, then A minimal converter total volume can be found.
• An experimental test for the EMI noise measurements has been conducted for two
units interleaved with conventional phase shift in chapter 4. Testing the non-standard
phase-shift with higher number of units can be as a future work.

61
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67
68 Appendix A. PLECS Model schematic

Appendix A

PLECS Model schematic

A.1 Full diagram

Figure A.1
A.2. LISN circuit 69

A.2 LISN circuit

L2 L1
A iD M

C3 C1 C2

L_Grid
R4 R2 R3 R1 V V1
L_DUT

N_DUT

N_Grid R5 R21 R31 R11 V2 V

C4 C11 C21
L21 L11

Figure A.2: Single-phase circuit of LISN A (CISPR 16-1-2) [8]

Where: R1 = R11 = 50 Ω, R3 = R31 = 1000 Ω, R2 = R21 = 5 Ω, R4 = R5 = 10 Ω,

C1 = C11 = 8 uF, C2 = C21 = 250 nF, and C3 = C4 = 4 uF,