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Mos Field Effect Transistor: Data Sheet

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0% found this document useful (0 votes)
116 views8 pages

Mos Field Effect Transistor: Data Sheet

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Adam Schwemlein
Copyright
© © All Rights Reserved
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DATA SHEET

MOS FIELD EFFECT TRANSISTOR


2SK3108
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE

DESCRIPTION
The 2SK3108 is N channel MOS FET device that features a ORDERING INFORMATION
low on-state resistance and excellent switching characteristics, PART NUMBER PACKAGE
and designed for high voltage applications such as DC/DC 2SK3108 Isolated TO-220
converter.

FEATURES
•Gate voltage rating ±30 V
•Low on-state resistance
RDS(on) = 0.4 Ω MAX. (VGS = 10 V, ID = 4.0 A)
•Low input capacitance
Ciss = 400 pF TYP. (VDS = 10 V, VGS = 0 V)
•Avalanche capability rated
•Built-in gate protection diode
•Isolated TO-220 package

ABSOLUTE MAXIMUM RATING (TA = 25°C)

Drain to Source Voltage (VGS = 0 V) VDSS 200 V


Gate to Source Voltage (VDS = 0 V) VGSS ±30 V

Drain Current(DC) (TC = 25°C) ID(DC) ±8.0 A


Note1
Drain Current(pulse) ID(pulse) ±24 A

Total Power Dissipation (TA = 25°C) PT1 2.0 W

Total Power Dissipation (TC = 25°C) PT2 25 W

Channel Temperature Tch 150 °C

Storage Temperature Tstg −55 to +150 °C


Note2
Single Avalanche Current IAS 8.0 A
Note2
Single Avalanche Energy EAS 51 mJ

Note1. PW ≤ 10 µs, Duty Cycle ≤ 1%


2. Starting Tch = 25°C, VDD = 100 V, RG = 25 Ω , VGS = 20 V→0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. D13331EJ1V0DS00 (1st edition) The mark ★ shows major revised points. © 1998,2000
Date Published January 2000 NS CP (K)
Printed in Japan
2SK3108

ELECTRICAL CHARACTERISTICS (TA = 25°C)


Characteristics Symbol Test Conditions MIN. TYP. MAX. Unit
Drain Leakage Current IDSS VDS = 200 V, VGS = 0 V 100 µA
Gate Leakage Current IGSS VGS = ±30 V, VDS = 0 V ±10 µA
Gate to Source Cut-off Voltage VGS(off) VDS = 10 V, ID = 1 mA 2.5 4.5 V
Forward Transfer Admittance | yfs | VDS = 10 V, ID = 4.0 A 1.5 S
Drain to Source On-state Resistance RDS(on) VGS = 10 V, ID = 4.0 A 0.32 0.4 Ω
Input Capacitance Ciss VDS = 10 V 400 pF
Output Capacitance Coss VGS = 0 V 110 pF
Reverse Transfer Capacitance Crss f = 1 MHz 55 pF
Turn-on Delay Time td(on) VDD = 100 V, ID = 4.0 A 12 ns
Rise Time tr VGS(on) = 10 V 25 ns
Turn-off Delay Time td(off) RG = 10 Ω 40 ns
Fall Time tf 20 ns
★ Total Gate Charge QG VDD = 160 V 18 nC
Gate to Source Charge QGS VGS = 10 V 3.5 nC
Gate to Drain Charge QGD ID = 8.0 A 10 nC
Diode Forward Voltage VF(S-D) IF = 8.0 A, VGS = 0 V 1.0 V
Reverse Recovery Time trr IF = 8.0 A, VGS = 0 V 250 ns
Reverse Recovery Charge Qrr di/dt = 50 A/µs 1.0 µC

TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME

D.U.T. D.U.T. VGS


RG = 25 Ω L RL
VGS 90 %
10 % VGS(on)
Wave Form
RG 0
PG. 50 Ω VDD PG.
VDD
VGS = 20 → 0 V ID 90 %
90 %
VGS ID
BVDSS 10 % 10 %
0 ID 0
IAS Wave Form

ID VDS τ td(on) tr td(off) tf


VDD
τ = 1 µs ton toff
Duty Cycle ≤ 1 %
Starting Tch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.
IG = 2 mA RL

PG. 50 Ω VDD

2 Data Sheet D13331EJ1V0DS00


2SK3108

★ TYPICAL CHARACTERISTICS (TA = 25°C)

DRAIN CURRENT vs. FORWARD TRANSFER CHARACTERISTICS


DRAIN TO SOURCE VOLTAGE
100
30 Pulsed

25 VGS = 30 V 10

ID - Drain Current - A
ID - Drain Current - A

20 1
VGS = 10 V
15
0.1

10 Tch =125˚C
75˚C
0.01 25˚C
5 -25˚C
VDS = 10 V
Pulsed 0.001
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V

GATE TO SOURCE CUT-OFF VOLTAGE vs. FORWARD TRANSFER ADMITTANCE vs.

|yfs| - Forward Transfer Admittance - s


CHANNEL TEMPERATURE DRAIN CURRENT
VGS(off) - Gate to Source Cut-off Voltage - V

5.0 10
VDS = 10 V VDS =10 V
ID = 1 mA Pulsed
4.5

1 Tch = -25˚C
4.0
Tch = 25˚C
Tch = 75˚C
3.5 Tch = 125˚C
0.1
3.0

2.5
0.01
2.0 0.01 0.1 1 10 100
− 50 − 25 0 25 50 75 100 125 150
Tch - Channel Temperature - ˚C ID- Drain Current - A

DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN TO SOURCE ON-STATE


RDS(on) - Drain to Source On-state Resistance - Ω
RDS(on) - Drain to Source On-state Resistance - Ω

GATE TO SOURCE VOLTAGE RESISTANCE vs. DRAIN CURRENT


1.0 1.0
Pulsed Pulsed

0.8 0.8
VGS = 10 V
ID = 8.0 A 0.6
0.6 4.0 A
1.6 A

0.4 0.4 VGS = 30 V

0.2 0.2

0 0
0 2 4 6 8 10 12 14 16 18 20 0.1 1 10 100
VGS - Gate to Source Voltage - V ID - Drain Current - A

Data Sheet D13331EJ1V0DS00 3


2SK3108

DRAIN TO SOURCE ON-STATE RESISTANCE vs.


CHANNEL TEMPERATURE
SOURCE TO DRAIN DIODE
RDS(on) - Drain to Source On-state Resistance - Ω

1.2 FORWARD VOLTAGE


100
Pulsed
1.0

ISD - Diode Forward Current - A


ID = 8.0 A
0.8
10

0.6 ID = 4.0 A

VGS = 10 V
0.4 1 VGS = 0 V

0.2
VGS = 10 V
Pulsed
0 0.1
− 50 − 25 0 25 50 75 100 125 150 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Tch - Channel Temperature - ˚C VSD - Source to Drain Voltage - V

CAPACITANCE vs. DRAIN TO


SOURCE VOLTAGE SWITCHING CHARACTERISTICS
10000 1000
VGS = 0 V
td(on), tr, td(off), tf - Switching Time - ns
Ciss, Coss, Crss - Capacitance - pF

f = 1 MHz
tr

1000 100

tf
Ciss
td(off)
100 td(on)
10

Coss VDD = 100 V


VGS = 10 V
Crss RG = 10 Ω
10 1
0.1 1 10 100 1000 0.1 1 10 100
VDS - Drain to Source Voltage - V ID - Drain Current - A

REVERSE RECOVERY TIME vs.


DRAIN CURRENT DYNAMIC INPUT/OUTPUT CHARACTERISTICS
1000 200 16
ID = 8.0 A VGS - Gate to Source Voltage - V
VDS - Drain to Source Voltage - V
trr - Reverse Recovery Time - ns

14

150 VDD = 160 V 12


100 V
100 40 V 10

100 8

6
10
50 VDD = 160 V 4
100 V
40 V 2
di/dt = 50A / µs
1 VGS = 0 V
0 0
0.1 1 10 100 0 5 10 15 20

ID - Drain Current - A QG - Gate Charge - nC

4 Data Sheet D13331EJ1V0DS00


2SK3108

DERATING FACTOR OF FORWARD BIAS TOTAL POWER DISSIPATION vs.


SAFE OPERATING AREA CASE TEMPERATURE
40
dT - Percentage of Rated Power - %

PT - Total Power Dissipation - W


100
30
80

60 20

40
10
20

0 0
0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160
TC - Case Temperature - ˚C TC - Case Temperature - ˚C

FORWARD BIAS SAFE OPERATING AREA


100

ID(pulse) PW
ited =
Lim 10
ID - Drain Current - A

S(o
n) 10
0 µs
10 RD µs

ID(DC) 1
Po m
s
we 10 3 m
r D 10 m s
iss 0 m s
ip s
at
io
1 n
Li
m
ite
d

TC = 25 ˚C
0.1 Single Pulse
1 10 100 1000
VDS - Drain to Source Voltage - V

TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH


1 000
rth(t) - Transient Thermal Resistance - ˚C/W

100 Rth(ch-A) = 62.5˚C/W

10 Rth(ch-C) = 5˚C/W

0.1

Single Pulse
0.01
10 µ 100 µ 1m 10 m 100 m 1 10 100 1 000

PW - Pulse Width - s

Data Sheet D13331EJ1V0DS00 5


2SK3108

SINGLE AVALANCHE ENERGY vs. SINGLE AVALANCHE ENERGY


INDUCTIVE LOAD DERATING FACTOR
100
VDD = 100 V VDD = 100 V
IAS - Single Avalanche Energy - A

VGS = 20 V 0 V VGS = 20 V 0 V
RG = 25 Ω 100 RG = 25 Ω

Energy Defrating Factor - %


Starting Tch = 25˚C IAS 8.0 A

80

10 IAS = 8.0 A 60
EA
S
=5
1m 40
J

20

1 0
0.01 0.1 1 10 25 50 75 100 125 150
L - Inductive Load - mH Starting Tch - Starting Channel Temperature - ˚C

6 Data Sheet D13331EJ1V0DS00


2SK3108

PACKAGE DRAWING(Unit : mm)

Isolated TO-220 (MP-45F)

10.0±0.3 4.5±0.2
φ 3.2±0.2
2.7±0.2

EQUIVALENT CIRCUIT

Drain
15.0±0.3

3±0.1
12.0±0.2

Body
Gate Diode
4±0.2
13.5 MIN.

Gate
Protection Source
Diode

0.7±0.1 1.3±0.2 2.5±0.1


1.5±0.2 0.65±0.1
2.54 TYP. 2.54 TYP.
1.Gate
2.Drain
3.Source
1 2 3

The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.

Data Sheet D13331EJ1V0DS00 7


2SK3108

• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
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rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
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"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
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M7 98. 8

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