Lab Session # 9

Finite State Machines (FSMs)

1. Introduction
In this experiment, you will get introduced to the concept of finite state machines (FSMs). In addition, you
will learn to design, implement and test a Moore type FSM using Quartus II Software.

2. Objectives
By the end of this lab experiment, students will:
• Learn the concept of Finite State Machines (FSMs).
• Know the difference between Moore and Mealy types of FSMs.
• Learn to design a Moore type FSM – a MOD counter and test it using Quartus II Software.
• Practice testing their designs by simulation and downloading on the Cyclone IV E FPGA on Altera
DE2-115 board.

3. Finite State Machines (FSMs)

Synchronous sequential circuits are realized using combinational logic and one or more flip-flops.
The general structure of such a circuit is shown in Figure 1. The circuit has a set of primary inputs (i.e.,
w), and produces a set of outputs (Z).

• Values of flip-flop outputs (Q) is referred to as state of the circuit.

• Under control of clock signal, flip-flop outputs change their state and the circuit moves
from one state to another.

• Sequential circuits are also called finite state machines (FSMs), as the functional behavior of
these circuits can be represented using a finite number of states.

• To ensure that only one transition from one state to another takes place during one clock
cycle, the flip-flops have to be edge-triggered type.

Figure 1: General Form of a Sequential Circuit

 The combinational logic that provides input signals to flip-flops derives its inputs from two sources:
the primary inputs (w) and the current outputs of the flip-flops (Q). Thus, changes in state depend on
both the present state and the values of the primary inputs.

Although the outputs always depend on the present state, they do not necessarily have to depend
directly on the primary inputs. Thus, the connection shown in dashed line in the figure may or may not
exist.
• Sequential circuits whose outputs depend only on the state of the circuit are known as Moore
Type FSM.
• Sequential circuits whose outputs depend on both the state and the primary inputs are
referred to as Mealy Type FSM.

4. Basic Design Steps for Moore-Type FSMs

Problem Statement: Designing a Counter Using Flip-Flops

Design a mod-8 counter using T-type flip-flops. The circuit has one input w, which can have a value of 0 or
1 respectively. If w=0, the counter must stop at the current state. When w=1, the counter must work
normally and move to next step upon receiving the clock edge. The output z will be 1 only when reaching
the last number in the counting sequence, and 0 elsewhere.

Step 1: Identifying Inputs, Outputs, and Control Signals

1. The circuit has one input, w and one output, z.
2. The T flip-flops are edge-triggered, and all changes in the circuit occur on the positive edge of a
clock signal.
3. In order to observe the state transition, the outputs of flip-flops are considered as observation
outputs.

Step 2: Designing the State Diagram

1. The circuit counts from 0 up to 7, then repeats (i.e., after count value 7, next count is 0). The
output Z is equal to 1 if the present state is 7. Otherwise, the value of Z is equal to 0. From this
specification, it is apparent that the output Z depends only on state (i.e., 1 only in state when
count value is 7).
2. Each count represents a state in the FSM and the counts (8 = 23) appear as a sequence of
outputs of three T-type flip-flops (Y2 , Y1 and Y0) at time steps corresponding to the clock.
3. Let the counts (000 to 111) be referred by names A to H.
4. A good way to begin drawing the state diagram, shown in Figure 2, is to select one particular
state as a starting state; this is the state that the circuit should enter when the power is first
turned on, or when a reset signal is applied. For the given example, assuming that the starting
state is called state A, 000.
 5. In a state diagram, states are represented by circles and inside the circle, name of the state
and the value of output (Z) in that state is written, i.e. A/Z=0. For all the states B to G, Z=0 and,
H/Z=1.
6. As long as input w = 0, circuit need not do anything, and so each active clock edge should result
in the circuit remaining in same state. This is represented by an arrow starting and ending in
the same state.
7. When w = 1, the machine should recognize this, and move to a different state, for example from
state A to state B and so on.

Complete the Following State Diagram of a Mod-8 Counter:

Figure 2: State Diagram of a Mod-8 Counter

Step 3: Designing the State Table

It is convenient to translate the information contained in the state diagram into a tabular form. Table 1
shows the state table for the example sequential circuit.

Complete the Following State Table of a Mod-8 Counter:

Table 1: State Table for Mod-8 Counter

Next State
Present State Output Z
w=0 w=1

A A B 0

B B C 0

C C D 0

D D E 0
Note that the output Z is specified with respect to the present state, namely the state that the circuit is
in at present time. Note also that the Reset input was not included; instead, an implicit assumption
was made that the first state in the table is the starting state.

Step 4: Choosing the Flip-Flops

In designing circuits, the output signal required is given and the inputs necessary to create these outputs
are to be found. The excitation tables list the input conditions necessary to cause all possible output
transitions of the flip-flop. The excitation table for the D, JK and T flip-flops is as shown in Tables 2, 3
and 4, respectively. The variable Qt represents the Q output prior to the declaration of the Clk input (i.e.
present state) and Qt+1 is the output after Clk has been declared (i.e. next state).

Table 2: D Flip-Flop Table 3: JK Flip-Flop Table 4: T Flip-Flop

Excitation Tables

Step 5: Deriving the T-Inputs Using Excitation Table

As T flip-flop is given in the specification of design, inputs T2 T1 T0 necessary to create the next state
outputs can be derived from the excitable table of T flip-flop.

Complete the Following Table with the T Values of Respective Flip-Flops:

Table 5: Derivation of T-Inputs

Step 6: Deriving the Expressions for T-Inputs and Output Z
• Consider the Present state values Y2Y1Y0 and w as variables and construct three K-Maps for the
variables T2 , T1 and T0.

Derive the Expressions for T2 , T1 ,T0 and Z:

K-Map for T2 K-Map for T1

T2 = T1 =

K-Map for T0 K-Map for Z

T0 = Z=
Student Name: Date:
Student ID:

Lab Exercise # 9

Problem Statement:
Implement the Problem Statement illustrated in the experiment description.

Procedure:
1. Implement the circuit designed in Figure 3 as schematic capture.
2. Create a new Block Diagram/Schematic File → Save As → lab9.bdf
3. Double-Click on the empty screen to enter a new symbol → select T Flip-Flop by either
i. Expanding the hierarchy in the c:/altera/13.1/quartus/libraries box →
Primitives → Storage → TFF → Ok.
ii. Typing TFF in the space specified for the symbol name → Ok.
4. Make all the necessary connections.
5. Save then Analyze and Synthesize the file to make sure that there are no errors.
6. Compile the file.
7. Perform a Functional Simulation to test the behavior of your design based on the state diagram
(Figure 2) to show the correct functionality of the design.
• Change w (0 or 1) alternatively and check for every clock pulse, whether the
output (Y2Y1Y0) remains the same or counts up (as shown in Table 5, columns 2
and 3).
8. To download your design to Altera DE2-115 Board to and check its functionality correctness, you
will need to add the LFC symbol, which will provide control over the Clk signal using a Push
Button (PB).
9. Your instructor will provide you with the LFC symbol, or LFC Verilog code, for which you will
have to create a symbol (refer to Section 3.5 in Lab Session#1).
10. Place the LFC symbol in the same Block Diagram/Schematic design file where you have the TFF
symbols connected.
11. Connect the Clk through LFC circuit. Now, the clock is generated by the LFC block, which is
triggered by the Push Button (PB).
12. Save your new design with a different name. Note that you cannot use the new design (with the
LFC symbol) to perform functional simulation. The LFC symbol is added only when downloading
your design to Altera DE2-115 Board.
13. Analyze and synthesize your design for the implemented circuit (refer to Section 3.2.5 in Lab
Session#1).
14. Compile your design.
15. Prepare the following pin assignment table using the pin configuration datasheet.
 Table 3: Pin Assignment

Input Selected DE2-115 Output Selected DE2-115

Signal Switch Cyclone IV E Pin Signal LED Cyclone IV E Pin
Pin
w SW0 LEDG2
PB KEY0 LEDG1
Clock CLOCK_50 LEDG0

16. Fit, Analyze and download the design into Cyclone IV E FPGA on Altera DE2-115 Board.
17. Compile your design AGAIN.
18. Program and configure the FPGA to test the implemented design physically using switches and
LEDs.
19. Test your downloaded design based on the state diagram (Figure 2) to show the correct
functionality of the design.

20. Print your design files and simulation waveforms.

Ask your engineer to check your results, write his/her comments and sign below:

………………………………………………………………………………………………………………………...…………………………...……….
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…………………………………………………………………………………………………………………...…………………………………………

Engineer Signature
……..……………..

Attachments:
Please attach with the lab exercise sheet printouts of the files indicated below. Don't forget to
write your Name and ID Number as comments in every file before printing.

1. Graphical design file without Pin Assignment (*.bdf file)

2. Waveform file (*.sim.vwf file)
3. Graphical design file with Pin Assignment (*.bdf file)