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What Are The Basic Components in A Microprocessor

The basic components in a microprocessor are address lines to refer to memory locations, data lines for data transfer, and integrated circuit chips for processing data. The five stages in a DLX pipeline are instruction fetch, instruction decode, execute, memory access, and write back. For a pipeline with n stages, the ideal throughput is one instruction per cycle, but pipeline hazards like structural, data, and control hazards can prevent achieving this ideal throughput.

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Mobin Akhtar
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57 views

What Are The Basic Components in A Microprocessor

The basic components in a microprocessor are address lines to refer to memory locations, data lines for data transfer, and integrated circuit chips for processing data. The five stages in a DLX pipeline are instruction fetch, instruction decode, execute, memory access, and write back. For a pipeline with n stages, the ideal throughput is one instruction per cycle, but pipeline hazards like structural, data, and control hazards can prevent achieving this ideal throughput.

Uploaded by

Mobin Akhtar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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What are the basic components in a

Microprocessor?
1,address lines to refer the addresse of a block.
2,data lines for data transfer.
3,ic chips 4processingdata.

What are the five stages in a DLX pipeline?

5 stages in DLX pipeling:


1. Instruction Fetch.
2. Instruction Decode.
3. Execute.
4. Memory Access and
5. Write Back.

For a pipeline with ?n? stages, what?s the ideal


throughput? What prevents us from achieving this
ideal throughput?
Instruction Time/n
Pipeline Hazardsstructural, data,control
What are the different hazards? How do you avoid
them?

1. Structural Hazards: It arise from resource conflicts when the hardware cannot support
all possible combinations of instructions simultaniously in ovelapped execution.

2. Data Hazards: It arise when an instruction depends on the results of previous


instruction in a way that is exposed by the ovelapping of instructions in the pipeline.

3. Control Hazards: It arise from the pipelining of branches and other instructions that
change the PC.

How to Avoid Hazards:

1. Structural Hazard: This arise when some functional unit is not fully pipelined. Then the
sequence of instructions using that unpipelined unit cannot proceed at the rate of one
one per clock cycle. Another common way that it may appear is when some resources are
not duplicated enough to allow all combination of instructionsin the pipeline to execute.
So by fully pipelining the stages and duplicating resouces will avoid structural pipeline.

2. Data Hazards: A major effect of pipelining is to change the relative timing of


instructions by overlapping their execution. This overlap introduce the data and control
hazards. Data hazards occur when the pipeline changes the order of read/write accesses
to operands so that the order differs from the order seen by sequentially executing
instructions on an unpipelined processor. It can be mimimized by simple hardware
technique called forwarding or by adding stalls.

3. Control Hazards: They are also know as Branch Hazards. The simplest scheme to
handle branches hazard is to freeze or flush the pipeline, holding or deleting any
instructions after the branch until the branch destination is known. In this case branch
penalty is fixed and cannot be reduced by software. The other scheme is predicted-not-
taken or predicted-untaken and delayed branch.

What is MESI?
What?s the difference between Write-Through and
Write-Back Caches? Explain advantages and
disadvantages of each.

Convert 65(Hex) to Binary?

How many types of memory in computer


architecture?

Convert 65(Hex) to Binary.

Instead of just 5-8 pipe stages why not have, say, a


pipeline with 50 pipe stages?

What are the different hazards? How do you avoid


them?
Cache Size is 64KB, Block size is 32B and the cache
is Two-Way Set Associative. For a 32-bit physical
address, give the division between Block Offset,
Index and Tag.

64k/32 = 2000 blocks


2 way set assoc- 2000/2 = 1000 lines-> 10 bits for index
32B block-> 5 bits for block offset
32-10-5= 17 bits for tag

What is Cache Coherency?

Cache coherence refers to the integrity of data stored in local caches of a shared
resource. Cache coherence is a special case of memory coherence. When clients in a
system, particularly CPUs in a multiprocessing system cache occurs.

what is the difference between interrupt service


routine and subroutine ?

What is a Snooping cache?


Snooping is the process where the individual caches monitor address lines for accesses to
memory locations that they have cached. When a write operation is observed to a
location that a cache has a copy of, the cache controller invalidates its own copy of the
snooped memory location.

Snarfing is where a cache controller watches both address and data in an attempt to
update its own copy of a memory location when a second master modifies a location in
main memory

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