CY7C65219

Dock Management Controller (DMC)

General Description
The CY7C65219-40LQXI Dock Management Controller (DMC) is a USB Billboard controller that is designed for managing USB dock
and monitor solutions. The DMC provides USB full-speed capability to support USB Billboard device class v1.21. It supports signed
and unsigned firmware download over USB to programmable dock components (such as USB PD Controller and Hub controller)
connected to the DMC. DMC uses Cypress’ proprietary M0S8 technology with a 32-bit, 48-MHz Arm® Cortex® -M0 processor with
128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, and a Crypto engine for authentication. DMC provides
system-level ESD protection. DMC is available in a 40-QFN package.

Features Power
■ 2.7 V to 5.5 V operation
Dock Management Controller
■ USB Billboard device class v1.21 support ■ Independent supply voltage pin for GPIO that allows 1.71 V to
5.5 V signaling on the I/Os
■ Firmware update support and status reporting for DMC and all
programmable dock components ■ Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA
32-bit MCU Subsystem System-Level ESD Protection
■ 48-MHz Arm Cortex-M0 CPU ■ On DPLUS and DMINUS pins
■ 128-KB Flash ■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
■ 8-KB SRAM on IEC61000-4-2 level 4C

Integrated Digital Blocks Packages

■ Hardware Crypto block enables Authentication ■ 40-pin QFN for Docks/monitors
■ Full-Speed USB Device Controller supporting Billboard Device
■ Supports industrial temperature range (–40 °C to +85 °C)
Class
■ Integrated timers and counters
■ Four run-time reconfigurable serial communication blocks
(SCBs) with reconfigurable I2C, SPI, or UART functionality
Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock

Logic Block Diagram

DMC: Dock Management Controller

MCU Subsystem Integrated Digital Blocks I/O Subsystem
Advanced High-Performance Bus (AHB)

4x TCPWM
Programmable
I/O Matrix

CORTEX-M0 4x SCB GPIO

48 MHz (I2C, SPI, UART) Port

Crypto Block

Flash
(128KB)

System Full-Speed USB

SRAM Resources Device Controller
(8KB)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-20954 Rev. *A Revised December 22, 2017
 CY7C65219

Contents
DMC Block Diagram ......................................................... 4 Device-Level Specifications ...................................... 13
Functional Overview ........................................................ 5 Digital Peripherals ..................................................... 15
CPU and Memory Subsystem ..................................... 5 System Resources .................................................... 17
Crypto Block ................................................................ 5 Ordering Information...................................................... 20
Firmware Update Support ........................................... 5 Ordering Code Definitions ......................................... 20
Full-Speed USB Subsystem........................................ 5 Packaging........................................................................ 21
Integrated Billboard Device ......................................... 5 Acronyms ........................................................................ 22
Peripherals .................................................................. 5 Document Conventions ................................................. 23
GPIO ........................................................................... 6 Units of Measure ....................................................... 23
Pinouts .............................................................................. 7 References and Links to Applications Collaterals ..... 24
Available Firmware and Software Tools......................... 9 Document History Page ................................................. 25
EZ-PD Dock DMC Configuration Generation Tool ...... 9 Sales, Solutions, and Legal Information ...................... 26
DMC Programming ......................................................... 10 Worldwide Sales and Design Support....................... 26
Programming the Device Flash over SWD Interface. 10 Products .................................................................... 26
Application Firmware Update over USB Interface..... 10 PSoC® Solutions ...................................................... 26
Applications .................................................................... 11 Cypress Developer Community................................. 26
Electrical Specifications ................................................ 12 Technical Support ..................................................... 26
Absolute Maximum Ratings....................................... 12

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DMC Block Diagram

Figure 1. DMC Block Diagram[1]

CPU Subsystem
DMC
SWD/TC SPCIF
Cortex
32-bit FLASH SRAM ROM
M0
128 KB 8 KB 8 KB
48 MHz
AHB-Lite FAST MUL
Read Accelerator SRAM Controller ROM Controller
NVIC, IRQMX
System Resources
Lite
System Interconnect (Single Layer AHB)
Power
Sleep Control Peripherals
WIC
POR REF
PWRSYS
PCLK Peripheral Interconnect (MMIO)

Clock
Clock Control
WDT USB-FS
IMO ILO
IOSS GPIO (3 x ports)

4 x TCPWM

CRYPTO
4 x SCB
Reset
Reset Control
XRES

Test
DFT Logic
DFT Analog

FS-PHY
Power Modes High Speed I/O Matrix
Active/Sleep
Deep Sleep
20 x GPIOs

I/O Subsystem

Note
1. See Acronyms section for more details.

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Functional Overview
CPU and Memory Subsystem Firmware Update Support
CPU DMC has the capability to do firmware update to itself and other
dock components such as USB PD Controller and Hub
The Cortex-M0 CPU in DMC is part of the 32-bit MCU Controller. It implements the firmware update functionality and
subsystem, which is optimized for low-power operation with status reporting on a vendor interface using a full-speed USB 2.0
extensive clock gating. It mostly uses 16-bit instructions and device controller. DMC gets the firmware update request and
executes a subset of the Thumb-2 instruction set. This enables firmware content through the USB interface from the host. DMC
fully compatible binary upward migration of the code to higher communicates with dock components using SCB.
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation Unsigned Firmware Update
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC) The firmware update procedure expects the host to send the
block with 32 interrupt inputs and also includes a Wakeup metadata of the programmable component's FW information.
Interrupt Controller (WIC). The WIC can wake the processor up This metadata includes SHA-256 of the individual firmware
from the Deep Sleep mode, allowing power to be switched off to image. DMC notifies the host to send the individual component's
the main processor when the chip is in the Deep Sleep mode. firmware image one by one and update to the dock component
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) connected to DMC through SCB. DMC verifies the firmware
input, which is made available to the user when it is not in use validity by comparing the received SHA-256 with the calculated
for system functions requested by the user. SHA-256 of the firmware received.

The CPU also includes a serial wire debug (SWD) interface, Signed Firmware Update
which is a two-wire form of JTAG. The debug configuration used The signed firmware update follows the same procedure as the
for DMC has four break-point (address) comparators and two unsigned firmware update but it uses RSA-2048/SHA-256 for
watchpoint (data) comparators. signing.
Flash Contact Cypress customer support for more information on the
The DMC device has a flash module with two banks of 64 KB signed firmware update.
flash, a flash accelerator, tightly coupled to the CPU to improve Refer to the EZ-PD™ Dock Reference Design Guide for more
average access times from the flash block. The flash block is details.
designed to deliver 1 wait-state (WS) access time at 48 MHz and
with 0-WS access time at 24 MHz. The flash accelerator delivers Peripherals
85% of single-cycle SRAM access performance on average.
Serial Communication Blocks (SCB)
SROM
DMC has four SCBs, which can be configured to implement an
A supervisory ROM that contains boot and configuration routines I2C, SPI, or UART interface. The hardware I2C blocks implement
is provided. full multi-master and slave interfaces capable of multimaster
arbitration. In the SPI mode, the SCB blocks can be configured
Crypto Block to act as master or slave.
DMC integrates a crypto block for hardware assisted In the I2C mode, the SCB blocks are capable of operating at
authentication of firmware images. The DMC Crypto block speeds of up to 1 Mbps (Fast Mode Plus) and have flexible
provides cryptography functionality. It includes hardware buffering options to reduce interrupt overhead and latency for the
acceleration blocks for Advanced Encryption Standard (AES) CPU. These blocks also support I2C that creates a mailbox
block cipher, Secure Hash Algorithm (SHA-1 and SHA-2), Cyclic address range in the memory of DMC and effectively reduce I2C
Redundancy Check (CRC), and pseudo random number communication to reading from and writing to an array in
generation. memory. In addition, the blocks support 128-deep FIFOs for
receive and transmit which, by increasing the time given for the
Full-Speed USB Subsystem
CPU to read data, greatly reduce the need for clock stretching
The FSUSB subsystem contains a full-speed USB device caused by the CPU not having read data on time.
controller as described in the Integrated Billboard Device
section. The I2C peripherals are compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
■ USB2.0 Full-Speed (FS) PHY with integrated 5.0 V to 3.3 V I2C-bus specification and user manual (UM10204).
regulator
The I2C bus I/Os are implemented with GPIO in open-drain
■ 8-kV IEC ESD Protection on the following pins: DP, DM modes.

Integrated Billboard Device

DMC integrates a complete full-speed USB 2.0 device controller
capable of functioning as a Billboard class device. The USB 2.0
device controller can also support other device classes.

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The I2C port on SCB 1-3 blocks of DMC are not completely GPIO
compliant with the I2C specification in the following aspects:
DMC has up to 20 GPIOs (these GPIOs can be configured for
2 GPIOs and SCB) and SWD pins, which can also be used as
■ The GPIO cells for SCB 1's I C port are not overvoltage-tolerant
GPIOs. The I2C pins from SCB 0 are overvoltage-tolerant.
and, therefore, cannot be hot-swapped or powered up
independently of the rest of the I2C system. The GPIO block implements the following:
■ Seven drive strength modes:
■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of
❐ Input only
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
❐ Weak pull-up with strong pull-down
VOL maximum of 0.6 V.
❐ Strong pull-up with weak pull-down
■ Fast-mode and Fast-mode Plus specify minimum Fall times, ❐ Open drain with strong pull-down
which are not met with the GPIO cell; Slow strong mode can ❐ Open drain with strong pull-up
help meet this spec depending on the bus load. ❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
Timer/Counter/PWM Block (TCPWM)
■ Input threshold select (CMOS or LVTTL)
DMC has four TCPWM blocks. Each implements a 16-bit timer,
counter, pulse-width modulator (PWM), and quadrature decoder ■ Individual control of input and output buffer enabling/disabling
functionality. in addition to the drive strength modes
■ Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
■ Selectable slew rates for dV/dt related noise control to improve
EMI
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.

Table 1. DMC Power Modes

Mode Description
Power is Valid and XRES is not asserted. An internal reset source is asserted or SleepController
RESET
is sequencing the system out of reset.
ACTIVE Power is Valid and CPU is executing instructions.
Power is Valid and CPU is not executing instructions. All logic that is not operating is clock gated
SLEEP
to save power.
Main regulator and most hard-IPs are shut off. Deep Sleep regulator powers logic, but only
DEEP SLEEP
low-frequency clock is available.

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Pinouts
Table 2. DMC Pin Description for 40-QFN Device
Pin Map Name Description
40-QFN
1 NC NC
2 NC NC
3 NC NC
4 NC NC
5 NC NC
6 NC NC
7 P1.0 GPIO/UART_2_TX / SPI_2_MISO
8 P1.1 GPIO/UART_2_RX / SPI_2_SEL
GPIO/UART_0_RX/ UART_3_CTS/ SPI_3_MOSI/
9 P1.2
I2C_3_SCL
GPIO/UART_0_TX/ UART_3_RTS/ SPI_3_CLK/
10 P1.3
I2C_3_SDA
11 P1.6 GPIO / UART_1_TX / SPI_1_MISO
12 P1.4 GPIO / UART_3_TX/ SPI_3_MISO/ SWD_1_CLK
13 P1.5 GPIO / UART_3_RX/ SPI_3_SEL/ SWD_1_DAT
14 P1.7 GPIO / UART_1_RX / SPI_1_SEL
GPIO / UART_1_CTS / SPI_1_CLK/ I2C_1_SCL /
15 P2.0
SWD_0_DAT
GPIO / UART_1_RTS / SPI_1_MOSI/ I2C_1_SDA /
16 P2.1
SWD_0_CLK
17 VDDD VDDD supply Input / Output (2.7 V–5.5 V)
1.71 V–5.5 V supply for I/Os. This supply also powers the
18 VDDIO
global analog multiplex buses.
19 VCCD 1.8-V regulator output for filter capacitor
20 VSYS System power supply (2.7 V–5.5 V)
21 DPLUS USB 2.0 DP
22 DMINUS USB 2.0 DM
23 P2.4 GPIO
24 P2.5 GPIO / UART_0_TX/ SPI_0_MOSI
25 P2.6 GPIO / UART_0_RX/ SPI_0_CLK
26 XRES External Reset Input. Internally pulled-up to VDDIO.
I2C_0_SDA / GPIO_OVT / UART_0_CTS / SPI_0_SEL/
27 P0.0
TCPWM0
I2C_0_SCL / GPIO_OVT / UART_0_RTS / SPI_0_MISO/
28 P0.1
TCPWM1
29 NC NC
30 NC NC
31 NC NC
32 NC NC
33 VSS Ground Supply (GND)

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Table 2. DMC Pin Description for 40-QFN Device (continued)

Pin Map Name Description
40-QFN
34 P3.2 GPIO / TCPWM0
35 P3.3 GPIO / TCPWM1
GPIO / UART_2_CTS / SPI_2_MOSI/ I2C_2_SDA /
36 P3.4
TCPWM2
37 P3.5 GPIO / UART_2_RTS / SPI_2_CLK/ I2C_2_SCL / TCPWM3
38 P3.6 GPIO
39 NC NC
40 NC NC

Figure 2. Pinout of 40-QFN Package (Top View)

GPIO
GPIO
GPIO
GPIO
GPIO
GND
NC
NC

NC
NC
40
39
38
37
36
35
34
33
32
31
NC 1 30 NC
NC 2 29 NC
NC 3 28 GPIO_OVT
NC 4 27 GPIO_OVT
NC 5 26 XRES
EPAD
NC 6 25 GPIO
GPIO 7 24 GPIO
GPIO 8 23 GPIO
GPIO 9 22 DMINUS
GPIO 10 21 DPLUS
11
12
13
14
15
16
17
18
19
20
VSYS
VDDD

VCCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO

VDDIO

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Available Firmware and Software Tools

EZ-PD Dock DMC Configuration Generation Tool
The EZ-PD Dock DMC Configuration Generation Tool can be used to update DMC images with the modified configuration. It allows
configuring the dock topology to manage and do firmware update to programmable dock components connected to DMC.

EZ-PD Dock Image Creation Tool

The EZ-PD Dock Image Creation Tool is used to create a single combined firmware image file, referred to as the composite dock
image from firmware files of components present in the dock. This composite image is used for firmware update to be used by EZ-PD
Dock Firmware Update Tool.

EZ-PD Dock Firmware Update Tool

The EZ-PD Dock Firmware Update Tool is a WinUSB-based application that runs on Windows systems. This tool updates firmware
for devices in the dock and reports the final consolidated status. It takes the files generated using the EZ-PD Dock Image Creation
Tool as the input and initiates a firmware update.
You can download the EZ-PD Dock DMC Configuration Generation Tool, EZ-PD Dock Image Creation Tool, EZ-PD Dock Firmware
Update Tool and its associated documentation at the following link:
http://www.cypress.com/documentation/reference-designs/ez-pd-ccg4-usb-type-c-monitordock-solution

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DMC Programming well as debug firmware. The flash is programmed by

downloading the information from a hex file. This hex file is a
There are two ways to program application firmware into a DMC binary file generated as an output of building the firmware project
device: in PSoC Creator Software. Click here for more information on
1. Programming the device flash over SWD Interface how to use the MiniProg3 programmer. There are many
third-party programmers that support mass programming in a
2. Application firmware update over an USB interface manufacturing environment.
Generally, the DMC device is programmed over the SWD As shown in the block diagram in Figure 3, the SWD_0_DAT and
interface only during development or during the manufacturing SWD_0_CLK pins are connected to the host programmer's
process of the end product. Once the end product is manufac- SWDIO (data) and SWDCLK (clock) pins respectively. During
tured, the DMC device's application firmware can be updated via SWD programming, the device can be powered by the host
the USB interface running on the alternate application image. programmer by connecting its VTARG (power supply to the
target device) to VSYS pin of the DMC device. If the DMC device
Programming the Device Flash over SWD Interface is powered using an on-board power supply, it can be
The DMC device can be programmed using the SWD interface. programmed using the “Reset Programming” option.
Cypress provides a programming kit (CY8CKIT-002 MiniProg3
Kit) called MiniProg3, which can be used to program the flash as
Figure 3. Connecting the Programmer to DMC Device
3.0 V
VDD

Host Programmer DMC

VCCD 1F
10V
VDD VSYS X7R

SWDCLK SWD_0_CLK
SWDIO SWD_0_DAT VDDD 1F
10V
XRES XRES
X7R
VDDIO
GND VSS
GND

Application Firmware Update over USB Interface

The application firmware provided by Cypress for all DMC applications have dual images. Application firmware can only be updated
using other copy of application firmware over the USB vendor interface that binds to the Microsoft WinUSB driver. This allows fail-safe
update of the alternate image while executing from the current image. For more information, refer to the EZ-PD Dock Reference
Design Guide.
In this application, the firmware update can be performed over the D+/D- lines (USB2.0) as shown in Figure 4.
Figure 4. Application Firmware Update

PC D+/D-
Running
DMC
EZ-PD Dock
Firmware Update Tool

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Applications
Figure 5 illustrates the application diagram of a dock/monitor I2C interface) and GPIOs. DMC communicates with the PD
using a DMC device. In this application, DMC is used as controller and Hub controller and provides their status. It also
Billboard and Firmware Update device for all programmable enables firmware update over the SCB interface.
dock components. More details including the schematic of the EZ-PD Dock
A typical dock/monitor application also includes a PD controller Reference Design can be found here.
for Type-C ports and Hub for port expansion. DMC is connected
to the PD controller and Hub controller through SCB (in this case
Figure 5. Dock/Monitor Application Diagram (40-QFN Device)
VDDD

2.2K 2.2K 2.2K

28
I2C_SCL / P0.1 1, 2, 3, 4, 5, 6, 29, VDDD
NC
27 30, 31, 32, 39, 40
I2C EEPROM I2C_SDA / P0.0
for Tier-2 HX3
23 2.2K 2.2K 2.2K
WP P2.4
9
38 I2C_SCL / P1.2
P3.6 10
Tier-2 HX3 PD Controller
I2C_SDA / P1.3
XRES
3.3V 34
20 P3.2 HPI INTR
VSYS
1F 0.1F 1F
10V 10V 10V
GPIO 11, 12, 13, 14, 15,
16, 24, 25
3.3V
17 CY7C65219-40LQXIT
VDDD
1F 0.1F 1F 18 40QFN
VDDIO
10V 10V 10V

VDDD 21
DPLUS
22
DMINUS
2.2K 2.2K 2.2K
37
I2C_SCL / P3.5
35
I2C EEPROM 36 P3.3 Dock Master Reset
I2C_SDA / P3.4
for Tier-2 HX3
8
WP P1.0
7 26
XRES
P1.1
Tier-2 HX3 33 0.1F
XRES
GND 10V
VCCD
X7R
19
1F
10V
X7R

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Electrical Specifications
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings

Parameter Description Min Typ Max Units Details/Conditions

VSYS_MAX Digital supply relative to VSS –0.5 – 6 V Absolute max

VDDIO_MAX Max supply voltage relative to VSS – – 6 V
VGPIO_ABS GPIO voltage –0.5 – VDDIO + 0.5 V
VGPIO_OVT_ABS OVT GPIO voltage –0.5 – 6 V
IGPIO_ABS Maximum current per GPIO –25 – 25 mA
GPIO injection current, Max for VIH >
IGPIO_INJECTION –0.5 – 0.5 mA Absolute max, current injected per pin
VDDD, and Min for VIL < VSS
Electrostatic discharge human body
ESD_HBM 2200 – – V –
model
Electrostatic discharge charged
ESD_CDM 500 – – V –
device model
LU Pin current for latch-up –100 – 100 mA Tested at 125 °C
Contact discharge on DPLUS, DMINUS
ESD_IEC_CON Electrostatic discharge IEC61000-4-2 8000 – – V
pins
ESD_IEC_AIR Electrostatic discharge IEC61000-4-2 15000 – – V Air discharge for DPLUS, DMINUS pins

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Device-Level Specifications
All specifications are valid for –40 °C  TA  105 °C and TJ  120 °C, except where noted.
Table 4. DC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID.PWR#1 VSYS – 2.7 – 5.5 V
SID.PWR#13 VDDIO I/O supply voltage 1.71 – 5.5[2] V 2.7 V < VDDD < 5.5 V
SID.PWR24 VCCD Output voltage for core Logic – 1.8 – V –
From VSYS
TA = 25 °C / VSYS = 5 V, TA = 25 °C
SID.PWR#4 IDD Supply current – 25 – mA FS USB, no I/O sourcing current,
2 SCBs at 1 Mbps, CPU at 24
MHz.
USB configured, USB Regulator
SID.PWR#1_B VSYS Power supply for USB operation 4.5 – 5.5 V
enabled
USB configured, USB Regulator
SID.PWR#1_C VSYS Power supply for USB operation 3.15 – 3.45 V
disabled
External regulator voltage bypass for
SID.PWR#15 Cefc 1 1.3 1.6 µF X5R ceramic or better
VCCD
Power supply decoupling capacitor
SID.PWR#16 Cexc 0.8 1 – µF X5R ceramic or better
for VSYS
Sleep Mode. VSYS = 2.7 V to 5.5 V. Typical values measured at VDD = 3.3 V and TA = 25 °C.
VSYS = 3.3 V, TA = 25 °C, All
WDT wakeup on. blocks except CPU are on, USB
SID25A IDD20A – 3.5 – mA
IMO at 48 MHz. in Suspend Mode, no I/O sourcing
current
Deep Sleep Mode
VSYS = 3.0 to 3.6 V. CC Attach, I2C, Power Source = VSYS, I2C and
SID_DS IDD_DS – 30 – µA
WDT Wakeup on. WDT enabled for Wakeup.
XRES Current
Supply current while XRES asserted.
This does not include current drawn Power Source = VSYS = 3.3 V,
SID307 IDD_XR – 30 – µA
due to the XRES internal pull-up TA = 25 °C
resistor.

Table 5. AC Specifications (Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.CLK#4 FCPU CPU input frequency DC – 48 MHz All VDDD
SID.PWR#20 TSLEEP Wakeup from sleep mode – 0 – µs –
SID.PWR#21 TDEEPSLEEP Wakeup from Deep Sleep mode – – 35 µs –
SID.XRES#5 TXRES External reset pulse width 5 – – µs All VDDIO

Note
2. If VDDIO > VDDD, GPIO P2.4 cannot be used. It must be left unconnected. See Table 2 for pin numbers.

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I/O
Table 6. I/O DC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID.GIO#37 VIH_CMOS Input voltage HIGH threshold 0.7 × VDDIO – – V CMOS input
SID.GIO#38 VIL_CMOS Input voltage LOW threshold – – 0.3 × VDDIO V CMOS input
SID.GIO#39 VIH_VDDIO2.7- LVTTL input, VDDIO < 2.7 V 0.7× VDDIO – – V –
SID.GIO#40 VIL_VDDIO2.7- LVTTL input, VDDIO < 2.7 V – – 0.3 × VDDIO V –
SID.GIO#41 VIH_VDDIO2.7+ LVTTL input, VDDIO  2.7 V 2.0 – – V –
SID.GIO#42 VIL_VDDIO2.7+ LVTTL input, VDDIO  2.7 V – – 0.8 V –
SID.GIO#33 VOH_3V Output voltage HIGH level VDDIO–0.6 – – V IOH = 4 mA at 3-V VDDIO
SID.GIO#34 VOH_1.8V Output voltage HIGH level VDDIO–0.5 – – V IOH = 1 mA at 1.8-V VDDIO
SID.GIO#35 VOL_1.8V Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V VDDIO
IOL = 4 mA at 3-V VDDIO
SID.GIO#36 VOL_3V Output voltage LOW level – – 0.6 V
for SBU and AUX pins
SID.GIO#5 RPU Pull-up resistor value 3.5 5.6 8.5 k +25 °C TA, all VDDIO
SID.GIO#6 RPD Pull-down resistor value 3.5 5.6 8.5 k +25 °C TA, all VDDIO
+25 °C TA, all VDDIO.
Input leakage current
SID.GIO#16 IIL – – 2 nA Guaranteed by
(absolute value)
characterization.
All VDDIO, all packages, all
SID.GIO#17 CPIN Max pin capacitance – 3.0 7 pF I/Os. Guaranteed by
characterization.
Input hysteresis, LVTTL Guaranteed by
SID.GIO#43 VHYSTTL 15 40 – mV
VDDIO  2.7 V characterization
VDDIO < 4.5 V. Guaranteed
SID.GIO#44 VHYSCMOS Input hysteresis CMOS 0.05 × VDDIO – – mV
by characterization.
Current through protection Guaranteed by character-
SID69 IDIODE – – 100 µA
diode to VDDIO/Vss ization
Maximum total sink chip Guaranteed by character-
SID.GIO#45 ITOT_GPIO – – 85 mA
current ization
OVT
Input current when Pad >
SID.GIO#46 IIHS – – 10.00 µA Per I2C specification
VDDIO for OVT inputs

Table 7. I/O AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID70 TRISEF Rise time in Fast Strong mode 2 – 12 ns 3.3 V VDDIO, Cload = 25 pF
SID71 TFALLF Fall time in Fast Strong mode 2 – 12 ns 3.3 V VDDIO, Cload = 25 pF

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XRES
Table 8. XRES DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Input voltage HIGH
SID.XRES#1 VIH_XRES 0.7 × VDDIO – – V CMOS input
threshold on XRES pin
Input voltage LOW
SID.XRES#2 VIL_XRES – – 0.3 × VDDIO V CMOS input
threshold on XRES pin
Input capacitance on Guaranteed by charac-
SID.XRES#3 CIN_XRES – – 7 pF
XRES pin terization
Input voltage hysteresis Guaranteed by charac-
SID.XRES#4 VHYSXRES – 0.05 × VDDIO – mV
on XRES pin terization

Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 9. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Fc max = CLK_SYS.
SID.TCPWM.3 TCPWMFREQ Operating frequency – – Fc MHz
Maximum = 48 MHz.
SID.TCPWM.4 TPWMENEXT Input trigger pulse width 2/Fc – – ns For all trigger events
Minimum possible width of
Overflow, Underflow, and CC
SID.TCPWM.5 TPWMEXT Output trigger pulse width 2/Fc – – ns
(Counter equals Compare
value) outputs
Minimum time between
SID.TCPWM.5A TCRES Resolution of counter 1/Fc – – ns
successive counts
Minimum pulse width of PWM
SID.TCPWM.5B PWMRES PWM resolution 1/Fc – – ns
output
Minimum pulse width between
SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc – – ns
quadrature-phase inputs

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 CY7C65219

I2C
Table 10. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID149 II2C1 Block current consumption at 100 kHz – – 60 µA –
SID150 II2C2 Block current consumption at 400 kHz – – 185 µA –
SID151 II2C3 Block current consumption at 1 Mbps – – 390 µA –
SID152 II2C4 I2C enabled in Deep Sleep mode – – 1.4 µA –

Table 11. Fixed I2C AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID153 FI2C1 Bit rate – – 1 Mbps –

Table 12. Fixed UART DC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Block current consumption at
SID160 IUART1 – – 125 µA –
100 Kbps
Block current consumption at
SID161 IUART2 – – 312 µA –
1000 Kbps

Table 13. Fixed UART AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID162 FUART Bit rate – – 1 Mbps –

Table 14. Fixed SPI DC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID163 ISPI1 Block current consumption at 1 Mbps – – 360 µA –
SID164 ISPI2 Block current consumption at 4 Mbps – – 560 µA –
SID165 ISPI3 Block current consumption at 8 Mbps – – 600 µA –

Table 15. Fixed SPI AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SPI Operating frequency (Master; 6X
SID166 FSPI – – 8 MHz –
oversampling)
Table 16. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID167 TDMO MOSI Valid after SClock driving edge – – 15 ns –
MISO Valid before SClock capturing Full clock, late MISO
SID168 TDSI 20 – – ns
edge sampling
Referred to slave capturing
SID169 THMO Previous MOSI data hold time 0 – – ns
edge

Document Number: 002-20954 Rev. *A Page 15 of 25

 CY7C65219

Table 17. Fixed SPI Slave Mode AC Specifications

(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
MOSI Valid before Sclock capturing
SID170 TDMI 40 – – ns –
edge
SID171 TDSO MISO Valid after Sclock driving edge – – 42 + 3 × TCPU ns TCPU = 1/FCPU
MISO Valid after Sclock driving edge
SID171A TDSO_EXT – – 48 ns –
in Ext Clk mode
SID172 THSO Previous MISO data hold time 0 – – ns –
SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 – – ns –

System Resources
Power-on-Reset (POR) with Brown Out SWD Interface
Table 18. Imprecise Power On Reset (PRES) (Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Power-on Reset (POR) rising trip
SID185 VRISEIPOR 0.80 – 1.50 V –
voltage
SID186 VFALLIPOR POR falling trip voltage 0.70 – 1.4 V –

Table 19. Precise Power On Reset (POR) (Guaranteed by Characterization)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Brown-out Detect (BOD) trip voltage
SID190 VFALLPPOR 1.48 – 1.62 V –
in active/sleep modes
SID192 VFALLDPSLP BOD trip voltage in Deep Sleep mode 1.1 – 1.5 V –

Table 20. SWD Interface Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SWDCLK 1/3 CPU clock
SID.SWD#1 F_SWDCLK1 3.3 V  VDDIO  5.5 V – – 14 MHz
frequency
SWDCLK 1/3 CPU clock
SID.SWD#2 F_SWDCLK2 1.8 V  VDDIO  3.3 V – – 7 MHz
frequency
Guaranteed by
SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns
characterization
Guaranteed by
SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns
characterization
Guaranteed by
SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK – – 0.50 × T ns
characterization
Guaranteed by
SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns
characterization

Document Number: 002-20954 Rev. *A Page 16 of 25

 CY7C65219

Internal Main Oscillator

Table 21. IMO DC Specifications
(Guaranteed by Design)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID218 IIMO1 IMO operating current at 48 MHz – – 1000 µA –

Table 22. IMO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Frequency variation at 24, 36, and
SID.CLK#13 FIMOTOL – – ±2 % –25 °C TA 85 °C, all VDDD
48 MHz (trimmed)
Guaranteed by
SID226 TSTARTIMO IMO start-up time – – 7 µs
characterization
Guaranteed by
SID229 TJITRMSIMO2 RMS jitter at 24 MHz – 145 – ps
characterization
SID.CLK#1 FIMO IMO frequency 24 – 48 MHz All VDDD

Internal Low-Speed Oscillator

Table 23. ILO DC Specifications
(Guaranteed by Design)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID231 IILO1 ILO operating current – 0.3 1.05 µA –
SID233 IILOLEAK ILO leakage current – 2 15 nA –

Table 24. ILO AC Specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Guaranteed by
SID234 TSTARTILO1 ILO start-up time – – 2 ms
characterization
Guaranteed by
SID238 TILODUTY ILO duty cycle 40 50 60 %
characterization
SID.CLK#5 FILO ILO frequency 20 40 80 kHz –

Table 25. VSYS Switch Specification

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Resistance from VSYS supply
Measured with a load current of 5 mA–10 mA
SID.vddsw.1 Res_sw input to the output supply – – 1.5 Ω
on VDDD.
VDDD

Document Number: 002-20954 Rev. *A Page 17 of 25

 CY7C65219

Memory
Table 26. Flash AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.MEM#3 FLASH_ERASE Row erase time – – 15.5 ms –
Row (Block) write time (erase
SID.MEM#4 FLASH_WRITE – – 20 ms –
and program)
SID.MEM#8 FLASH_ROW_PGM Row program time after erase – – 7 ms –
SID178 TBULKERASE Bulk erase time (64 KB) – – 35 ms –
SID180 TDEVPROG Total device program time – – 7.5 s Guaranteed by characterization
Flash retention, TA ≤ 55 °C,
SID182 FRET1 20 – – years Guaranteed by characterization
100 K P/E cycles
Flash retention, TA ≤ 85 °C,
SID182A FRET2 10 – – years Guaranteed by characterization
10 K P/E cycles
Flash retention, TA ≤ 105 °C,
SID182B FRET3 3 – – years Guaranteed by characterization
10 K P/E cycles

Document Number: 002-20954 Rev. *A Page 18 of 25

 CY7C65219

Ordering Information
Table 27 lists the DMC part numbers and features.
Table 27. DMC Ordering Information
Part Number Application Default FW Package Si ID
CY7C65219-40LQXIT Application launcher and 2 copies of
Docks/Monitors application FW that can update DMC 40-QFN 1D0A
CY7C65219-40LQXI as unsigned firmware update

Ordering Code Definitions

CY 7 C 65 219 - 40 LQ X I T
T = Tape and reel
Temperature Range: I = Industrial (-40 ºC to 85 ºC)
Lead: X = Pb-free
Package Type: LQ = QFN
Number of pins: 40 pins
Part Number
Family Code: 65
Technology Code: C = CMOS
Marketing Code: 7 = Cypress products
Company ID: CY = Cypress

Document Number: 002-20954 Rev. *A Page 19 of 25

 CY7C65219

Packaging
Table 28. Package Characteristics
Parameter Description Conditions Min Typ Max Units
TA Operating ambient temperature Industrial –40 25 85 °C
TJ Operating junction temperature Industrial –40 25 100 °C
TJA Package JA (40-pin QFN) – – – 17 °C/W
TJC Package JC (40-pin QFN) – – – 2 °C/W

Table 29. Solder Reflow Peak Temperature

Maximum Time within 5 °C of Peak
Package Maximum Peak Temperature Temperature
40-pin QFN 260 °C 30 seconds

Table 30. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package MSL
40-pin QFN MSL 3

Figure 6. 40-pin QFN Package Outline, 001-80659

001-80659 *A

Document Number: 002-20954 Rev. *A Page 20 of 25

 CY7C65219

Acronyms Table 31. Acronyms Used in this Document (continued)

Table 31. Acronyms Used in this Document Acronym Description

PGA programmable gain amplifier
Acronym Description
PHY physical layer
ADC analog-to-digital converter
POR power-on reset
AES advanced encryption standard
PRES precise power-on reset
AMBA (advanced microcontroller bus architecture)
AHB PSoC® Programmable System-on-Chip™
high-performance bus
API application programming interface PWM pulse-width modulator
ARM ®
advanced RISC machine, a CPU architecture RAM random-access memory
CPU central processing unit RISC reduced-instruction-set computing
cyclic redundancy check, an error-checking RMS root-mean-square
CRC
protocol RTC real-time clock
digital input/output, GPIO with only digital capabil- RX receive
DIO
ities, no analog. See GPIO.
SAR successive approximation register
electrically erasable programmable read-only
EEPROM SCB serial communication block
memory
EMI electromagnetic interference SCL I2C serial clock
ESD electrostatic discharge SDA I2C serial data
FS full-speed S/H sample and hold
GPIO general-purpose input/output SHA secure hash algorithm
IC integrated circuit Serial Peripheral Interface, a communications
SPI
protocol
IDE integrated development environment
SRAM static random access memory
I2C, or IIC Inter-Integrated Circuit, a communications protocol
SWD serial wire debug, a test protocol
ILO internal low-speed oscillator, see also IMO
TCPWM timer/counter pulse-width modulator
IMO internal main oscillator, see also ILO
TX transmit
IOSS input/output subsystem
a new standard with a slimmer USB connector and
I/O input/output, see also GPIO Type-C a reversible cable, capable of sourcing up to 100 W
LDO low-dropout regulator of power
LVD low-voltage detect Universal Asynchronous Transmitter Receiver, a
UART
communications protocol
LVTTL low-voltage transistor-transistor logic
USB Universal Serial Bus
MCU microcontroller unit
USB PD USB Power Delivery
MMIO memory mapped input/output
USB-FS USB Full-Speed
NC no connect
USB input/output, CCG2 pins used to connect to a
NMI nonmaskable interrupt USBIO
USB port
NVIC nested vectored interrupt controller VDM vendor defined messages
opamp operational amplifier XRES external reset I/O pin
PCB printed circuit board

Document Number: 002-20954 Rev. *A Page 21 of 25

 CY7C65219

Document Conventions
Units of Measure
Table 32. Units of Measure
Symbol Unit of Measure
°C degrees Celsius
Hz hertz
KB 1024 bytes
kHz kilohertz
k kilo ohm
Mbps megabits per second
MHz megahertz
M mega-ohm
Msps megasamples per second
µA microampere
µF microfarad
µs microsecond
µV microvolt
µW microwatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ns nanosecond
 ohm
pF picofarad
ppm parts per million
ps picosecond
s second
sps samples per second
V volt

Document Number: 002-20954 Rev. *A Page 22 of 25

 CY7C65219

References and Links to Applications Collaterals

Knowledge Base Articles
■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and ■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
CCG4 - KBA210740
■ AN210403 - Hardware Design Guidelines for Dual Role Port
■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™ Applications Using EZ-PD™ USB Type-C Controllers
CCG4 Using PSoC® Programmer and MiniProg3 - KBA96477
■ AN210771 - Getting Started with EZ-PD™ CCG4
■ CCGX Frequently Asked Questions (FAQs) - KBA97244
Reference Designs
■ Handling Precautions for CY4501 CCG1 DVK - KBA210560
■ EZ-PD™ CCG2 Electronically Marked Cable Assembly
■ Cypress EZ-PD™ CCGx Hardware - KBA204102 (EMCA) Paddle Card Reference Design
■ Difference between USB Type-C and USB-PD - KBA204033
■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
■ CCGx Programming Methods - KBA97271
■ CCG1 USB Type-C to DisplayPort Cable Solution
■ Getting started with Cypress USB Type-C Products -
KBA04071 ■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution
■ Type-C to DisplayPort Cable Electrical Requirements ■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
■ Dead Battery Charging Implementation in USB Type-C ■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle
Solutions - KBA97273 Card Reference Design
■ Termination Resistors Required for the USB Type-C Connector ■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card
– KBA97180 Reference Schematics
■ VBUS Bypass Capacitor Recommendation for Type-C Cable ■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle
and Type-C to Legacy Cable/Adapter Assemblies – KBA97270
■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
■ Need for Regulator and Auxiliary Switch in Type-C to
DisplayPort (DP) Cable Solution - KBA97274 ■ CCG2 20W Power Adapter Reference Design
■ Need for a USB Billboard Device in Type-C Solutions – ■ CCG2 18W Power Adapter Reference Design
KBA97146
■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference
■ CCG1 Devices in Type-C to Legacy Cable/Adapter Assemblies Design Kit
– KBA97145
■ EZ-PD Dock Reference Design
■ Cypress USB Type-C Controller Supported Solutions –
KBA97179 Kits
■ Termination Resistors for Type-C to Legacy Ports – KBA97272 ■ CY4501 CCG1 Development Kit
■ Handling Instructions for CY4502 CCG2 Development Kit – ■ CY4502 EZ-PD™ CCG2 Development Kit
KBA97916
■ CY4531 EZ-PD CCG3 Evaluation Kit
■ Thunderbolt™ Cable Application Using CCG3 Devices -
KBA210976 ■ CY4541 EZ-PD™ CCG4 Evaluation Kit
■ Power Adapter Application Using CCG3 Devices - KBA210975 Datasheets
■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974 ■ CCG1 Datasheet: USB Type-C Port Controller with Power
■ Device Flash Memory Size and Advantages - KBA210973 Delivery
■ Applications of EZ-PD™ CCG4 - KBA210739 ■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode
Controller on Type-C
Application Notes
■ CCG2: USB Type-C Port Controller Datasheet
■ AN96527 - Designing USB Type-C Products Using Cypress’s
CCG1 Controllers ■ CCG4: Two-Port USB Type-C Controller Datasheet
■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™
CCG2

Document Number: 002-20954 Rev. *A Page 23 of 25

 CY7C65219

Document History Page

Document Title: CY7C65219 Dock Management Controller (DMC)
Document Number: 002-20954
Orig. of Submission
Revision ECN Description of Change
Change Date
*A 6002250 MUTH 12/21/2017 Initial release. Changed datasheet status to Final.

Document Number: 002-20954 Rev. *A Page 24 of 25

 CY7C65219

Sales, Solutions, and Legal Information

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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.

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Power Management ICs cypress.com/pmic
Touch Sensing cypress.com/touch
USB Controllers cypress.com/usb
Wireless Connectivity cypress.com/wireless

IMPORTANT NOTE REGARDING PROTECTED FIRMWARE DOWNLOAD: Cypress has implemented protections in the product to prevent unauthorized firmware updates from being applied to the
product. However, no computing device or system can be absolutely secure. Therefore, the parties agree that Cypress shall not have any liability arising out of any failure of the product's security
features, such as the inability to load firmware or a breach allowing the loading of unauthorized firmware.

Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB
Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify
the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely
responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any
modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you
had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT
NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.

© Cypress Semiconductor Corporation, 2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided
by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.

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OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-20954 Rev. *A Revised December 22, 2017 Page 25 of 25

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