Interrupt

User program handler X

Interrupt
handler Y

(a) Sequential interrupt processing

Interrupt
User program handler X

Interrupt
handler Y

(b) Nested interrupt processing

Figure 3.13 Transfer of Control with Multiple Interrupts

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 Printer Communication
User program
interrupt service routine interrupt service routine
t=0

15
0 t=
t =1

t = 25

t= t = 25 Disk
40 interrupt service routine

t=
35

Figure 3.14 Example Time Sequence of Multiple Interrupts

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+
I/O Function
◼ I/O module can exchange data directly with the processor

◼ Processor can read data from or write data to an I/O module

◼ Processor identifies a specific device that is controlled by a
particular I/O module
◼ I/O instructions rather than memory referencing instructions

◼ In some cases it is desirable to allow I/O exchanges to occur

directly with memory
◼ The processor grants to an I/O module the authority to read from
or write to memory so that the I/O memory transfer can occur
without tying up the processor
◼ The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
◼ This operation is known as direct memory access (DMA)

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 Read Memory
Write
N Words
Address 0 Data

Data N–1

Read I/O Module Internal

Write Data

External
Address M Ports Data

Internal
Data Interrupt
Signals
External
Data

Instructions Address

Control
Data CPU Signals

Interrupt Data
Signals

Figure 3.15 Computer Modules

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 The interconnection structure must support the
following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access

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 A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices reception by all other
devices attached to the bus
I
• Key characteristic is that it is a
shared transmission medium • If two devices transmit during the

n
same time period their signals will
overlap and become garbled

n
e
Typically consists of multiple
Computer systems contain a t
B c
communication lines
number of different buses
• Each line is capable of that provide pathways
transmitting signals representing
binary 1 and binary 0 between components at e
u t
various levels of the
computer system hierarchy

r
s i
System bus c
• A bus that connects major The most common computer o
o
computer components (processor,
memory, I/O) interconnection structures
are based on the use of one
or more system buses
n
n
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 Data Bus
◼ Data lines that provide a path for moving data among system
modules

◼ May consist of 32, 64, 128, or more separate lines

◼ The number of lines is referred to as the width of the data bus

◼ The number of lines determines how many bits can be

transferred at a time

◼ The width of the data bus

is a key factor in
determining overall
system performance

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+ Address Bus Control Bus

◼ Used to designate the source or

destination of the data on the ◼ Used to control the access and the
data bus use of the data and address lines
◼ If the processor wishes to
read a word of data from ◼ Because the data and address lines
memory it puts the address of are shared by all components there
the desired word on the must be a means of controlling their
use
address lines
◼ Control signals transmit both
◼ Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
◼ Timing signals indicate the validity
◼ Also used to address I/O ports of data and address information
◼ The higher order bits are
used to select a particular ◼ Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
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 CPU Memory Memory I/O I/O

Control lines

Address lines Bus

Data lines

Figure 3.16 Bus Interconnection Scheme

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+ Summary A Top-Level View of
Computer Function
and Interconnection
Chapter 3

◼ Computer components
◼ Computer function
◼ Instruction fetch and
execute
◼ Interrupts
◼ I/O function
◼ Interconnection structures
◼ Bus interconnection

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