A novel low-power full-adder cell with new technique in designing logical gates

based on static CMOS inverter

(A Synopsis On Project Activity for The fulfillment of M.Tech)

(VINOD RATHOR)

(MEL-2592-2K8)

(YMCA University of Science & Technology, Faridabad)

Submitted To:-
Introduction
Addition is a very basic operation in arithmetic. Subtraction, multiplication, division and address
calculation are some of the well-known operations based on addition. These operations are
widely used in many VLSI applications, since the full-adder cell is the building block of the
binary adder, enhancing the performance of the 1-bit full-adder is a significant goal and has
attracted much attention. A variety of full-adders using different logic styles and technologies
have been reported in literature and they commonly aim at reducing power consumption and
increasing speed.

The total power dissipated in a generic digital CMOS gate is given by

Ptotal = Pdynamic+ Pshortcircuit + Pstatic

. Many full-adders have been designed and published in literature. They are built upon different
logic styles. Among these adders the circuits explained below will be used for comparison in this
paper. Although all of them perform a similar function, but the method of producing the
intermediate nodes and the outputs, the loads on them and the transistor count are varied.
Different logic styles tend to favor one performance aspect at the expense of the other. Some of
them use one logic style for the whole full- adder and the others use more than one logic style for
their implementation. In all of these full-adders, it is tried to reduce power and delay factors and
thus decrease power-delay product (PDP) in comparison to the previous ones. It is based on
regular CMOS structure with pull-up and pull-down transistors and has 28 transistors. Another
conventional adder is the Complementary Pass-Transistor Logic (CPL) with swing restoration
which uses 32 transistors. CPL produces many intermediate nodes and their complement to make
the outputs. The basic difference between the pass- transistor logic and the complementary
CMOS logic styles is that the source side of the pass logic transistor network is con

Analysis and results

Simulations using HSpice have been performed on nine circuits including: Static
3inputNAND,Static 3 input NOR, Static 3input MAJORITY-NOT Function, Dynamic 3 input
NAND ,Dynamic 3 input NOR, Dynamic 3 input MAJORITY-NOT Function ,New Static 3
input NAND, New Static 3 input NOR and New Static 3input MAJORITY NOT Function with
revising threshold voltage .The technology being used is 0.18mm. For the six previous static and
dynamic circuits the threshold voltage of the NMOS and PMOS transistors are around 0.39 and
0.42 V, respectively, but by modifying the threshold voltage of the circuit NAND ,NOR ,and
MAJORITY-NOT Function can be implemented. The operating frequency is 100MHz and the
supply voltage is 1V at 27 degree C. The input sarefed from the buffers (two cascaded inverters)
to give more realistic input signals. A randomly generated input pattern is applied to the cells for
a long period in order to measure the average power consumption of the cells. Comparison of
different NAND, NOR and MAJORITY-NOT Function to achieve minimum PDP is discussed
below and the three subsections refer to DELAY, POWER, and PDP.

(1) Delay comparison: the values of power, delay and power-delay product of conventional and
presented gates are illustrated in Table for comparison. For each transition, the delay is measured
from 50% of the input voltage swing to 50% of the output voltage swing. The maximum delay is
taken as the cell delay. The new design of NAND gate is 16% and 36% faster than Dynamic and
Static NAND gates, respectively. The delay of Dynamic NOR gate is smaller than the new
design, but this degradation is compensated with its improvement in power dissipation and as It
is shown this new design has better Power-Delay Product.

(2) Power comparison: HSpice generated an average power consumption value for each
circuit. As Table shows, simulation results illustrate that the Static 3 input gates with revising
threshold voltage have lowest power dissipation amongst the other gates. The proposed NOR
gate consumes 8%, 23%, NAND gate 7 % ,25% and MAJORITY-NOT Function gate 21%,22%
less powe rthan the Static and Dynamic gates, respectively.

(3) Power-delay product comparison: The PDP is a quantitative measure of the efficiency and a
compromise between power dissipation and speed. PDP is particularly important when low-
power operation is needed. As Table shows, among all of these gates the presented circuits have
the best PDP.

Three input NAND, NOR, MAJORITY-NOT function gate with capacitors.

New inverter-based full-adder with pass transistors

 .

New inverter-based full-adder with transmission gates

Simulation results In this section, the proposed circuit is evaluated and compared to the other
ones chosen from literature. The full-adder cells are simulated using 0.18 mm and 90nm CMOS
technology files with250MHz and at 27 degree C and the supply voltages varying from 0.8 to
1.8V for 0.18 mm and 0.6–1.2V for 90 nm. It has been a common practice to treat the full-adder
cell as a standalone cell in simulation. It is also not unusual that the full-adder cells that perform
well in such simulation still fail upon actual deployment because of the lack of driving power.
This is because full-adder cells are normally cascaded to form a use ful arithmetic circuit.
Therefore, the full-adder cells must possess sufficient drivability to provide the next cell with
clean inputs.

Test-bench structure

the driving cell must provide almost full swing outputs to the driven cells. Otherwise, the
performance of the circuit will be degraded dramatically or become non-operative at low supply
voltage. For this reason, the adder cells of TFA, TGA, 14T, and 10T cannot be cascaded without
additional buffers attached to the outputs of each cell. In order to have a practical application for
the proposed circuit, the suggested structure for simulation is shown in Fig. 7, which is made of
16 cascaded full-adder cells. This structure simulates the circuits like regular multipliers and
binary adders that use full- adder cells as the building block. The inputs are fed from the buffers
to give more realistic input signals and the outputs are loaded with buffers to give proper loading
condition. All the required input-pattern-to-input-pattern transitions are included in the test
patterns..

Layout of MOSCAPs and PMOS transistors

Proposed symmetric full-adder layout.

Conclusions
A novel low-power inverter-based bit full-adder is proposed. Its simple16 transistors structure
results in a significant improvement in power consumption, PDP and performance of a bit full-
adder cell. Few transistor counts, the ability to work at ultra low-power supply voltages, and
finally elimination of short circuit current are the three major features of the proposed adder cell.
Directions for future works may include more detailed performance metrics valuations, as well
as implementing many other circuits in nanometer regime such as Single Electron
Transistor(SET), Carbon Nano Tube (CNT), Quantum dot Cellular Automata(QCA),and
generally whenever the threshold detector technique is applicable.