Hardware Specification

For SW programmer
L3 10Gigabit Data Center
Top of Rack / Spine Switch

ES5654BT2X-FLF-168ZZ
( AS5812-54X )

Version: V.01

By Alan Chen

Doc. Number:
Jun.,15, 2016
Accton Technology Corporation
No. 1, Creation Rd. III, Science-Based Industrial Park,
Hsinchu 300, Taiwan, R.O.C.

Copyright 2011 Accton. All rights reserved

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Copyright © 2014 by Accton Technology Corporation. All rights reserved.

The drawings, specifications and the data contain herein are the exclusive property of Accton Technology Corp.
issued in strict confidence and shall not, without the prior written permission of Accton Technology Corp., be
reproduced, copied or used, in parts or as a whole, for any purpose whatsoever, except the manufacture of
articles for Accton Technology Corp.
Accton makes no warranties with respect to the correctness, accuracy or wholeness of this PRELIMINARY
specification. The information in this document is subject to change without notice. Accton reserves the
right to make revisions to this document and the product described herein without obligation to notify any
person or entity of any such changes.

Warning

This document is intended for internal use only. A Non-Disclosure Agreement (NDA) approved by Chief
Technology Officer (CTO) is required to release this document under any circumstances.

Reviewed By: Alan Chen Date: _06__ /_15__ /_2016__

Approved By: Alan Chen Date: _06__ /_15__ /_2016__

Released By: Alan Chen Date: _06__ /_15__ /_2016__

Accton and SwitcHub are trademarks or registered trademarks of Accton Technology Corporation. Other
trademarks or brand names mentioned herein are trademarks of their respective companies .

Revision History
Rev. Date Author Revision Description
V0.1 05/23/2016 Alan Chen First Released for Intel platform (Intel Rangeley 2538)
For Software programmer application

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Table of Content

1. Introduction ................................................................................................................................... 1
1.1. Reference Documents ............................................................................................. 1
1.2. Acronyms and Terminology .................................................................................... 2
2. Hardware Architecture................................................................................................................. 3
2.1. Overview ................................................................................................................. 3
2.2. Block Diagram ........................................................................................................ 4
2.2.1. Reset Tree ........................................................................................................ 6
2.3. EEPOM ................................................................................................................... 7
2.4. Flash ........................................................................................................................ 7
2.5. I2C/SMBus Architecture ......................................................................................... 9
2.6. Interrupt ..................................................................................................................11
2.7. GPIO...................................................................................................................... 12
2.7.1. RTC clock ...................................................................................................... 14
2.8. CPLD ..................................................................................................................... 15
2.8.1. Reserved (0x00) ............................................................................................ 16
2.8.2. CPLD Version (0x01, Read only).................................................................. 17
2.8.3. PSU Status (0x02, Read only) ....................................................................... 17
2.8.4. Reserved (0x03) ............................................................................................ 18
2.8.5. Reset Control (0x04, Read & Write) ............................................................. 18
2.8.6. Reset Control (0x05, Read & Write) [Useless for ES5654BT2]................... 19
2.8.7. Reset Control (0x06, Read & Write) [Useless for ES5654BT2]................... 20
2.8.8. LM75 Interrupt Status (0x07) ....................................................................... 21
2.8.9. PHY Interrupt (16~9) Status (0x08) [Useless for ES5654BT2] ................... 22
2.8.10. PHY Interrupt (8~1) Status (0x09) [Useless for ES5654BT2] ..................... 23
2.8.11. System LED Status (0x0A) ........................................................................... 24
2.8.12. PSU LED Status (0x0B) ................................................................................ 24
2.8.13. FAN Fault Status (0x0C) ............................................................................... 25
2.8.14. FAN PWM Cycle Status (0x0D) ................................................................... 26
2.8.15. FAN LED (0x0E) for 2U (96+0) [Useless for ES5654BT2]......................... 27
2.8.16. FAN1 SPEED (0x10) .................................................................................... 28
2.8.17. FAN2 SPEED (0x11) .................................................................................... 28
2.8.18. FAN3 SPEED (0x12) .................................................................................... 28
2.8.19. FAN4 SPEED (0x13) .................................................................................... 28

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2.8.20. FAN5 SPEED (0x14) .................................................................................... 28

2.8.21. 1U (48+6) FAN LED (0x16) for ES5654BT2 used only .............................. 29
2.8.22. 1U (48+6) FAN LED (0x17) for ES5654BT2 used only .............................. 30
2.8.23. FANR1 SPEED (0x18) .................................................................................. 31
2.8.24. FANR2 SPEED (0x19) .................................................................................. 31
2.8.25. FANR3 SPEED (0x1A) ................................................................................. 31
2.8.26. FANR4 SPEED (0x1B) ................................................................................. 31
2.8.27. FANR5 SPEED (0x1C) ................................................................................. 31
FANR Fault Status (0x1F) ............................................................................................. 32
2.9. CPLD 2 .................................................................................................................. 33
2.9.1. Reserved (0x00) ............................................................................................ 34
2.9.2. CPLD Version (0x01, Read only).................................................................. 34
2.9.3. I2C_Select (0x02, R/W) ................................................................................ 34
2.9.4. SFP+_INT (0x03, R/W) ................................................................................ 35
2.9.5. SFP+_INT (0x04, R/W) ................................................................................ 35
2.9.6. SFP+_INT (0x05, R/W) ................................................................................ 35
2.9.7. SFP+_Present_1 (0x06, Read only) .............................................................. 36
2.9.8. SFP+_Present_2 (0x07, Read only) .............................................................. 36
2.9.9. SFP+_Present_3 (0x08, Read only) .............................................................. 36
2.9.10. TX_Fault_1 (0x09, Read only) ..................................................................... 36
2.9.11. TX_Fault_2 (0x0A, Read only) .................................................................... 37
2.9.12. TX_Fault_3 (0x0B, Read only) ..................................................................... 37
2.9.13. TX_Disable_1 (0x0C, R/W) ......................................................................... 37
2.9.14. TX_Disable_2 (0x0D, R/W) ......................................................................... 38
2.9.15. TX_Disable_3 (0x0E, R/W) .......................................................................... 38
2.9.16. RX_LOSS_1 (0x0F, Read only) .................................................................... 38
2.9.17. RX_LOSS_2 (0x10, Read only) .................................................................... 39
2.9.18. RX_LOSS_3 (0x11, Read only) .................................................................... 39
2.10. CPLD 3 .................................................................................................................. 40
2.10.1. Reserved (0x00) ............................................................................................ 42
2.10.2. CPLD Version (0x01, Read only).................................................................. 42
2.10.3. I2C_Select (0x02, R/W) ................................................................................ 42
2.10.4. SFP+_INT (0x03, R/W) ................................................................................ 43
2.10.5. SFP+_INT (0x04, R/W) ................................................................................ 43
2.10.6. SFP+_INT (0x05, R/W) ................................................................................ 43
2.10.7. SFP+_Present_1 (0x06, Read only) .............................................................. 44

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2.10.8. SFP+_Present_2 (0x07, Read only) .............................................................. 44

2.10.9. SFP+_Present_3 (0x08, Read only) .............................................................. 44
2.10.10. TX_Fault_1 (0x09, Read only) ............................................................. 44
2.10.11. TX_Fault_2 (0x0A, Read only) ............................................................ 45
2.10.12. TX_Fault_3 (0x0B, Read only) ............................................................. 45
2.10.13. TX_Disable_1 (0x0C, Read only) ......................................................... 45
2.10.14. TX_Disable_2 (0x0D, Read only) ........................................................ 46
2.10.15. TX_Disable_3 (0x0E, Read only) ......................................................... 46
2.10.16. RX_LOSS_1 (0x0F, Read only) ............................................................ 46
2.10.17. RX_LOSS_2 (0x10, Read only)............................................................ 47
2.10.18. RX_LOSS_3 (0x11, Read only) ............................................................ 47
2.10.19. QSFP+_INT (0x12, R/W) ..................................................................... 48
2.10.20. QSFP+_Module_INT (0x13, Read only) .............................................. 48
2.10.21. QSFP+_Present (0x14, Read only) ....................................................... 48
2.10.22. QSFP+_MOD_RST (0x15, R/W) ......................................................... 49
2.10.23. QSFP+_LPMODE (0x16, R/W) ........................................................... 49
3. Switch Sub-System ...................................................................................................................... 50
3.1. Port Mapping ......................................................................................................... 50
4. Port LED ...................................................................................................................................... 51
4.1. Network Port ......................................................................................................... 53
4.2. System LEDs ......................................................................................................... 54
4.2.1. Fan /Fan’s suggested alternative present/Suggested thermal map ................ 55
4.2.2. Thermal sensor Location ............................................................................... 58

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Tables
Table 1 System Overview ....................................................................................................... 3
Table 2 EEPOM ...................................................................................................................... 7
Table 3 SPI Flash .................................................................................................................... 7
Table 4 USB to NAND Flash ................................................................................................. 8
Table 5 I2C/SMBus Table..................................................................................................... 10
Table 6 GPIO Connection ..................................................................................................... 14
Table 7 System CPLD Register Table .................................................................................. 16
Table 8 CPLD for SFP+(Port1-24) Register Table ............................................................... 33
Table 9 CPLD for SFP+(Port25-48)/QSFP+(Port1-6) Register Table ................................. 41
Table 10 Switch Port Mapping Table.................................................................................... 51
Table 11 Port LED Definition ............................................................................................... 52
Table 12 Types of Transceiver Supported............................................................................. 54
Table 13 System LED Definition.......................................................................................... 55
Table 14 Thermal Sensor mapping table .............................................................................. 58

Figures
Figure 1 Block Diagram of CPU module ................................................................................ 4
Figure 2 Block Diagram of Mainboard ................................................................................... 5
Figure 3 CPU Reset Tree ......................................................................................................... 6
Figure 4 USB to NAND Channel (eUSB) .............................................................................. 8
Figure 5 I2C Architecture ........................................................................................................ 9
Figure 6 Front Port Mapping ................................................................................................. 50
Figure 7 Mainboard thermal location .................................................................................... 58

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1. Introduction
This document describes the hardware product requirements and hardware architecture for
AS5812-54X, which is also known as ES5654BT2X. The switch configurations consist of
48*10G SFP+ ports and 6*40G QSFP ports on the front panel. The AS5812-54X enables the
aggregation of high density 1U rack servers, as the data center transitions from 1GE to 10GE
and beyond 40G, also Top-of-Rack, End-of-Row and core switches provide agile network
infrastructure solutions to keep ahead of the growing bandwidth demands in data center
networks.
All default ports are SFP+ optical ports that support standard 10Gb SFP+ optical
transceivers and standard 1Gb SFP optical transceivers.
The ES5654BT2X is a power reduction version which is more suitable to be deployed in
data center to support low-power consumption requirement.

1.1. Reference Documents

Some of the applicable documents used in this document are listed below:
1) Rangeley_WW30_MoW (512025)
2) AvotonRangeley_OrCAD_Symbol_Files (509711)
3) RangeleyRCCPlatform_Schematic_Rev0_4_X200_Schematic (519127)
4) RCC_Docs_V100 (534604)
5) Rangeley_SOC_RCC_F200_Layout_BOM (526564)
6) RCC_platform_Design_Guide_Supplement_review (511898)
7) Rangeley_EDS_Rev1.7_Review (510524)
8) EFRP-G657-S40_rev1.0, 07/09/2013
9) Broadcom 56860-DS112-RDS, 6/28/2013
10) Broadcom 54616S-AN103-RDS, 2/7/2013

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1.2. Acronyms and Terminology

Some of the acronyms used in this document are listed below:
CCSR Configuration, Control, and Status Register
PCB Printed Circuit Board
PCBA Printed Circuit Board Assembly
PSU Power Supply Unit
RU Rack Mount Unit (equivalent to 1.75 inches)
SERDES Serializer / Deserializer
SKU Stock Keeping Unit
SMI Serial Management Interface
FRU Field Replaceable Unit
GPIO General Purpose Input Output
IP Internet Protocol
NP Network Processor
CPLD Complex Programmable Logic Device
RXAUI Reduced XAUI
RU Rack Mount Unit (equivalent to 1.75 inches)
SFP+ Small Form-Factor Pluggable plus
SGMII Serial GMII
XAUI 10 G Attachment Unit Interface
XLAUI 40 G Attachment Unit Interface
QSFP+ 40 G Small Form-Factor Pluggable

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2. Hardware Architecture
This chapter describes the architecture of PCBA, cooling, power consumption, electrical,
reset, clocks, Ethernet port mapping etc..

2.1. Overview
ES5654BT2X-FLF-168ZZ
CPU: C2538 2.4GHz 3.0V FCBGA1283 INTEL
SDRAM: DDRIII 4GB x 2 with ECC SO-DIMM
M3D0-4GHS2LPC 4GB 1.35V ECCSODIMM INNODISK
USB to NAND Flash memory : 8GB ATP AF8GSSGH-AC1
SPI NOR Flash (Boot): 8 MB W25Q64FVSSIG WINBOND
CPU SPI NOR Flash (Backup): 8 MB W25Q64FVSSIG WINBOND
sub-system SPI NOR Flash (FPGA): 4MB AT25DF321A-MH-T ADESTO
EEPROM (Ethernet): 256Kb 25AA256T-I/SM MICROCHIP
EEPROM (FPGA-Board ID): 2Kb GT24C02-2UDLI-TR GIANTEC
FPGA: A2F200M3F-1FGG256 MICROSEMI
CPLD: Altera EPM570 (3 pcs, TQFP144 package)
TPM: ST33ZP24AR28PVSP ST
Management UART RS232 console port (RJ45), Out-band Management Ethernet port (RJ45)
Broadcom Trident2+ BCM56864, 1 pcs, 720Gbs multi-layer Ethernet switch
MAC
controller
SATA CONN Reserve mSATA connector
Ethernet Ports 48x SFP+ ports + 6x QSFP+
14-Layers, TUC TU-872LK for Mainboard
PCB 12-Layers, FR4, Tg 180 for CPU module
4-Layers, FR4, Tg 150 (TU662) FAN Board
Compuware 400W PSU(CPR-4011-4M21:back to front airflow, AC to DC ;
Power Supply CPR-4011-4M11:front to back airflow, AC to DC), 1+1 redundant load-sharing,
hot-swappable
Cooling 5 fan-tray modules with 5 pcs of 40mmx40mmx56mm 12V fans, hot-swappable
Dimension 473mm (L: Depth) x 442.5mm (W: Width) x 43.95mm (H: Height)
Table 1 System Overview

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2.2. Block Diagram

The high-level CPU module block diagram is shown as below

Figure 1 Block Diagram of CPU module

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The high-level Data plane block diagram is shown as below

Figure 2 Block Diagram of Mainboard

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2.2.1.Reset Tree

Figure 3 CPU Reset Tree

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2.3. EEPOM
There are several EEPROMs on the CPU board, which are saving the configuration files of
specific chips.
1. 2kb EEPROM via SMbus, saving the board information, current the content is TBD.
2. 256kb EEPROM via SPI interface of Rangeley, used to save the GBE configuration
files of Rangeley.

Type Base Address Size Actual Size Component Notes

EEPROM 2kb 2kb U37 FPGA Board ID for
H/W info
EEPROM 256kb 256kb U33 GBE configuration

Table 2 EEPOM

2.4. Flash
There are several Flash on the CPU board, which consist two groups:
1. SPI flash used to save the configuration files for specific chips
2. USB to NAND flash used to save the run-time software instead of SSD.
For SPI flash,
1. 4MB SPI flash, used to save the boot information for FPGA.
2. 8MB SPI flash, used to be the CI flash to save the boot files of Rangeley.
3. 8MB SPI flash, used to be the KGI flash save the redundant boot files of Rangeley
Type Base Address Size Actual Size Component Notes
SPI Flash 4MB 4MB U24 For FPGA

SPI Flash 8MB 8MB U16 CI flash

SPI Flash 8MB 8MB U36 KGI flash

Table 3 SPI Flash

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For USB to NAND flash:

The CPU board consists of a ATP AF8GSSGH-AC1, 8GB SLC NAND flash to store the run-time
software instead of the SSD.

The CPU board will using the USB (USB ch3) interface to manage the USB to NAND flash
controller to control the NAND flash.
Type Base Address Size Actual Size Component Notes
USB to 8GB 8GB CONN12 For run-time
NAND Flash

Table 4 USB to NAND Flash

Figure 4 USB to NAND Channel (eUSB)

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2.5. I2C/SMBus Architecture

The CPU-C2538 has two I2C channels for our application. The SMBus0 used for system
peripheral access include SODIMM, FPGA, CLK GEN and CPLDs. The SMBus1 used for
EEPROM, Power Supply, DC/DC, thermal sensor and USB HUB.

Figure 5 I2C Architecture

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Slave device Slave address Slave device Slave address

SODIMM SPD EEPROM CH0 0x52
SODIMM SPD EEPROM CH1 0x53
CLK GEN 0x69
FPGA
SMBus 0 Potentmeter 0x2E
CPLD 1 0x60
Refer to 3.20
CPLD 2 0x61 24xSFP+ ( Port1 –24 )
CPLD2 mapping table
24xSFP+ ( Port25 –48 ) Refer to 3.21
CPLD 3 0x62
6xQSFP+ ( Port1 –6 ) CPLD3 mapping table

Slave device Slave address Slave device Slave address

Ch1 PSU1 module 0x38/0x3C

Ch2 PSU2 module 0x3B/0x3F
Ch3 DC/DC 0x08
SMBus 1 PCA9548 0x70
Ch4
Ch5 LM75 thermal sensor 0x48
Ch6 LM75 thermal sensor 0x49
Ch7 LM75 thermal sensor 0x4A
EEPROM 0x57

Table 5 I2C/SMBus Table

Note. PSU1 DC48V power supply address – 0x50

PSU2 DC48V power supply address – 0x53

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2.6. Interrupt
Interrupt map as below.

Bit 0
R LM75
LM75
0x48

Bit 1 R LM75
LM75
0x49 SFP+
SFP+_INT
R LM75
LM75
R/W (Port1
Port1 –8)
Bit 2 (Register 0x03)
0x4A 03)
GBE_
GBE_SDP0
SDP0_0 CPLD_
CPLD_INT_
INT_CPU
SFP+
SFP+_INT
System CPLD R/W
EPM570
(Port9
Port9 –16)
16)
EPM 570T
570T
0x60 Management PHY (Register 0x04)
04)
INTEL B2B CONN R
RANGELEY 07 )Bit 3
(Register 0x07) BCM54616
BCM 54616S
54616S
SFP+
SFP+_INT
Board R/W (Port17
Port17 –24)
24)
(Register 0x05)
05)
CPLD2
CPLD2 SFP+
SFP+_INT
Bit 4
R EPM1270
EPM 1270
R/W (Port25
Port25 –32)
32)
0x61
( CPLD2
CPLD 2_INT_
INT_L ) (Register 0x03)
03)

CPLD3
CPLD3
Bit 5 R EPM1270
EPM 1270
SFP+
SFP+_INT
R/ W (Port33
Port33 –40)
40)
0x62
( CPLD3
CPLD 3_INT_
INT_L ) (Register 0x04)
04)

R/W SFP+
SFP+_INT
(Port41
Port41 –48)
48)
(Register 0x05)
05)

R/W QSFP+
QSFP+_INT
(Port1
Port1 –6)
(Register 0x12)
12)

QSFP+
QSFP+_Module_
Module _INT
R
(Port1
Port1 –6)
(Register 0x13)
13)

Pin Name of C2538 Function Connection

CPLD_INT_L
GBE_SDP0_0
(GPIO_SUS17)

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2.7. GPIO
The C2538 can support 58 general purpose I/O ports. Each port can be configured as an
input or as an output. If a port is configured as an input, it can optionally generate an interrupt
upon detection of a change. If a port is configured as an output, it can be individually
configured as an open-drain or a fully active output. In ES5654BT1 we use some of GPIO pin
to simulate the JTAG signals for MB and module CPLD code upgrade. The detail GPIO
mapping configuration is as below table.
GPIOs Pin# Alternate Function Rangeley Configuration
GPIO_0 AL56 NMI Alternate Function
GPIO_1 AL63 ERROR2_B Alternate Function
GPIO_2 AL62 ERROR1_B Alternate Function
GPIO_3 AL65 ERROR0_B Alternate Function
GPIO_4 AM52 IRERR_B Alternate Function
GPIO_5 AL52 MCERR_B Alternate Function
GPIO_6 AG50 UART1_RXD Alternate Function
GPIO_7 AH50 UART1_TXD Alternate Function
GPIO_8 AN62 SMB_CLK0 Alternate Function
GPIO_9 AP62 SMB_DATA0 Alternate Function
GPIO_10 AL58 SMB_ALRT_N0 Alternate Function
GPIO_11 AN63 SMB_DATA1 Goes to Mainboard
GPIO_12 AR63 SMB_CLK1 Goes to Mainboard
GPIO_13 AN65 SMB_DATA2 UART0_TXD
GPIO_14 AR65 SMB_CLK2 UART0_RXD
GPIO_15 AT63 SATA_GP0 BD_ID_0
GPIO_16 AL49 SATA_LEDN N/A
GPIO_17 AH51 SATA3_GP0 BD_ID_1
GPIO_18 AH54 SATA3_LEDN Alternate Function
GPIO_19 AH59 FLEX_CLK_SE0 Alternate Function
GPIO_20 AG56 FLEX_CLK_SE1 Alternate Function
GPIO_21 AG54 LPC_LAD0 Alternate Function
GPIO_22 AM53 LPC_LAD1 Alternate Function
GPIO_23 AL53 LPC_LAD2 Alternate Function
GPIO_24 AG59 LPC_LAD3 Alternate Function
GPIO_25 AH56 LPC_FRAMEB Alternate Function

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GPIO_26 AG51 LPC_CLKOUT0 Alternate Function

GPIO_27 AM49 LPC_CLKOUT1 Alternate Function
GPIO_28 AH48 LPC_CLKRUNB Alternate Function
GPIO_29 AT50 ILB_SERIRQ Alternate Function
GPIO_30 AM58 PMU_RESETBUTTON_B Alternate Function

GPIOs Pin# Alternate Function Rangeley Configuration

GPIO_SUS0 V66 N/A ALTA_CPLD_TCK
GPIO_SUS1 W54 N/A ALTA_CPLD_TDI
BD_ID_2
GPIO_SUS2 T53 N/A
(SOC_FPGA_DATA_OUT)
GPIO_SUS3 Y63 CPU_RESET_B Alternate Function
GPIO_SUS4 Y57 SUSPWRDNACK N/A ; pull up
GPIO_SUS5 AD58 PMU_SUSCLK N/A
Goes to FPGA
GPIO_SUS6 AC52 PMU_SLP_DDRVTT_B
(SOC_FPGA_CLK)
Goes to FPGA, Output
GPIO_SUS7 Y50 PMU_SLP_LAN_B
(SOC_FPGA_DATA_IN)
GPIO_SUS8 AD66 PMU_WAKE_B Alternate Function
GPIO_SUS9 AC49 PMU_PWRBTN_B Alternate Function
N/A, pull down
GPIO_SUS10 AB65 SUS_STAT_B
(BUS switch select)
GPIO_SUS11 AD63 USB_OC0_B Alternate Function
GPIO_SUS12 AC58 SPI_CS1_B Alternate Function
GPIO_SUS13 W51 GBE_EE_DI Alternate Function
GPIO_SUS14 W60 GBE_EE_DO Alternate Function
GPIO_SUS15 T50 GBE_EE_SK Alternate Function
GPIO_SUS16 R59 GBE_EE_CS Alternate Function

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GPIO_SUS17 T58 GBE_SDP0_0 CPLD_INT_L

GPIO_SUS18 T48 GBE_SDP0_1 CPLD2_INT_L
GPIO_SUS19 P46 GBE_LED0 N/A, pull down
GPIO_SUS20 W50 GBE_LED1 N/A, pull down
GPIO_SUS21 P48 GBE_LED2 N/A, pull down
GPIO_SUS22 R58 GBE_LED3 N/A, pull down
GPIO_SUS23 V63 GBE_WOL N/A, pull down
GPIO_SUS24 W56 GBE_MDIO0_I2C_CLK MDIO0_CLK
GPIO_SUS25 W59 GBE_MDIO0_I2C_DATA MDIO0_DATA
GPIO_SUS26 Y54 GBE_MDIO1_I2C_CLK ALTA_CPLD_TDO
GPIO_SUS27 Y53 GBE_MDIO1_I2C_DATA ALTA_CPLD_TMS

Table 6 GPIO Connection

2.7.1.RTC clock
• RTC Clock input signal (32.768KHz)

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2.8. CPLD
A CPLD would be used for C2538 as the glue logic for getting some Specific
system-related information and doing some system controls. The CPLD for C2538 is connected
to the SMBus0.

The I/O register address mapping is listed in the table below: (System CPLD)
Register Offset R/W Default Value Description
Board ID 0x00 R 0x02 Board ID Setting for (96+8)/(96+0)/(48+6)
CPLD Version 0x01 R 0x01 CPLD Version information
PSU Status 0x02 R Power Supply 1 & 2 status information
Reserved 0x03 R Not define
0x04 R Reset control for BCM56850,
Reset Control
BCM54616S ,PCA9548PW
[Useless for 0x05 R N/A Register reserved for ES5654BT2
ES5654BT2] Register content just for reference
[Useless for 0x06 R N/A Register reserved for ES5654BT2
ES5654BT2] Register content just for reference
LM75 Interrupt status 0x07 R LM75 Interrupt status
[Useless for 0x08 R Register reserved for ES5654BT2
ES5654BT2] Register content just for reference
[Useless for 0x09 R 0x1F Register reserved for ES5654BT2
ES5654BT2] Register content just for reference
System LED 0x0A R 0x00 System LED control
PSU LED 0x0B R/W PSU LED status
FAN Fault 0x0C R FAN Fault status
FAN PWM cycle 0x0D R/W FAN PWM cycle control
[Useless for 0x0E R FAN LED control only used for 2U system -
ES5654BT2] ES56A4BT/ES5696BT
FAN1 Speed 0x10 R FAN1 speed Max. value to 21500 R.P.M.
FAN2 Speed 0x11 R FAN2 speed Max. value to 21500 R.P.M.
FAN3 Speed 0x12 R FAN3 speed Max. value to 21500 R.P.M.
FAN4 Speed 0x13 R FAN4 speed Max. value to 21500 R.P.M.
FAN5 Speed 0x14 R FAN5 speed Max. value to 21500 R.P.M.
FAN LED(1-4) 0x16 R FAN LED control only used for 1U system

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Register Offset R/W Default Value Description

0x17 R FAN LED control only used for 1U system –
FAN LED5
ES5654BT
FANR1 Speed 0x18 R FANR1 speed Max. value to 18000 R.P.M.
FANR2 Speed 0x19 R FANR2 speed Max. value to 18000 R.P.M.
FANR3 Speed 0x1A R FANR3 speed Max. value to 18000 R.P.M.
FANR4 Speed 0x1B R FANR4 speed Max. value to 18000 R.P.M.
FANR5 Speed 0x1C R FANR5 speed Max. value to 18000 R.P.M.
0x1D R Reserved
FANR Fault 0x1F R FANR Fault status

Table 7 System CPLD Register Table

2.8.1.Reserved (0x00)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Reserved Reserved Reserved Reserved Board_4 Board_3 Board_2 Board_1
Board ID = 0001 for ES5696BT-AO (96+0)
Board ID = 0010 for ES5654BT2-ZZ (48+6)
Board ID = 0011 for 32P x 40G
Board ID = 0100 for ES56A4BT-AO (96+8)

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2.8.2.CPLD Version (0x01, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

CPLD CPLD CPLD CPLD
Reserved Reserved Reserved Reserved
Version Bit3 Version Bit2 Version Bit1 Version Bit0
CPLD Version = 0001 for R0A H/W
CPLD Version = 0010 for R0B H/W

2.8.3.PSU Status (0x02, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserv PS2_AC_AL PS2_12V_ PS2_PRESE Reserv PS1_AC_AL PS1_12V_ PS1_PRESE
ed ERT PG NT ed ERT PG NT

PS2_AC_ALERT
0: AC is not OK
1: AC is OK

PS2_12V_ PG:
0: 12V Power Fail
1: 12V Power Good

PS2_ Present:
0: PSU present
1: PSU does not present

PS1_AC_ALERT
0: AC is not OK
1: AC is OK

PS1_12V_PG:
0: 12V Power Fail
1: 12V Power Good

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PS1_Present:
0: PSU present
1: PSU does not present

2.8.4.Reserved (0x03)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

2.8.5.Reset Control (0x04, Read & Write)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Reserved Reserved Reset_MAC MGMT_PHY_RST_N I2C_SW_PWR_RESET_N N_SHIFT_REG_CLR

Reset_MAC:
0: Reset the BCM56854 (MAC).
1: Not reset the BCM56854 (MAC).

MGMT_PHY_RST_N
0: Reset the BCM54616S (Management Port)
1: Not reset the BCM54616S (Management Port)

I2C_SW_PWR_RESET_N
0: Reset the PCA9548PW (I2C switch).
1: Not reset the PCA9548PW (I2C switch).

N_SHIFT_REG_CLR
0: Clear the Shift Register (74164).
1: Not clear the Shift Register (74164).

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2.8.6.Reset Control (0x05, Read & Write) [Useless for ES5654BT2]

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PHY16 PHY15 PHY14 PHY13 PHY12 PHY11 PHY10 PHY9
Reset Reset Reset Reset Reset Reset Reset Reset
Default 0xFF

PHY16 Reset
0: Reset PHY16
1: Not reset PHY16

PHY15 Reset
0: Reset PHY15
1: Not reset PHY15

PHY14 Reset
0: Reset PHY14
1: Not reset PHY14

PHY13 Reset
0: Reset PHY13
1: Not reset PHY13

PHY12 Reset
0: Reset PHY12
1: Not reset PHY12

PHY11 Reset
0: Reset PHY11
1: Not reset PHY11

PHY10 Reset
0: Reset PHY10
1: Not reset PHY10
PHY9 Reset
0: Reset PHY9

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1: Not reset PHY9

2.8.7.Reset Control (0x06, Read & Write) [Useless for ES5654BT2]

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PHY8 PHY7 PHY6 PHY5 PHY4 PHY3 PHY2 PHY1
Reset Reset Reset Reset Reset Reset Reset Reset
Default 0xFF
PHY8 Reset
0: Reset PHY8
1: Not reset PHY8

PHY7 Reset
0: Reset PHY7
1: Not reset PHY7

PHY6 Reset
0: Reset PHY6
1: Not reset PHY6

PHY5 Reset
0: Reset PHY5
1: Not reset PHY5

PHY4 Reset
0: Reset PHY4
1: Not reset PHY4

PHY3 Reset
0: Reset PHY3
1: Not reset PHY3

PHY2 Reset
0: Reset PHY2
1: Not reset PHY2

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PHY1 Reset
0: Reset PHY1
1: Not reset PHY1

2.8.8.LM75 Interrupt Status (0x07)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Reserved Reserved CPLD3_INT_L CPLD2_INT_L B54616_INT LM75_INT_ch3 LM75_INT_ch2 LM75_INT_ch1

CPLD3_INT_L
0: Interrupt from CPLD3 (for P25-P48SFP and P1-P6 QSFP).
1: No Interrupt from CPLD3 (for P25-P48SFP and P1-P6 QSFP).

CPLD2_INT_L
0: Interrupt from CPLD2 (for P1-P24SFP).
1: No Interrupt from CPLD2 (for P1-P24SFP).

B54616_INT
0: Interrupt from BCM54616S (Management Port).
1: No Interrupt from BCM54616S (Management Port).

LM75_INT_ch3
0: Interrupt from LM75 chip 3 (Thermal Sensor).
1: No Interrupt from LM75 chip 3 (Thermal Sensor).

LM75_INT_ch2
0: Interrupt from LM75 chip 2 (Thermal Sensor).
1: No Interrupt from LM75 chip2 (Thermal Sensor).

LM75_INT_ch1
0: Interrupt from LM75 chip 1(Thermal Sensor).
1: No Interrupt from LM75 chip1 (Thermal Sensor).

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2.8.9.PHY Interrupt (16~9) Status (0x08) [Useless for ES5654BT2]

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PHY16 PHY15 PHY14 PHY13 PHY12 PHY11 PHY10 PHY9
INT INT INT INT INT INT INT INT
PHY16 INT
0: PHY16 Interrupt occurs.
1: PHY16 Interrupt not occurs.
PHY15 INT
0: PHY15 Interrupt occurs.
1: PHY15 Interrupt not occurs.

PHY14 INT
0: PHY14 Interrupt occurs.
1: PHY14 Interrupt not occurs.

PHY13 INT
0: PHY13 Interrupt occurs.
1: PHY13 Interrupt not occurs.

PHY12INT
0: PHY12 Interrupt occurs.
1: PHY12 Interrupt not occurs.

PHY11 INT
0: PHY11 Interrupt occurs.
1: PHY11 Interrupt not occurs.

PHY10 INT
0: PHY10 Interrupt occurs.
1: PHY10 Interrupt not occurs.

PHY9 INT
0: PHY9 Interrupt occurs.
1: PHY9 Interrupt not occurs.

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2.8.10. PHY Interrupt (8~1) Status (0x09) [Useless for ES5654BT2]

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PHY8 INT PHY7 INT PHY6 INT PHY5 INT PHY4 INT PHY3 INT PHY2 INT PHY1 INT
PHY8 INT
0: PHY8 Interrupt occurs.
1: PHY8 Interrupt not occurs.

PHY7 INT
0: PHY7 Interrupt occurs.
1: PHY7 Interrupt not occurs.

PHY6 INT
0: PHY6 Interrupt occurs.
1: PHY6 Interrupt not occurs.

PHY5 INT
0: PHY5 Interrupt occurs.
1: PHY5 Interrupt not occurs.

PHY4 INT
0: PHY4 Interrupt occurs.
1: PHY4 Interrupt not occurs.

PHY3 INT
0: PHY3 Interrupt occurs.
1: PHY3 Interrupt not occurs.

PHY2 INT
0: PHY2 Interrupt occurs.
1: PHY2 Interrupt not occurs.

PHY1 INT
0: PHY1 Interrupt occurs.
1: PHY1 Interrupt not occurs.

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2.8.11. System LED Status (0x0A)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved LOC_B control LOC_B DIAG_A DIAG_G FAN_A FAN_G
LOC_B control
0: Locator LED OFF
1: Locator LED Blinking

LOC_B
0: Locator LED On
1: Locator LED OFF

DIAG_A
0: System self-diagnostic test detected a fault. (Fan, thermal or any interface fault.)
1: System self-diagnostic test doesn’t detect any fault. (Fan, thermal or any interface fault.)

DIAG_G
0: System self-diagnostic test successfully
1: System self-diagnostic test unsuccessfully

FAN_A
FAN_G
00: Release FAN LED control from S/W, FAN LED is lighted based on FAN hardware
status signals
01: Solid Amber by S/W means FAN operates abnormally
10: Solid Green by S/W means FAN operates normally
11: LED Off by S/W

2.8.12. PSU LED Status (0x0B)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Reserved Reserved PSU2_A PSU2_G PSU1_A PSU1_G
0000: Release PSU1/PSU2 LED control from S/W, PSU1/PSU2 LED is lighted based on
PSU1/PSU2 hardware status signals
0101: Solid Amber by S/Wand means PSU present or the power is failed.

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1010: Solid Green by S/W and means PSU operates normally

1111: LED Off by S/W

2.8.13. FAN Fault Status (0x0C)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserve Reserve Reserve FAN_FAUL FAN_FAUL FAN_FAUL FAN_FAUL FAN_FAUL
d d d T Bit 4 T Bit 3 T Bit 2 T Bit 1 T Bit 0

FAN_FAULT Bit4 (for ES5654BT2-ZZ product used)

0: FAN5 operates normally
1: FAN5 operates abnormally

FAN_FAULT Bit3
0: FAN4 operates normally
1: FAN4 operates abnormally

FAN_FAULT Bit2
0: FAN3 operates normally
1: FAN3 operates abnormally

FAN_FAULT Bit1
0: FAN2 operates normally
1: FAN2 operates abnormally

FAN_FAULT Bit0
0: FAN1 operates normally
1: FAN1 operates abnormally

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2.8.14. FAN PWM Cycle Status (0x0D)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Reserved PWM_Bit4 PWM_Bit3 PWM_Bit2 PWM_Bit1 PWM_Bit0

Default value: 10100 (100%)

PWM control set; value duty cycle
00000 0%
00001 5%
00010 10%
00011 15%
00100 20%
00101 25%
00110 30%
00111 35%
01000 40%
01001 45%
01010 50%
01011 55%
01100 60%
01101 65%
01110 70%
01111 75%
10000 80%
10001 85%
10010 90%
10011 95%
10100 100%
Note. (20% is the lowest Fan speed and can be adjusted register value. )

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2.8.15. FAN LED (0x0E) for 2U (96+0) [Useless for ES5654BT2]

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LED4_O LED4_G LED3_O LED3_G LED2_O LED2_G LED1_O LED1_G
FAN_LED Bit7
0: Orange LED on FAN4 off
1: Orange LED on FAN4 on

FAN_LED Bit6
0: Green LED on FAN4 off
1: Green LED on FAN4 on

FAN_LED Bit5
0: Orange LED on FAN3 off
1: Orange LED on FAN3 on

FAN_LED Bit4
0: Green LED on FAN3 off
1: Green LED on FAN3 on

FAN_LED Bit3
0: Orange LED on FAN2 off
1: Orange LED on FAN2 on

FAN_LED Bit2
0: Green LED on FAN2 off
1: Green LED on FAN2 on

FAN_LED Bit1
0: Orange LED on FAN1 off
1: Orange LED on FAN1 on

FAN_LED Bit0
0: Green LED on FAN1 off
1: Green LED on FAN1 on

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2.8.16. FAN1 SPEED (0x10)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FAN1)
Note: FAN speed’s Max. value to 21500 R.P.M.

2.8.17. FAN2 SPEED (0x11)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FAN2)
Note: FAN speed’s Max. value to 21500 R.P.M.

2.8.18. FAN3 SPEED (0x12)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FAN3)
Note: FAN speed’s Max. value to 21500 R.P.M.

2.8.19. FAN4 SPEED (0x13)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FAN4)
Note: FAN speed’s Max. value to 21500 R.P.M.

2.8.20. FAN5 SPEED (0x14)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FAN5)
Note: FAN speed’s Max. value to 21500 R.P.M.

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2.8.21. 1U (48+6) FAN LED (0x16) for ES5654BT2 used only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
LED4_O LED4_G LED3_O LED3_G LED2_O LED2_G LED1_O LED1_G

FAN_LED Bit7
0: Orange LED on FAN4 off
1: Orange LED on FAN4 on

FAN_LED Bit6
0: Green LED on FAN4 off
1: Green LED on FAN4 on

FAN_LED Bit5
0: Orange LED on FAN3 off
1: Orange LED on FAN3 on

FAN_LED Bit4
0: Green LED on FAN3 off
1: Green LED on FAN3 on

FAN_LED Bit3
0: Orange LED on FAN2 off
1: Orange LED on FAN2 on

FAN_LED Bit2
0: Green LED on FAN2 off
1: Green LED on FAN2 on

FAN_LED Bit1
0: Orange LED on FAN1 off
1: Orange LED on FAN1 on

FAN_LED Bit0
0: Green LED on FAN1 off
1: Green LED on FAN1 on

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2.8.22. 1U (48+6) FAN LED (0x17) for ES5654BT2 used only

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Reserved Reserved Reserved Reserved LED5_O LED5_G
FAN_LED Bit1
0: Orange LED on FAN5 off
1: Orange LED on FAN5 on

FAN_LED Bit0
0: Green LED on FAN5 off
1: Green LED on FAN5 on

PSU2 FAN5 FAN4 FAN3 FAN2 FAN1 PSU1

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2.8.23. FANR1 SPEED (0x18)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FANR1)
Note: FAN speed’s Max. value to 18000 R.P.M.

2.8.24. FANR2 SPEED (0x19)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FANR1)
Note: FAN speed’s Max. value to 18000 R.P.M.

2.8.25. FANR3 SPEED (0x1A)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FANR1)
Note: FAN speed’s Max. value to 18000 R.P.M.

2.8.26. FANR4 SPEED (0x1B)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FANR1)
Note: FAN speed’s Max. value to 18000 R.P.M.

2.8.27. FANR5 SPEED (0x1C)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Bit7~Bit0) * 150 = R.P.M (FANR1)
Note: FAN speed’s Max. value to 18000 R.P.M.

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FANR Fault Status (0x1F)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FANR_FAULT FANR_FAULT FANR_FAULT FANR_FAULT FANR_FAULT
Reserved Reserved Reserved
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FAN_FAULT Bit4
0: FANR5 operates normally
1: FANR5 operates abnormally

FAN_FAULT Bit3
0: FANR4 operates normally
1: FANR4 operates abnormally

FAN_FAULT Bit2
0: FANR3 operates normally
1: FANR3 operates abnormally

FAN_FAULT Bit1
0: FANR2 operates normally
1: FANR2 operates abnormally

FAN_FAULT Bit0
0: FANR1 operates normally
1: FANR1 operates abnormally

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2.9. CPLD 2
The I/O register address mapping is listed in the table below: (CPLD for SFP+(Port1-24))
Register Offset R/W Default Value Description
Reserved 0x00 R Reserved
CPLD Version 0x01 R 0x01 CPLD Version information
I2C_Select 0x02 R/W 0x00 Select I2C bus for SFP+ Port 1 to Port 24
0x03 R/W 0xFF Interrupt status when a SFP+ is present or not.
SFP+_INT_1
For SFP+ port 1 to port 8
0x04 R/W 0xFF Interrupt status when a SFP+ is present or not.
SFP+_INT_2
For SFP+ port 9 to port 16
0x05 R/W 0xFF Interrupt status when a SFP+ is present or not.
SFP+_INT_3
For SFP+ port 17 to port 24
0x06 R 0xFF Present status when a XCVR is installed or
SFP+_Present_1 not.
For SFP+ port 1 to port 8
0x07 R 0xFF Present status when a XCVR is installed or
SFP+_Present_2 not.
For SFP+ port 9 to port 16
0x08 R 0xFF Present status when a XCVR is installed or
SFP+_Present_3 not.
For SFP+ port 17 to port 24
TX_Fault_1 0x09 R 0xFF TX Fault status for SFP+ port 1 to port 8
TX_Fault_2 0x0A R 0xFF TX Fault status for SFP+ port 9 to port 16
TX_Fault_3 0x0B R 0xFF TX Fault status for SFP+ port 17 to port 24
TX_Disable_1 0x0C R/W 0x00 TX Disable status for SFP+ port 1 to port 8
TX_Disable_2 0x0D R/W 0x00 TX Disable status for SFP+ port 9 to port 16
TX_Disable_3 0x0E R/W 0x00 TX Disable status for SFP+ port 17 to port 24
RX_LOSS_1 0x0F R 0xFF RX LOSS status for SFP+ port 1 to port 8
RX_LOSS_2 0x10 R 0xFF RX LOSS status for SFP+ port 9 to port 16
RX_LOSS_3 0x11 R 0xFF RX LOSS status for SFP+ port 17 to port 24

Table 8 CPLD for SFP+(Port1-24) Register Table

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2.9.1.Reserved (0x00)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Reserved Reserved Reserved Reserved Board_4 Board_3 Board_2 Board_1

2.9.2.CPLD Version (0x01, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

CPLD CPLD CPLD CPLD
Reserved Reserved Reserved Reserved
Version Bit3 Version Bit2 Version Bit1 Version Bit0
CPLD Version = 0001 for R0A H/W
CPLD Version = 0010 for R0B H/W

2.9.3.I2C_Select (0x02, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

I2C_Select I2C_Select I2C_Select I2C_Select I2C_Select
Reserved Reserved Reserved
Bit4 Bit3 Bit2 Bit1 Bit0
I2C_Select Bit0
00000: Select I2C bus for SFP+ Port 1
00001: Select I2C bus for SFP+ Port 2
…………………………..
10101: Select I2C bus for SFP+ Port 22
10110: Select I2C bus for SFP+ Port 23
10111: Select I2C bus for SFP+ Port 24
FF: No select I2C bus

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2.9.4.SFP+_INT (0x03, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT
Port8 Port7 Port6 Port5 Port4 Port3 Port2 Port1
SFP+_INT_ Port1 to Port 8
0: Generates an interrupt when a SFP is present for SFP+ Port
1: No interrupt
Note: After Fiber port has been presented, SW need to clear interrupt status from low to high status.

2.9.5.SFP+_INT (0x04, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT
Port16 Port15 Port14 Port13 Port12 Port11 Port10 Port9
SFP+_INT_ Port9 to Port 16
0: Generates an interrupt when a SFP is present for SFP+ Port
1: No interrupt
Note: After Fiber port has been presented, SW need to clear interrupt status from low to high status.

2.9.6.SFP+_INT (0x05, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT
Port24 Port23 Port22 Port21 Port20 Port19 Port18 Port17
SFP+_INT_ Port17 to Port 24
0: Generates an interrupt when a SFP is present for SFP+ Port
1: No interrupt
Note: After Fiber port has been presented, SW need to clear interrupt status from low to high status.

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2.9.7.SFP+_Present_1 (0x06, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE
Port8 Port7 Port6 Port5 Port4 Port3 Port2 Port1

SFP+ Present signal for Port1 to Port 8

0: There is a SFP+ XCVR installed.
1: SFP+ port has been uninstalled

2.9.8. SFP+_Present_2 (0x07, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE
Port16 Port15 Port14 Port13 Port12 Port11 Port10 Port9

SFP+ Present signal for Port9 to Port 16

0: SFP+ port has been installed
1: SFP+ port has been uninstalled

2.9.9.SFP+_Present_3 (0x08, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE
Port24 Port23 Port22 Port21 Port20 Port19 Port18 Port17

SFP+ Present signal for Port 17 to Port 24

0: SFP+ port has been installed
1: SFP+ port has been uninstalled

2.9.10. TX_Fault_1 (0x09, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

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Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault
Port8 Port7 Port6 Port5 Port4 Port3 Port2 Port1

SFP+ TX_Fault status for Port 1 to Port 8

0: SFP+ Transmitter is working well
1: SFP+ Transmit Fault

2.9.11. TX_Fault_2 (0x0A, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault
Port16 Port15 Port14 Port13 Port12 Port11 Port10 Port9

SFP+ TX_Fault status for Port 9 to Port 16

0: SFP+ Transmitter is working well
1: SFP+ Transmit Fault

2.9.12. TX_Fault_3 (0x0B, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault
Port24 Port23 Port22 Port21 Port20 Port19 Port18 Port17

SFP+ TX_Fault status for Port 17 to Port 24

0: SFP+ Transmitter is working well
1: SFP+ Transmit Fault

2.9.13. TX_Disable_1 (0x0C, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+

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Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable
Port8 Port7 Port6 Port5 Port4 Port3 Port2 Port1

SFP+ TX_Disable status for Port 1 to Port 8

0: SFP+ is under transmit enable
1: SFP+ is under transmit disable

2.9.14. TX_Disable_2 (0x0D, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable
Port16 Port15 Port14 Port13 Port12 Port11 Port10 Port9

SFP+ TX_Disable status for Port 9 to Port 16

0: SFP+ is under transmit enable
1: SFP+ is under transmit disable

2.9.15. TX_Disable_3 (0x0E, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable
Port24 Port23 Port22 Port21 Port20 Port19 Port18 Port17

SFP+ TX_Disable status for Port 17 to Port 24

0: SFP+ is under transmit enable
1: SFP+ is under transmit disable

2.9.16. RX_LOSS_1 (0x0F, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS

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Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Port8 Port7 Port6 Port5 Port4 Port3 Port2 Port1

SFP+ RX_LOSS status for Port 1 to Port 8

0: SFP+ Receiver is working well
1: SFP+ Receive Loss

2.9.17. RX_LOSS_2 (0x10, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS
Port16 Port15 Port14 Port13 Port12 Port11 Port10 Port9

SFP+ RX_LOSS status for Port 9 to Port 16

0: SFP+ Receiver is working well
1: SFP+ Receive Loss

2.9.18. RX_LOSS_3 (0x11, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS
Port24 Port23 Port22 Port21 Port20 Port19 Port18 Port17

SFP+ RX_LOSS status for Port 17 to Port 24

0: SFP+ Receiver is working well
1: SFP+ Receive Loss

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2.10. CPLD 3
The I/O register address mapping is listed in the table below:
(CPLD for SFP+(Port24-48)/QSFP+(Port 49-54))
Register Offset R/W Default Value Description
Reserved 0x00 R Reserved
CPLD Version 0x01 R 0x02 CPLD Version information
0x02 R/W 0x1D Select I2C bus for SFP+ Port 25 to Port 48
I2C_Select
And QSFP+ Port 49 to Port 54
0x03 R/W 0xFF Interrupt status when a SFP+ is present or not.
SFP+_INT_1
For SFP+ port 25 to port 32
0x04 R/W 0xFF Interrupt status when a SFP+ is present or not.
SFP+_INT_2
For SFP+ port 33 to port 40
0x05 R/W 0xFF Interrupt status when a SFP+ is present or not.
SFP+_INT_3
For SFP+ port 41 to port 48
0x06 R 0xFF Present status when a XCVR is installed or
SFP+_Present_1 not.
For SFP+ port 25 to port 32
0x07 R 0xFF Present status when a XCVR is installed or
SFP+_Present_2 not.
For SFP+ port 33 to port 40
0x08 R 0xFF Present status when a XCVR is installed or
SFP+_Present_3 not.
For SFP+ port 41 to port 48
TX_Fault_1 0x09 R 0xFF TX Fault status for SFP+ port 25 to port 32
TX_Fault_2 0x0A R 0xFF TX Fault status for SFP+ port 33 to port 40
TX_Fault_3 0x0B R 0xFF TX Fault status for SFP+ port 41 to port 48
TX_Disable_1 0x0C R/W 0x00 TX Disable status for SFP+ port 25 to port 32
TX_Disable_2 0x0D R/W 0x00 TX Disable status for SFP+ port 33 to port 40
TX_Disable_3 0x0E R/W 0x00 TX Disable status for SFP+ port 41 to port 48
RX_LOSS_1 0x0F R 0xFF RX LOSS status for SFP+ port 25 to port 32
RX_LOSS_2 0x10 R 0xFF RX LOSS status for SFP+ port 33 to port 40
RX_LOSS_3 0x11 R 0xFF RX LOSS status for SFP+ port 41 to port 48

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Register Offset R/W Default Value Description

0x12 R/W 0xFF Present status when a XCVR is installed or
QSFP+_INT not.
For QSFP+ port 49 to port 54
0x13 R 0xFF Show module fault or status critical to the
system. The intL is internally pulled HIGH in
QSFP+_Module_INT
the module. Note. This is from the real QSFP+
XCVR pin28’s definition.
0x14 R 0xFF Present status when a XCVR is installed or
QSFP+_Present not.
For QSFP+ port 49 to port 54
0x15 R/W 0x00 Reset to the QSFP+ module.
QSFP+_MOD_RST
[Depend on module with reset function or not]
0x16 R/W 0x00 SW to control module under low power mode
QSFP+_LPMODE or high power mode. [Depend on module with
reset function or not]

Table 9 CPLD for SFP+(Port25-48)/QSFP+(Port1-6) Register Table

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2.10.1. Reserved (0x00)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Reserved Reserved Reserved Reserved Board_4 Board_3 Board_2 Board_1

2.10.2. CPLD Version (0x01, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

CPLD CPLD CPLD CPLD
Reserved Reserved Reserved Reserved
Version Bit3 Version Bit2 Version Bit1 Version Bit0
CPLD Version = 0001 for R0A H/W
CPLD Version = 0010 for R0B H/W

2.10.3. I2C_Select (0x02, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
I2C_Select I2C_Select I2C_Select I2C_Select I2C_Select
Reserved Reserved Reserved
Bit4 Bit3 Bit2 Bit1 Bit0
I2C_Select:
00000: Select I2C bus for SFP+ Port 25
00001: Select I2C bus for SFP+ Port 26
…………………………..
10111: Select I2C bus for SFP+ Port 48
11000: Select I2C bus for QSFP+ Port 49
11001: Select I2C bus for QSFP+ Port 52
11010: Select I2C bus for QSFP+ Port 50
11011: Select I2C bus for QSFP+ Port 53
11100: Select I2C bus for QSFP+ Port 51
11101: Select I2C bus for QSFP+ Port 54
FF: No Select I2C bus

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2.10.4. SFP+_INT (0x03, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT
Port32 Port31 Port30 Port29 Port28 Port27 Port26 Port25
SFP+_INT_ Port25 to Port 32
0: Generates an interrupt when a SFP is present for SFP+ Port
1: No interrupt
Note: After Fiber port has been presented, SW need to clear interrupt status from low to high status.

2.10.5. SFP+_INT (0x04, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT
Port40 Port39 Port38 Port37 Port36 Port35 Port34 Port33
SFP+_INT_ Port33 to Port 40
0: Generates an interrupt when a SFP is present for SFP+ Port
1: No interrupt
Note: After Fiber port has been presented, SW need to clear interrupt status from low to high status.

2.10.6. SFP+_INT (0x05, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT SFP+_INT
Port48 Port47 Port46 Port45 Port44 Port43 Port42 Port41
SFP+_INT_ Port41 to Port 48
0: Generates an interrupt when a SFP is present for SFP+ Port
1: No interrupt
Note: After Fiber port has been presented, SW need to clear interrupt status from low to high status.

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2.10.7. SFP+_Present_1 (0x06, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE
Port32 Port31 Port30 Port29 Port28 Port27 Port26 Port25

SFP+ Present signal for Port25 to Port 32

0: There is a SFP+ XCVR installed.
1: SFP+ port has been uninstalled

2.10.8. SFP+_Present_2 (0x07, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE
Port40 Port39 Port38 Port37 Port36 Port35 Port34 Port33

SFP+ Present signal for Port33 to Port 40

0: SFP+ port has been installed
1: SFP+ port has been uninstalled

2.10.9. SFP+_Present_3 (0x08, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE SFP+_PRE
Port48 Port47 Port46 Port45 Port44 Port43 Port42 Port41

SFP+ Present signal for Port 41 to Port 48

0: SFP+ port has been installed
1: SFP+ port has been uninstalled

2.10.10. TX_Fault_1 (0x09, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

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Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault
Port32 Port31 Port30 Port29 Port28 Port27 Port26 Port25

SFP+ TX_Fault status for Port 25 to Port 32

0: SFP+ Transmitter is working well
1: SFP+ Transmit Fault

2.10.11. TX_Fault_2 (0x0A, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault
Port40 Port39 Port38 Port37 Port36 Port35 Port34 Port33

SFP+ TX_Fault status for Port 33 to Port 40

0: SFP+ Transmitter is working well
1: SFP+ Transmit Fault

2.10.12. TX_Fault_3 (0x0B, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault TX_Fault
Port48 Port47 Port46 Port45 Port44 Port43 Port42 Port41

SFP+ TX_Fault status for Port 41 to Port 48

0: SFP+ Transmitter is working well
1: SFP+ Transmit Fault

2.10.13. TX_Disable_1 (0x0C, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+

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Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable
Port32 Port31 Port30 Port29 Port28 Port27 Port26 Port25

SFP+ TX_Disable status for Port 25 to Port 32

0: SFP+ is under transmit enable
1: SFP+ is under transmit disable

2.10.14. TX_Disable_2 (0x0D, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable
Port40 Port39 Port38 Port37 Port36 Port35 Port34 Port33

SFP+ TX_Disable status for Port 33 to Port 40

0: SFP+ is under transmit enable
1: SFP+ is under transmit disable

2.10.15. TX_Disable_3 (0x0E, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable TX_Disable
Port48 Port47 Port46 Port45 Port44 Port43 Port42 Port41

SFP+ TX_Disable status for Port 41 to Port 48

0: SFP+ is under transmit enable
1: SFP+ is under transmit disable

2.10.16. RX_LOSS_1 (0x0F, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS

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Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Port32 Port31 Port30 Port29 Port28 Port27 Port26 Port25

SFP+ RX_LOSS status for Port 25 to Port 32

0: SFP+ Receiver is working well
1: SFP+ Receive Loss

2.10.17. RX_LOSS_2 (0x10, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS
Port40 Port39 Port38 Port37 Port36 Port35 Port34 Port33

SFP+ RX_LOSS status for Port 33 to Port 40

0: SFP+ Receiver is working well
1: SFP+ Receive Loss

2.10.18. RX_LOSS_3 (0x11, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+
RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS RX_LOSS
Port48 Port47 Port46 Port45 Port44 Port43 Port42 Port41

SFP+ RX_LOSS status for Port 41 to Port 48

0: SFP+ Receiver is working well
1: SFP+ Receive Loss

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2.10.19. QSFP+_INT (0x12, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
QSFP+ QSFP+ QSFP+ QSFP+ QSFP+ QSFP+
Reserved Reserved
Port54 Port51 Port53 Port50 Port52 Port49
**(QSFP+ Ports bits update base on front QSFP+ port number definition)**
QSFP+ _INT status for QSFP+ Port 49 to Port 54 [from CPLD]
0: Generates an interrupt when a QSFP+ port is present
1: No interrupt
Note: After Fiber port has been presented, SW need to clear interrupt status from low to high status.

2.10.20. QSFP+_Module_INT (0x13, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

QSFP+ QSFP+ QSFP+ QSFP+ QSFP+ QSFP+
Reserved Reserved
Port54 Port51 Port53 Port50 Port52 Port49
**(QSFP+ Ports bits update base on front QSFP+ port number definition)**
QSFP+ _Module_INT status for QSFP+ Port 49 to Port 54 [from QSFP+ Module]
0: Show QSFP+ module fault or status critical to system.
1: No interrupt
Note: Depend on transceiver supplier support this function or not.

2.10.21. QSFP+_Present (0x14, Read only)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

QSFP+ QSFP+ QSFP+ QSFP+ QSFP+ QSFP+
Reserved Reserved
Port54 Port51 Port53 Port50 Port52 Port49
**(QSFP+ Ports bits update base on front QSFP+ port number definition)**
QSFP+ _Present status for QSFP+ Port 49 to Port 54
0: Show QSFP+ module has been installed
1: No QSFP+ module be installed

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2.10.22. QSFP+_MOD_RST (0x15, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
QSFP+ QSFP+ QSFP+ QSFP+ QSFP+ QSFP+
Reserved Reserved
Port54 Port51 Port53 Port50 Port52 Port49
**(QSFP+ Ports bits update base on front QSFP+ port number definition)**
QSFP+ _MOD_RST status for QSFP+ Port 49 to Port 54
0: Reset QSFP+ module by SW.
1: Normal status
Note: Depend on transceiver supplier support this function or not.

2.10.23. QSFP+_LPMODE (0x16, R/W)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
QSFP+ QSFP+ QSFP+ QSFP+ QSFP+ QSFP+
Reserved Reserved
Port54 Port51 Port53 Port50 Port52 Port49
**(QSFP+ Ports bits update base on front QSFP+ port number definition)**
QSFP+ _LPMODE status for QSFP+ Port 49 to Port 54
0: Set LPMODE in High Power.
1: Set LPMODE in Lowe Power.
Note1: Depend on transceiver supplier support this function or not.
Note2: Need to consider “Power_over-ride” and “Power_set” software control bits.

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3. Switch Sub-System
3.1. Port Mapping
Below are the port mapping between MAC and front port number
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 52
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 53
51 54

Port 49 Port 50 Port 51 Port 52 Port 53 Port 54

LED1
LED 1-4 LED1
LED 1-4 LED1
LED 1-4 LED1
LED 1-4 LED1
LED 1-4 LED1
LED 1-4
QSFP+
QSFP+ Breakout mode LEDs

Port 1~ port48 => SFP+ Port Port 1~port 6 => QSFP+ Port
Figure 6 Front Port Mapping

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Table 10 Switch Port Mapping Table

4. Port LED
The status of port LED will not be affected when the switch is in configuration mode. Each
port has its dedicated LED which build-in with SFP+ connectors. The management port has
dedicated LED to indicate Link and Activity.

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 52
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 53
51 54

Port 49 Port 50 Port 51 Port 52 Port 53 Port 54

LED1
LED 1 -4 LED1
LED 1 -4 LED1
LED 1-4 LED1
LED 1-4 LED1
LED 1-4 LED1
LED 1-4
QSFP+
QSFP+ Breakout mode LEDs

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LED CONDITION STATUS

On/Flashing SFP+ port has a valid link at 10G.
Green Flashing indicates activity.
SFP+ Port LED On/Flashing SFP+ port has a valid link at 1G.
Amber Flashing indicates activity.
Off There is no link on the port.
QSFP+ Port LED in 40G On/Flashing SFP+ port has a valid link at 40G.
Mode Green Flashing indicates activity.
(Port 49~ 54)

Off There is no link on the port.

QSFP+ Port LED in 10G QSFP port has a valid link at 10G via break out
On/Flashing
Mode cable. The LED on 40G QSFP end is also present
Green
(With Breakout cable) OFF. Flashing indicates activity.

Off There is no link on the port.

On Port has a valid link

OOB LED (Link)
Off There is no link on the port
Flashing Flashing indicates activity
OOB LED (Activity)
Off There is no link on the port

Table 11 Port LED Definition

o . Single-color LED will be used for 40G QSFP+ uplink port to indicate link/activity.

There should be four LEDs per QSFP port. These LEDs can represent state of
40GE port or 4 10GE ports when used in breakout mode.

The 40G QSFP+ LED should present OFF while there’s breakout cable plugged
in.

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4.1. Network Port

There are 48 1000/10G SFP+ ports and 6*40G QSFP on the front panel, and 48*10G will
operate in full duplex mode when the speed is 1000/10GMbps. There are two additional
dedicated Gigabit ports at front panel as well.

The SFP+ port will support full duplex mode only. The SFP+ ports should be able to
support the following types of SFP modules:

 10 Gigabit Ethernet SFP+ Options

Standard Diameter (um) Wavelength (nm) Distance

10GBASE-SR Up to 300m link length with 2000 MHz*km MMF
Pre-terminated twin-ax copper cables with link lengths of 1m, 2m, 3m and
10GBASE-CR
5m
10GBase-SR AVAGO AFBR-704SDZ
10GBase-SR Finisar FCBG110SD1C03 Note. (AOC) 3m
10GBase-LR Opnext TRS5020EN-S002
10GBase-CR All Best R-CS-PBB7PBB7-DI-500-G
10GBase-CR FOXCONN HP2008 (Single Loopback)
40GBase-SR4 Finisar FTL410QE1C
40GBase-SR4 Finisar FTL410QE1C
40GBase-CR4 AHSI 599940002

 Not support 10GBASE-LRM Transceiver

 Gigabit Ethernet SFP Options

Wavelength
Standard Diameter (um) Distance
(nm)

1000Base-SX Opnext TRF2716AALB400

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Source Photonics FTM-3012C-SLG

1000Base-LX
(SPGBLXCNFH)

Note. It needs BCM shell commands to enable when using 1G SFP

Table 12 Types of Transceiver Supported

4.2. System LEDs

The system LEDs are used to indicate the status of power and system.

LABEL COLOR DESCRIPTION

Green This power is operating normally.
PS1
PWR present but not power on or this power is
(Power Supply Amber
fault.
Status)
Off Power supply not present.
Green This power is operating normally.
PS2
PWR present but not power on or this power is
(Power Supply Amber
fault.
Status)
Off Power supply not present.
System self-diagnostic test successfully
Green
Diag completed.
(Diagnostic) System self-diagnostic test has detected a fault.
Amber
(Fan, thermal or any interface fault.)

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Green System FAN operating normally.

FAN
Amber Fan tray present buy system FAN is fault.
OFF System OFF
Flashing by remote management command.
Amber Flashing Assists the technician in finding the right device
LOC for service in the rack.
Not a particular switch that technician need to
OFF
find
Table 13 System LED Definition

4.2.1. Fan /Fan’s suggested alternative present/Suggested thermal map

## Fan’s suggested alternative present method :
Due to the fan’s pin definition is without present signal so Accton recommends to use below suggested
alternative way to check fan module is presented or not presented in the system.
( Using Fan speed status to instead of “present” signal by SW. Below is the recommended application)

Note. FAN speed status will be recommended to check “FAN speed” and “FANR speed” together
When both registers of CPLD1 are as “0”, that means this fan slot is under no present condition.

## Suggested system thermal map :

o
1. When (LM75-1 + LM75-2)/2 ≧ 49.5 C, set fan speed from 40% to 65%.
o
2. When (LM75-1 + LM75-2)/2 ≧ 53.0 C, set fan speed from 65% to 80%
o
3. When (LM75-1 + LM75-2)/2 ≦ 42.7 C, set fan speed from 65% to 40%
o
4. When (LM75-1 + LM75-2)/2 ≧ 57.7 C, set fan speed from 80% to 100%
o
5. When (LM75-1 + LM75-2)/2 ≦ 47.7 C, set fan speed from 80% to 65%
o
6. When (LM75-1 + LM75-2)/2 ≦ 52.7 C, set fan speed from 100% to 80%

Default state:

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7. The default FAN speed is 40% under the room temperature with air condition.
8. The system will run full fan speed if there are only four fan modules working well whatever it is
due to FAN faulty or remove one fan module manually.

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System Boot-Up

Set FAN Speed to

40%

Probe Sensor N
T ≧49.
49. 5oC

Set FAN Speed to

65%

N
Probe Sensor N Probe Sensor Y
T ≧53oC T ≦42.
42. 7oC

Set FAN Speed to

80%

N
Probe Sensor N Probe Sensor Y
57. 7oC
T ≧57. 47.7o C
T ≦47.

Set FAN Speed to

100%

N
Probe Sensor Y
T ≦52.
52. 7oC

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4.2.2. Thermal sensor Location

Figure 7 Mainboard thermal location

Table 14 Thermal Sensor mapping table

Sensor# Device I2C Address Location Measurement point

2 LM75#1 0x48 U16 on Mainboard Front middle
3 LM75#2 0x49 U6 on Mainboard Rear right
4 LM75#3 0x4A U15 on Mainboard Front right

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