DFT

( DESIGN FOR TESTABILITY )

 CONTENTS

● ASIC FLOW
● DFT INTRODUCTION
● SOC DFT FLOW
● WHY DFT?
● ROLE OF DFT
● DFT FLOW
ASIC FLOW
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ASIC(Application specific integrated circuit) is designed for a special solo purpose and the function of chip is same
through out the chip life.It's digital circuitry is made up of permanently connected gates and flip flops in silicon so the
logic function can't be changed.

specifications:-

Day by day the technology is increasing and customer also expecting new features(like low power
consumption,high speed) in the device.In this stage the features information which is expecting from the customer is
collected by some marketing people.

Architecture design:-

The architecture team will design an architecture based on the specifications.The architecture is like a block diagram we
can find the all the details which are using in the design(like processors,memories) and how the are connected.This
architecture team will estimate the block area,how much power is required and cost for the design.
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RTL design:-

Register transfer level(RTL) constructing a digital design using combinational and sequential circuit in hardware
description language like verilog or VHDL.The above architecture is converted into verilog or VHDL code.This code
describes how data is transformed as it is passed from register to register

RTL verification:-

It is a functional verification of RTL design.After the RTL design by applying test cases we verify the design in
verification stage.If any mistakes are found then the design is re send to the RTL designing department.The verification
stage will take nearly 60% of the total time.Performing this verification at this stage is most advantageous because
correcting the faults at routing stage is difficult and takes more time.
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Synthesis:-

It is a process of converting the RTL code into gate level netlist.Up to RTL verification the design is technology
independent.In synthesis process the design is converted into technology dependent.it is 3 stage process.

1.Translation:- The RTL code is converted in to Boolean expression.

2.Optimization:- In this stage Boolean expression is optimized by SOP and POS optimization method.

3.Mapping:- In this technology independent Boolean expression is converted into technology dependent and generates
the gate level netlist.

The inputs for synthesis are RTL code, .SDC and .LIB.after the synthesis the generated outputs are gate level netlist and
.SDC.
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DFT:-

Design for testability(DFT) is a technique which facilitates a design to become testable after production.In this stage we put extra
logic along with the design logic during implementation process which helps post production process.The DFT will make the testing
easy at post production process.At this stage an ATPG(automatic test pattern generator) file will generated.

Floorplan:-

The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of
placing blocks/macros in the chip/core area thereby determining routing areas between them.It determines the size of the die and
creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o
,pin/pad placement information.

Placement:-

Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global
placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site
rows(legalize placement).In placement stage we check the congestion value by GRC map.
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CTS (clock tree synthesis):-
In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give
the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay
in order to meet timing and power.
Routing:-
Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this
stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The
global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed
routing the physical connections are done.
Signoff:- After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and
performance of the layout before tapeout.After this the design is converted into GDS II fil

Fabrication:- By the GDS II file information we fabricate the chip.The total design is converted into chip by the manufacturing
process.

Packaging and testing:-

After the fabrication process we test the chip.If there is any fault in the design then we modifies the design by repeating the
steps.If there are no faults then chip will go to packaging.
DFT INTRODUCTION

● Let us assume that size of the chip is about 200,000 equivalent logic gates.
● Whole chip will be running the STA (Static Timing Analysis) to see if the circuit is meeting all the timing
requirements.
● Run the functional test using various test vectors to test the functionality of the device .Once this is done ,we are
almost sure that the chip will function correctly in the field in all the operating conditions .
● When deliver the entire database to the semiconductor vendor has the manufacturing house to fabricate the
chip.When the fabricated chip is soldered on a board in the system,it is expected to do the required function .
● Assume that the board is malfunctioning! Which element would you suspect ?Obviously our device must be the
culprit!
● We checked our device thoroughly using STA and using hundreds of testcases,yet it is causing problems!
● Test design plays a major role .Test design process introduces some additional circuit in the design using which
one can check the device after manufacturing.
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● Types of defects think of in an electrical circuit

● open Circuit or a Short circuit. semiconductor device also there could be shorts or opens between
two points, which may cause malfunctioning Of devices
● These shorts and opens in the transistors manifest as stuck-at-one (ST-1) or stuck-at-zero (ST-0)
faults in a gate or a flop in the chip.
● Other effects like a slow transition of the output of a device
● physical defect, the electrical equivalence and effect on the gate'S
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The first question is what is DFT and why do we need it?

● A simple answer is DFT is a technique, which facilitates a design to become testable after production.
● It's the extra logic which we put in the normal design, during the design process, which helps its post-production
testing.
● Post-production testing is necessary because, the process of manufacturing is not 100% error free.
● To detect manufacturing detects early in the design DFT is needed.
● The DFT techniques are required in order to improve the quality and reduce the test cost of the digital circuit,
while at the same time simplifying the test, debug and diagnose tasks, for testing modem digital circuits.
● Manufacturing testing verifies that your chip does not have manufacturing defects by focusing on circuit structure
rather than functional behavior. Manufacturing defects include problems such as Power or ground shorts
● Open interconnect on the die due to dust particles
● Short circuited source or drain on the transistor due to metal spike-through
● Manufacturing defects might remain undetected by functional testing yet cause undesirable behavior during
circuit operation,
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Verification Testing

● Verifies the correctness of the design ● Tests the correctness of manufactured device
● Done by simulation or formal methods, ● Two step process Test Generation and Test
hardware emulation Application
● Performed only once ● Applied to manufactured device
● Responsible for quality of design ● Responsible for quality of device
● Functional vectors are more ● Test Vectors are Less
● Functional Coverage is Less ● Test Coverage is More
ROLE OF DFT

Controllability:

Ability to place nets, nodes, gates, or sequential elements to a known state.

Observability:

Ability to observe nets, nodes, gates, or sequential elements after they have been driven to a known
logic state
What is manufacturing Test and list down the goals?

The process of detecting defective parts is manufacturing test

The following are the goals of testability:

● Maximization of test coverage

● Maximization of fault coverage
● Minimize the number of test patterns
● Minimization of test time Minimization of test generation effort
● Minimize hardware or software overhead needed for testing
● Make the system self-testing as much as possible
DFT_FLOW
DFT STEPS

● BOUNDRAY SCAN
● MBIST INSERTION
● EDT INSERTION
● OCC INSERTION
● SCAN INSERTION
● ATPG
● SIMULATIONS
SOC DFT Architecture
DFT INSERTED DESIGN
DFT INSERTED DESIGN