A B C D E

1 1

Compal Confidential
2 2

BAUS0 BAUY0
DIS M/B Schematics Document
AMD Stoney SOC with DDR4

AMD R16M-M1-30
2015-12-17
3 3

LA-D541P

REV!
!0.2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
20141107B Date: Thursday, December 17, 2015 Sheet 1 of 43
A B C D E
 A B C D E

YOGA/S series

AMD R16M-M1-30 PCIe x4 Memory Bus CH-A DDR4 SODIMM x1

VRAM(DDR3)*4 2GB DDR4 2133MHz (1.2V)

1 1

eDP Panel eDP x1 USB3.0 x2

2 Lanes USB3.0 Connector x2
x2
AMD Stoney 15W
HDMI Conn. DDI
FP4 968pin BGA USB2.0 x6 USB2.0 Connector (SUB-BOARD)
(USB Charger of TI TPS2546RTER)

SD Card Connector Card Reader Camera

Realtek RTS5220-GR

Touch Panel
(YOGA only)

2 2

RJ45 Conn. LAN PCIE Blue Tooth (WIFI + BT combo)

Realtek RTL8111H NGFF half

Wireless LAN (WIFI + BT combo)

NGFF half Int. Speaker

SPI ROM (8MB) SPI HDA Audio Codec Int. Array Mic x2
W25Q64FVSSIQ Realtek ALC3240

Combo Jack
I2C x2 SATA x1 HDD Conn.
3 3

Touch Panel
(YOGA only)

LPC
Touch Pad

PS2 EC Lid Switch x2

Nuvoton NPCE388NA1DX YOGA x2
S Series x1

YOGA Sub-borad S series Sub-borad I2C x1

I/O Board I/O Board Int. KBD G Sensor x2

(YOGA only)
4 4

Sensor Board
(G sensor,Hall sensor)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTES LIST
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 2 of 43
A B C D E
 A B C D E

Voltage Rails
SIGNAL
STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
Power Plane Description S0 S3 S5
VIN Adapter power supply (20V) ON ON ON Stoney_APU PCB Full ON HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. ON ON ON ZZZ
UAPU1 A9@ DA6001JJ000 S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF
+APU_CORE Core voltage for APU ON OFF OFF SA00009PT00 PCB 1NZ LA-D541P REV0 M/B
S IC ZM2901FY23AC 2.9G BGA 968P SS@
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF ZZZ
1 UAPU1 A6@ DA6001JJ100 1
S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON ON SA00009PU00 PCB 1O0 LA-D541P REV0 M/B
S IC ZM2401AVY23AC 2.5G BGA 968P YOGA@
+3VS 3.3V switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON
UAPU1 E2@
+1.8VS 1.8V switched power rail ON OFF OFF SA00009PV00
S IC ZM2001AVY23AC 2.1G BGA 968P
USB OC MAPPING
+0.95VALW 0.95V always on power rail ON ON ON
OC# USB Port
+0.95VS 0.95V switched power rail ON OFF OFF
+1.2V 1.2V power rail for APU and DDR ON ON OFF BARCODE 0 USB20 port0
+2.5V 2.5V power rail for DDR ON ON OFF 1 USB20 port6,7 USB30 port2,3
ZZZ1 @ ZZZ3 @
+1.5VS 1.5V switched power rail ON OFF OFF 2
+3VGS 3.3V switched power rail for VGA ON OFF OFF 3
+1.8VGS 1.8V switched power rail for VGA ON OFF OFF
BARCODE_8X8 BARCODE_12X4
+1.5VGS 1.5V switched power rail for VGA ON OFF OFF BOM Structure Table
+0.95VGS 0.95V switched power rail for VGA ON OFF OFF
ZZZ2 @ ZZZ9 @
BOM Structure Item
+5VALW 5V always on power rail ON ON ON
45@ For HDMI Logo
+5VS 5V switched power rail ON OFF OFF
UMA@ For UMA
2
+RTC_APU RTC power ON ON ON 2
DIS@ For DIS
+0.6VS 0.6V switched power rail for DDR terminator ON OFF OFF BARCODE_20X4 BARCODE_10X10
EMI@ EMI pop componemt
+0.775VALW* 0.775V always on power rail OFF* ON* ON*
@EMI@ EMI Unpop component
ESD@ ESD pop component

Vinafix
@ESD@ ESD Unpop component
RFS@ S-series RF componemt
APU PCIE PORT LIST RFY@ YOGA RF componemt
Port Device ME@ ME part
EX_THM@ For thermal sensor componemt
GPP0 Card Reader
KBL@ Keyboard backlight
GPP1 LAN NOKBL@ Non-Keyboard backlight
GPP2 WLAN
X76@ X76 part
GPP3 A9@ A9 CPU
A6@ A6 CPU
E2@ E2 CPU
SS@ For S series
3 3
YOGA@ For YOGA
8111H@ For 8111H
GIGA@ For GIGA LAN
100@ For 100 LAN
USB Port Table @ Unpop
H2G@ For HYNIX 2G VRAM
EC SM Bus1 address EC SM Bus2 address 3 External
USB 2.0 USB 3.0 Port S2G@ For SAMSUNG 2G VRAM
USB Port
Device Address HEX Device Address HEX M2G@ For MICRON 2G VRAM
0 USB2.0 (Charger) RF pop component
Smart Battery 0001 011X b 16H Thermal Sensor 1001 101X b 9AH RF@
1 Touch Screen RF Unpop component
Charger 0001 0010 b 12H SB-TSI (APU) 1001 100X b 98H @RF@
2 WLAN/BT Combo
VGA Internal Thermal 1000 001X b
3 Camera
82H
4
5
2 6 USB3.0
XHCI
3 7 USB3.0
4
APU 4

SM Bus address
Device Address HEX
DDR DIMM1 1010 001Xb A2H Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NOTES LIST
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 3 of 43
A B C D E
 5 4 3 2 1

Power up Sequencing S0 TO S3 TO S0

Power up Sequencing G3 TO S0

D D

C C

B B

Power on Sequence required:

1. There is no sequencing requirement between power supplies within the individual power groups.

2. All power supplies in Group A must be stable and within specifications for 5 seconds before any power supply in Power sequenceing
Group B is greater than 10% of its specified minimum operating voltage.

3. All power supplies in Group B must be stable and within specifications before any power supply in Power sequencing Group C is

greater than 10% of its specified minimum operating voltage.

4. All power supplies in Group C must be stable and within specifications before any power supply in Power sequencing Group D is

greater than 10% of its specified minimum operating voltage.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 4 of 43
5 4 3 2 1
 5 4 3 2 1

UAPU1B
D D
PCIE

U10 P_GPP_RXP[0] P_GPP_TXP[0] R1 PCIE_ATX_DRX_P0 CC135 1 2 0.1U_0201_10V6K

<27> PCIE_DTX_C_ARX_P0 U9 R2 1 2 PCIE_ATX_C_DRX_P0 <27>
Card Reader P_GPP_RXN[0] P_GPP_TXN[0] PCIE_ATX_DRX_N0 CC134 0.1U_0201_10V6K Card Reader
<27> PCIE_DTX_C_ARX_N0 PCIE_ATX_C_DRX_N0 <27>
T6 P_GPP_RXP[1] P_GPP_TXP[1] R4 PCIE_ATX_DRX_P1 CC17 1 2 0.1U_0201_10V6K
<28> PCIE_DTX_C_ARX_P1 T5 R3 1 2 PCIE_ATX_C_DRX_P1 <28>
LAN P_GPP_RXN[1] P_GPP_TXN[1] PCIE_ATX_DRX_N1 CC18 0.1U_0201_10V6K LAN
<28> PCIE_DTX_C_ARX_N1 PCIE_ATX_C_DRX_N1 <28>
T9 P_GPP_RXP[2] P_GPP_TXP[2] N1 PCIE_ATX_DRX_P2 CC19 1 2 0.1U_0201_10V6K
<24> PCIE_DTX_C_ARX_P2 PCIE_ATX_C_DRX_P2 <24>
WLAN T8 P_GPP_RXN[2] P_GPP_TXN[2] N2 PCIE_ATX_DRX_N2 CC20 1 2 0.1U_0201_10V6K WLAN
<24> PCIE_DTX_C_ARX_N2 PCIE_ATX_C_DRX_N2 <24>
P7 P_GPP_RXP[3] P_GPP_TXP[3] N4
P6 P_GPP_RXN[3] P_GPP_TXN[3] N3
Type1&3: 196 ohm PD
Type1&3: 196 ohm +0.95VS RC1 1 2 196_0402_1% P_ZVDDP U7 P_ZVDDP P_ZVSS/P_RX_ZVDDP U6 P_ZVSS RC3 1 2 196_0402_1% Type2: 1 k ohm PU
Type2: 1.69 k ohm
DIS@
P10 P_GFX_RXP[0] P_GFX_TXP[0] M2 PCIE_PTX_DRX_P0 CC7 1 2 0.22U_0402_6.3V6K
<13> PCIE_PRX_DTX_P0 PCIE_PTX_C_DRX_P0 <13>
<13> PCIE_PRX_DTX_N0 P9 P_GFX_RXN[0] P_GFX_TXN[0] M1 PCIE_PTX_DRX_N0 CC8 1 2 0.22U_0402_6.3V6K
PCIE_PTX_C_DRX_N0 <13>
DIS@ DIS@
GPU <13> PCIE_PRX_DTX_P1
N6
N5
P_GFX_RXP[1] P_GFX_TXP[1] L1
L2
PCIE_PTX_DRX_P1
PCIE_PTX_DRX_N1
CC9
CC10
1
1
2 0.22U_0402_6.3V6K
2 0.22U_0402_6.3V6K
PCIE_PTX_C_DRX_P1 <13> GPU
P_GFX_RXN[1] P_GFX_TXN[1]
C <13> PCIE_PRX_DTX_N1 PCIE_PTX_C_DRX_N1 <13> C

N9 P_GFX_RXP[2] P_GFX_TXP[2] L4 DIS@

N8 P_GFX_RXN[2] P_GFX_TXN[2] L3

L7 P_GFX_RXP[3] P_GFX_TXP[3] J1
L6 P_GFX_RXN[3] P_GFX_TXN[3] J2

L10 P_GFX_RXP[4] P_GFX_TXP[4] J4

L9 P_GFX_RXN[4] P_GFX_TXN[4] J3

K6 P_GFX_RXP[5] P_GFX_TXP[5] H2
K5 H1
Port4~Port7 P_GFX_RXN[5] P_GFX_TXN[5]

Not support in Type3. K9

K8
P_GFX_RXP[6] P_GFX_TXP[6] G1
G2
P_GFX_RXN[6] P_GFX_TXN[6]

J7 P_GFX_RXP[7] P_GFX_TXP[7] G4
J6 P_GFX_RXN[7] P_GFX_TXN[7] G3

FP4 REV 0.93

FP4_BGA968
B @ B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP4 PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 5 of 43
5 4 3 2 1
 5 4 3 2 1
UAPU1A UAPU1I
<12> DDRAB_SMA[0..13] DDRAB_SDQ[0..63] <12>
MEMORY A MEMORY B
AE28 MA_ADD[0] MA_DATA[0] H17 DDRAB_SMA0 AG31 MB_ADD[0] MB_DATA[0] A25 DDRAB_SDQ0
Y27 MA_ADD[1] MA_DATA[1] J17 DDRAB_SMA1 AC30 MB_ADD[1] MB_DATA[1] C25 DDRAB_SDQ1
Y29 MA_ADD[2] MA_DATA[2] F20 DDRAB_SMA2 AC31 MB_ADD[2] MB_DATA[2] C27 DDRAB_SDQ2
Y26 MA_ADD[3] MA_DATA[3] H20 DDRAB_SMA3 AB32 MB_ADD[3] MB_DATA[3] D27 DDRAB_SDQ3
W 28 MA_ADD[4] MA_DATA[4] E17 DDRAB_SMA4 AA32 MB_ADD[4] MB_DATA[4] B24 DDRAB_SDQ4
W 29 MA_ADD[5] MA_DATA[5] F17 DDRAB_SMA5 AA33 MB_ADD[5] MB_DATA[5] B25 DDRAB_SDQ5
W 26 MA_ADD[6] MA_DATA[6] K18 DDRAB_SMA6 AA31 MB_ADD[6] MB_DATA[6] B27 DDRAB_SDQ6
U29 MA_ADD[7] MA_DATA[7] E20 DDRAB_SMA7 Y33 MB_ADD[7] MB_DATA[7] A27 DDRAB_SDQ7
W 25 MA_ADD[8] DDRAB_SMA8 AA30 MB_ADD[8]
U26 MA_ADD[9] MA_DATA[8] A21 DDRAB_SMA9 W 32 MB_ADD[9] MB_DATA[8] A29 DDRAB_SDQ8
AG29 MA_ADD[10] MA_DATA[9] C21 DDRAB_SMA10 AG32 MB_ADD[10] MB_DATA[9] C29 DDRAB_SDQ9
U27 MA_ADD[11] MA_DATA[10] C23 DDRAB_SMA11 Y32 MB_ADD[11] MB_DATA[10] B32 DDRAB_SDQ10
D D
T28 MA_ADD[12] MA_DATA[11] D23 DDRAB_SMA12 W 33 MB_ADD[12] MB_DATA[11] D32 DDRAB_SDQ11
AK26 MA_ADD[13] MA_DATA[12] B20 DDRAB_SMA13 AL31 MB_ADD[13] MB_DATA[12] B28 DDRAB_SDQ12
T26 MA_ADD[14]/MA_BG[1] MA_DATA[13] B21 <12>
W 30 MB_ADD[14]/MB_BG[1] MB_DATA[13] B29 DDRAB_SDQ13
DDRAB_BG1
T25 MA_ADD[15]/MA_ACT_L MA_DATA[14] B23 <12>
V32 MB_ADD[15]/MB_ACT_L MB_DATA[14] A31 DDRAB_SDQ14
DDRAB_ACT#
MA_DATA[15] A23 MB_DATA[15] C31 DDRAB_SDQ15

MA_DATA[16] G22 MB_DATA[16] E30 DDRAB_SDQ16

AG26 MA_BANK[0] MA_DATA[17] H22 <12> DDRAB_SBS0#
AH32 MB_BANK[0] MB_DATA[17] E31 DDRAB_SDQ17
AG27 MA_BANK[1] MA_DATA[18] E25 <12> DDRAB_SBS1#
AG33 MB_BANK[1] MB_DATA[18] G33 DDRAB_SDQ18
T29 MA_BANK[2]/MA_BG[0] MA_DATA[19] G25 <12> DDRAB_BG0
W 31 MB_BANK[2]/MB_BG[0] MB_DATA[19] G32 DDRAB_SDQ19
MA_DATA[20] J20 <12> DDRAB_SDM[0..7] MB_DATA[20] C33 DDRAB_SDQ20
E19 MA_DM[0] MA_DATA[21] E22 DDRAB_SDM0 D25 MB_DM[0] MB_DATA[21] D33 DDRAB_SDQ21
D21 MA_DM[1] MA_DATA[22] H23 DDRAB_SDM1 D29 MB_DM[1] MB_DATA[22] G30 DDRAB_SDQ22
K21 MA_DM[2] MA_DATA[23] J23 DDRAB_SDM2 E33 MB_DM[2] MB_DATA[23] G31 DDRAB_SDQ23
F29 MA_DM[3] DDRAB_SDM3 J33 MB_DM[3]
AP28 MA_DM[4] MA_DATA[24] F26 DDRAB_SDM4 AR30 MB_DM[4] MB_DATA[24] J30 DDRAB_SDQ24
AV26 MA_DM[5] MA_DATA[25] E27 DDRAB_SDM5 AW 30 MB_DM[5] MB_DATA[25] J31 DDRAB_SDQ25
AR22 MA_DM[6] MA_DATA[26] J26 DDRAB_SDM6 BC30 MB_DM[6] MB_DATA[26] L33 DDRAB_SDQ26
BC22 MA_DM[7] MA_DATA[27] J27 MB_DM[8] DDRAB_SDM7 BC26 MB_DM[7] MB_DATA[27] L32 DDRAB_SDQ27
K29 MA_DM[8] MA_DATA[28] H25 N33 MB_DM[8] MB_DATA[28] H32 DDRAB_SDQ28
MA_DATA[29] E26 Not support in Type3. MB_DATA[29] H33 DDRAB_SDQ29
H19 MA_DQS_H[0] MA_DATA[30] G28 B26 MB_DQS_H[0] MB_DATA[30] L30 DDRAB_SDQ30
<12> DDRAB_SDQS0
G19 MA_DQS_L[0] MA_DATA[31] G29 A26 MB_DQS_L[0] MB_DATA[31] L31 DDRAB_SDQ31
<12> DDRAB_SDQS#0
B22 MA_DQS_H[1] B30 MB_DQS_H[1]
<12> DDRAB_SDQS1
A22 MA_DQS_L[1] MA_DATA[32] AN26 A30 MB_DQS_L[1] MB_DATA[32] AN31 DDRAB_SDQ32
<12> DDRAB_SDQS#1
F23 MA_DQS_H[2] MA_DATA[33] AP29 F32 MB_DQS_H[2] MB_DATA[33] AP32 DDRAB_SDQ33
<12> DDRAB_SDQS2
E23 MA_DQS_L[2] MA_DATA[34] AR26 E32 MB_DQS_L[2] MB_DATA[34] AT32 DDRAB_SDQ34
<12> DDRAB_SDQS#2
G27 MA_DQS_H[3] MA_DATA[35] AP24 K32 MB_DQS_H[3] MB_DATA[35] AU32 DDRAB_SDQ35
<12> DDRAB_SDQS3
F27 MA_DQS_L[3] MA_DATA[36] AN29 J32 MB_DQS_L[3] MB_DATA[36] AN33 DDRAB_SDQ36
<12> DDRAB_SDQS#3
C AP25 MA_DQS_H[4] MA_DATA[37] AN27 AR32 MB_DQS_H[4] MB_DATA[37] AN32 DDRAB_SDQ37 C
<12> DDRAB_SDQS4
AP26 MA_DQS_L[4] MA_DATA[38] AR29 AR33 MB_DQS_L[4] MB_DATA[38] AR31 DDRAB_SDQ38
<12> DDRAB_SDQS#4
AW 27 MA_DQS_H[5] MA_DATA[39] AR27 AW 32 MB_DQS_H[5] MB_DATA[39] AT33 DDRAB_SDQ39
<12> DDRAB_SDQS5
AV27 MA_DQS_L[5] AW 33 MB_DQS_L[5]
<12> DDRAB_SDQS#5
AV22 MA_DQS_H[6] MA_DATA[40] AU26 BA29 MB_DQS_H[6] MB_DATA[40] AU30 DDRAB_SDQ40
<12> DDRAB_SDQS6
AU22 MA_DQS_L[6] MA_DATA[41] AV29 AY29 MB_DQS_L[6] MB_DATA[41] AV32 DDRAB_SDQ41
<12> DDRAB_SDQS#6
BA21 MA_DQS_H[7] MA_DATA[42] AU25 BA25 MB_DQS_H[7] MB_DATA[42] BA33 DDRAB_SDQ42
<12> DDRAB_SDQS7
AY21 MA_DQS_L[7] MA_DATA[43] AW 25 AY25 MB_DQS_L[7] MB_DATA[43] AY32 DDRAB_SDQ43
<12> DDRAB_SDQS#7
L27 MA_DQS_H[8] MA_DATA[44] AU29 P32 MB_DQS_H[8] MB_DATA[44] AU33 DDRAB_SDQ44
L26 MA_DQS_L[8] MA_DATA[45] AU28 MB_DQS_H[8],MB_DQS_L[8] N32 MB_DQS_L[8] MB_DATA[45] AU31 DDRAB_SDQ45
MA_DATA[46] AW 26 Not support in Type3. MB_DATA[46] AW 31 DDRAB_SDQ46
AE25 MA_CLK_H[0] MA_DATA[47] AT25 AE33 MB_CLK_H[0] MB_DATA[47] AY33 DDRAB_SDQ47
<12> DDRA_CLK0
AE26 MA_CLK_L[0] AE32 MB_CLK_L[0]
<12> DDRA_CLK0#
AD26 MA_CLK_H[1] MA_DATA[48] AV23 AE30 MB_CLK_H[1] MB_DATA[48] BC31 DDRAB_SDQ48
<12> DDRA_CLK1
AD27 MA_CLK_L[1] MA_DATA[49] AW 23 AE31 MB_CLK_L[1] MB_DATA[49] BB30 DDRAB_SDQ49
<12> DDRA_CLK1#
AB28 MA_CLK_H[2] MA_DATA[50] AV20 AD32 MB_CLK_H[2] MB_DATA[50] BB28 DDRAB_SDQ50
AB29 MA_CLK_L[2] MA_DATA[51] AW 20 AD33 MB_CLK_L[2] MB_DATA[51] AY27 DDRAB_SDQ51
AB25 MA_CLK_H[3] MA_DATA[52] AR23 AC33 MB_CLK_H[3] MB_DATA[52] BB32 DDRAB_SDQ52
AB26 MA_CLK_L[3] MA_DATA[53] AT23 AC32 MB_CLK_L[3] MB_DATA[53] BA31 DDRAB_SDQ53
MA_DATA[54] AR20 MB_DATA[54] BC29 DDRAB_SDQ54
N29 MA_RESET_L MA_DATA[55] AT20 <12> MEM_MAB_RST# MEM_MAB_RST# T33 MB_RESET_L MB_DATA[55] BB29 DDRAB_SDQ55
AE29 MA_EVENT_L
<12> MEM_MAB_EVENT# AG30 MB_EVENT_L
MA_DATA[56] BB23 MB_DATA[56] BB27 DDRAB_SDQ56
P27 MA_CKE0 MA_DATA[57] BB22 DDRAB_CKE0 U32 MB_CKE0 MB_DATA[57] BB26 DDRAB_SDQ57
<12> DDRAB_CKE0
P29 MA_CKE1 MA_DATA[58] BB20 DDRAB_CKE1 U33 MB_CKE1 MB_DATA[58] BB24 DDRAB_SDQ58
<12> DDRAB_CKE1
MA_DATA[59] AY19 MB_DATA[59] AY23 DDRAB_SDQ59
MA_DATA[60] BA23 MB_DATA[60] BA27 DDRAB_SDQ60
MA_DATA[61] BC23 MB_DATA[61] BC27 DDRAB_SDQ61
AK27 MA0_ODT[0] MA_DATA[62] BC21 AL30 MB0_ODT[0] MB_DATA[62] BC25 DDRAB_SDQ62
<12> DDRA_ODT0
AL26 MA0_ODT[1] MA_DATA[63] BB21 AM32 MB0_ODT[1] MB_DATA[63] BB25 DDRAB_SDQ63
B <12> DDRA_ODT1 B
AH25 MA1_ODT[0] AJ32 MB1_ODT[0]
AL25 MA1_ODT[1] MA_CHECK[0] K26 AM33 MB1_ODT[1] MB_CHECK[0] N30
MA_CHECK[1] K28 MB_CHECK[1] N31
AH26 N26 AJ33 R33
AL29
MA0_CS_L[0]
MA0_CS_L[1]
MA_CHECK[2]
MA_CHECK[3] N28
<12> DDRA_SCS0#
<12> DDRA_SCS1#
AL32
MB0_CS_L[0]
MB0_CS_L[1]
MB_CHECK[2]
MB_CHECK[3] R32 MB_CHECK[0]~MB_CHECK[7]
AH29
AL28
MA1_CS_L[0]
MA1_CS_L[1]
MA_CHECK[4]
MA_CHECK[5]
J29
K25
AJ30
AL33
MB1_CS_L[0]
MB1_CS_L[1]
MB_CHECK[4]
MB_CHECK[5]
M32
M33
Not support in Type3.
MA_CHECK[6] L29 MB_CHECK[6] R30
MA_CHECK[7] N25 MB_CHECK[7] R31
AG24 MA_RAS_L/MA_RAS_L_ADD[16] <12>
AH33 MB_RAS_L/MB_RAS_L_ADD[16]
DDRAB_SRAS#
AK29 MA_CAS_L/MA_CAS_L_ADD[15] <12>
AK32 MB_CAS_L/MB_CAS_L_ADD[15]
DDRAB_SCAS#
AH28 MA_WE_L/MA_WE_L_ADD[14] <12> AJ31 MB_WE_L/MB_WE_L_ADD[14]
DDRAB_SWE#

B19 MA_VREFDQ MA_ZVDDIO_MEM_S AD29 A19 MB_VREFDQ MB_ZVDDIO_MEM_S AF32 MEM_MB_ZVDDIO 1 2

+1.2V
+MEM_VREF
T32 M_VREF RC4
39.2_0402_1%
FP4 REV 0.93 FP4 REV 0.93

@ FP4_BGA968 @ FP4_BGA968

+1.2V RPC1 +MEM_VREF

MEM_MAB_RST#
1 8
CLOSE TO APU

100P_0402_50V8J
2 7 CC16 1
3 6 MEM_MAB_EVENT#
4 5
1
CC21
1
CC22 @ESD@
close to CPU
1K_0804_8P4R_1% 0.1U_0201_10V6K 1000P_0402_50V7K 2
A 2 2 A

MEMORY VREF
ESD
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP4 MEMORY INTERFACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 6 of 43
5 4 3 2 1
 A B C D E

+3VS
DP_VARY_BL, DP_BLON, DP_DIGON:
Type1&3--> VDD_18

2
+1.8VS
UAPU1C
Type2--> VDD_33 RC7

5
DISPLAY/SVI2/JTAG/TEST
UC5 2.2K_0402_5%
1

1
B6 A9 DP_ZVSS RC6 1 2 2K_0402_1% NC 4
DP2_TXP[0] DP_ZVSS
Y ENBKL <20,30>
A6 DP2_TXN[0] DP_AUX_ZVSS B9 DP_AUX_ZVSS RC8 1 2 150_0402_1% ENBKL_R 2
A

G
DP_BLON G5 ENBKL_R
D7 G6 ENVDD_R NL17SZ07DFT2G_SC70-5
DP2 is not support on DP2_TXP[1] DP_DIGON

3
C7 DP2_TXN[1] DP_VARY_BL F11 INVT_PWM_R SA00004BV00

FP4 Type 2 processors. A7 DP2_TXP[2]

B7 DP2_TXN[2] DP2_AUXP H9 @
DP2_AUXN G9 RC9 1 2 0_0402_5%
1 1
D9 DP2_TXP[3] DP2_HPD E9
C9 DP2_TXN[3]
DP1_AUXP F7
A2 E7 HDMICLK_NB <21>
DP1_TXP[0] DP1_AUXN RC10 1 2 0_0402_5%
<21> HDMI_TX2+_CK HDMIDAT_NB <21>
A3 DP1_TXN[0] DP1_HPD F5
<21> HDMI_TX2-_CK HDMI_HPD <21>

D
B4 DP1_TXP[1] DP0_AUXP F8 EDP_HPD_APU 3 1
<21> HDMI_TX1+_CK EDP_AUXP <20> EDP_HPD <20>
A4 DP1_TXN[1] DP0_AUXN E8 @ RPC2
<21> HDMI_TX1-_CK G8 EDP_AUXN <20> +3VALW 8 1
EDP_HPD_APU QC2 MESS138W-G_SOT323-3
HDMI D5
DP0_HPD
ENBKL_R 7 2

G
DP1_TXP[2]
<21> HDMI_TX0+_CK

2
C5 DP1_TXN[2] RSVD_1 K24 CORETYPE 1 @ 2 ENVDD_R 6 3
<21> HDMI_TX0-_CK +1.8VS +3VS
TEMPIN0 E15 RC11 100K_0402_5% EDP_HPD_APU 5 4
+1.8VS A5 DP1_TXP[3] TEMPIN1 E14 TEMPIN0,TEMPIN1,TEMPIN2,TEMPINRETURN
<21> HDMI_CLK+_CK B5 E12 +1.8VS
@ RPC3 DP1_TXN[3] TEMPIN2 Not support in Type3. 100K_0804_8P4R_5%
<21> HDMI_CLK-_CK

2
8 1 APU_SVT TEMPINRETURN F14
7 2 E2 DP0_TXP[0] TEST410 AK24 APU_TEST410 RC14
<20> EDP_TXP0 TPC6

5
6 3 APU_SVD E1 DP0_TXN[0] TEST411 AL24 APU_TEST411 UC4 4.7K_0402_5%
<20> EDP_TXN0 TPC7
5 4 APU_SVC P24 APU_TEST4 1
eDP TEST4

P
TPC8 NC
E3 DP0_TXP[1] TEST5 N24 APU_TEST5 4
<20> EDP_TXP1 TPC9 SOC_ENVDD <20,30>

1
1K_0804_8P4R_5% E4 TEST6 AN24 APU_TEST6 ENVDD_R 2 Y
DP0_TXN[1] TPC10
<20> EDP_TXN1 A

G
TEST9 AB8 APU_TEST9 TPC11
D1 DP0_TXP[2] TEST10 Y9 APU_TEST10 NL17SZ07DFT2G_SC70-5
TPC12

3
D2 DP0_TXN[2] TEST14 B10 APU_TEST14 SA00004BV00
TEST15 D11 APU_TEST15 TPC13
C1 DP0_TXP[3] TEST16 A10 APU_TEST16
Place resistor(0ohm) for SVT in PWR side B1 DP0_TXN[3] TEST17 C11 APU_TEST17 +3VS
TEST11 B11 APU_TEST11 @
APU_SVT C15 SVT0 TEST18 A14 APU_TEST18 RC13 1 2 0_0402_5%
<38> APU_SVT

2
RC127 1 2 0_0402_5% APU_SVC_R D17 SVC0 TEST19 B14 APU_TEST19
<38> APU_SVC +1.8VS
RC128 1 2 0_0402_5% APU_SVD_R D19
For SIC, SID, ALERT_L, <38> APU_SVD SVD0
RC20
PROCHOT_L SVC1, SVD1, SVT1 B15 SVT1 TEST28_H A13 APU_TEST28_H TPC14 4.7K_0402_5%

5
B16 B13 APU_TEST28_L UC2
Type1&3: Each are pulled SVC1 TEST28_L
TPC15

1
Not support in Type3. A18 TEST31 P26 APU_TEST31 1

P
SVD1 TPC16 NC
up to VDD_18 APU_SIC B18 SIC
DP_STEREOSYNC/TEST36

TEST37
E11
A17
DP_STEREOSYNC
APU_TEST37 INVT_PWM_R 2 Y
4 INVT_PWM
INVT_PWM <20>
TPC30
Type2: Each are pulled up A

G
APU_SID C17 SID
NL17SZ07DFT2G_SC70-5
2
to VDD_33 2

3
2
RC17
+1.8VS RC21 1 2 300_0402_5% APU_RST# D15 RESET_L SA00004BV00
+1.8VS RC22 1 2 300_0402_5% APU_PWRGD C19 PWROK

<38> APU_PWRGD A15 PROCHOT_L

+1.8VS <30> H_PROCHOT#

10K_0402_5%
APU_ALERT# B17 ALERT_L TPC28

1
VDDCR_GFX_SENSE H11
TPC29
APU_TDI H15 TDI VDDCR_NB_SENSE J12
APU_VDDNB_SEN <38>
APU_TDO H14 TDO VDDCR_CPU_SENSE G12
D13 AY18 APU_VDD_SEN <38>
RPC5 APU_TCK TCK VDDP_SENSE VDDP_SENSE TPC21
8 1 APU_SID APU_TMS G15 TMS TPC27
7 2 APU_ALERT# APU_TRST# J14 TRST_L VSS_SENSE H12
APU_VDD_RUN_FB_L <38>
6 3 APU_SIC APU_DBRDY C13 DBRDY
5 4 H_PROCHOT# APU_DBREQ# A11 DBREQ_L

1K_0804_8P4R_5%

FP4 REV 0.93

FP4_BGA968
@

DP_STEREOSYNC:
APU_TEST17 8
@ RPC6
1
checklist-->PD
APU_TEST11 7 2 check with AMD-->PU
APU_TEST16 6 3
APU_TEST14 5 4

1K_0804_8P4R_5% DP_STEREOSYNC 1 2 +1.8VS

+3VS RC27
1K_0402_5%

RC109 1 2 2.2K_0402_5% EC_SMB_CK2 APU_PWRGD

@
RC111 1 2 2.2K_0402_5% EC_SMB_DA2 APU_RST# 1 2
RC31
100P_0402_50V8J

3 +1.8VS 3
1K_0402_5%
100P_0402_50V8J

ESD@ 1 ESD@ 1
CC126 CC127
2
G

2 2
EC_SMB_CK2 1 3 APU_SIC
<14,25,30> EC_SMB_CK2
D

QC4
MESS138W-G_SOT323-3
ESD
2
G

EC_SMB_DA2 1 3 APU_SID
<14,25,30> EC_SMB_DA2
HDT+
D

+1.8VS
QC5 MESS138W-G_SOT323-3 JHDT1 @
1 2 APU_TCK
1 2 +1.8VS
3 4 APU_TMS RPC8
3 4 APU_DBREQ# 1 8
5 6 APU_TDI APU_TDI 2 7
5 6 APU_TCK 3 6
7 8 APU_TDO APU_TMS 4 5
7 8
APU_TRST# 1 2 APU_TRST#_R 9 10 APU_PWRGD 1K_0804_8P4R_5%
RC34 33_0402_5% 9 10
RPC9 HDT_P11 11 12 APU_RST# +1.8VS
1 8 11 12 RPC10
2 7 HDT_P13 13 14 APU_DBRDY 1 8
3 6 13 14 APU_TRST# 2 7
4 5 HDT_P15 15 16 APU_DBREQ# APU_TEST18 3 6
15 16 APU_TEST19 4 5
10K_0804_8P4R_5% 17 18 APU_TEST19
17 18 1K_0804_8P4R_5%
19 20 APU_TEST18 APU_TRST# 1 2
19 20
@ CC23
4 0.01U_0402_16V7K 4
SAMTE_ASP-136446-07-B

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP4 DISP/MISC/HDT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 7 of 43
A B C D E
 A B C D E

1 2 RC57 +3VS
CC24 150P_0402_50V8J
UAPU1D
ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
10K_0402_5%
1 2 MB_ID 32.768KMHz CRYSTAL
RC36 1 2 33_0402_5% LPC_RST_A# BB12 LPC_RST_L SD0_WP/EGPIO101 BB2 MB_ID SS@ 32K_X1
<30> LPC_RST#
RC38 1 2 33_0402_5%APU_PCIE_RST#_R AN7 PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 BB5
<13,24,27,28> APU_PCIE_RST#
SD0_CD/AGPIO25 BC2 1 YOGA@ 2
1 2 EC_RSMRST#_R AE4 RSMRST_L SD0_CLK/EGPIO95 BB4 S: HIGH
CC25 150P_0402_50V8J AY5 RC58
SD0_CMD/EGPIO96
YOGA: LOW

1
AE1 PWR_BTN_L/AGPIO0 10K_0402_5%
<30> PBTN_OUT#
PW R_GOOD_APU BC9 PWR_GOOD YC1
SYS_RST# AF2 SYS_RESET_L/AGPIO1 SENSOR_EC_INT <30> 32.768KHZ 9PF 20PPM CM7V-T1A9.0PF20PPM
APU_PCIE_W AKE# AG2 WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BC3
<24> APU_PCIE_W AKE# BT_OFF# <24>

2
SD0_DATA1/EGPIO98 BA3 RPC16 +3VALW
W LAN_OFF# <24>
1 AK7 SLP_S3_L SD0_DATA2/EGPIO99 BC5 1
<30> PM_SLP_S3#
AH5 SLP_S5_L SD0_DATA3/EGPIO100 BA5 S0A3_GPIO1 8
<30,33> PM_SLP_S5#
SD0_LED/EGPIO93 BB6 AGPIO40 2 7 2 1 32K_X2
S0A3_GPIO AE8 S0A3_GPIO/AGPIO10 AGPIO5 3 6 RC84
RPC15 AH8 SCL0/I2C2_SCL/EGPIO113 BA15 APU_SCLK0 AGPIO8 4 5 20M_0402_5%
1 8
<10> S5_MUX_CTRL
S5_MUX_CTRL/EGPIO42

SDA0/I2C2_SDA/EGPIO114 AY17 APU_SDATA0

APU_SCLK0 <12>
APU_SDATA0 <12>
DDR 1 1
2 7 APU_TEST0 AH6 TEST0 10K_0804_8P4R_5%
3 6 APU_TEST1 AK8 SCL1/I2C3_SCL/AGPIO19 AG5 APU_SCLK1 CC28 CC29
4 5 APU_TEST2 AE3
TEST1/TMS
TEST2 SDA1/I2C3_SDA/AGPIO20 AG4 APU_SDATA1
Touch Pad 22P_0402_50V8J 22P_0402_50V8J
2 2
15K_0804_8P4R_5% AY15
<30> KB_RST#
<30> GATEA20
BC19
ESPI_RESET_L/KBRST_L/AGPIO129
GA20IN/AGPIO126 port0: S0 domain BOT side
AD7 AL5 MEM_VOLT_SEL1
<30> EC_SCI#
BB13
LPC_PME_L/AGPIO22
LPC_SMI_L/AGPIO86
AGPIO3
AGPIO4 AL6 port1: S5 domain
AJ1 AGPIO5 +3VALW +3VS
AG3 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23
AGPIO5
AGPIO6/LDT_RST AJ3 SMBUS Port1: Touch Pad
AD5 IR_TX0/USB_OC5_L/AGPIO13 AGPIO7/LDT_PWROK AH1
AL8 AJ4 AGPIO8

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
IR_TX1/USB_OC6_L/AGPIO14 AGPIO8

1
AN8 IR_RX1/AGPIO15 AGPIO9 AK5 GPIO39:
AE2 AD8

RC66

RC67

RC144

RC145
IR_LED_L/LLB_L/AGPIO12 VDDGFX_PD/AGPIO39
BC15 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40 AG8 AGPIO40 Not support in Type3.
<27> CR_CLKREQ#
BB17 CLK_REQ1_L/AGPIO115 AGPIO64 AW15
<28> LAN_CLKREQ#

2
BC17 CLK_REQ2_L/AGPIO116 AGPIO65 AU15
<24> W LAN_CLKREQ#

2
BB18 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
RC131 1 @ 2 0_0402_5% VGA_CLKREQ#_R BB16 CLK_REQG_L/OSCIN/EGPIO132 AGPIO66/SHUTDOWN_L AT15 APU_SCLK1 6 1
<14> VGA_CLKREQ# APU_SCLK1_TP <26>
AH9 USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK AU12
<27> USB_OC0#
AG1 USB_OC1_L/TDI/AGPIO17 AGPIO69/SGPIO_LOAD AT14 QC17A
<27> USB_OC1#

5
AH2 AR14
PXS_RST# <13> AND Gate, as before
USB_OC2_L/TCK/AGPIO18 AGPIO71/SGPIO_DATAOUT 2N7002KDW 2N SC88-6
AL9 USB_OC3_L/TDO/AGPIO24 AGPIO72/SGPIO_DATAIN BC13
DGPU_PW R_EN <15,30,40>
2 APU_SDATA1 3 4 2
<22> HDA_SDIN0 APU_SDATA1_TP<26>
HDA_BITCLK AU6 AZ_BITCLK/I2S_BCLK_MIC SPKR/AGPIO91 BA17 QC17B
APU_SPKR <22>
RPC11 HDA_SDIN0 AR8 AZ_SDIN0/I2S_DATA_MIC[0] 2N7002KDW 2N SC88-6
<22> HDA_SYNC_AUDIO
1 8HDA_SYNC HDA_SDIN1 AP6 AZ_SDIN1/I2S_LR_PLAYBACK BLINK/USB_OC7_L/AGPIO11 AN5 AGPIO11
HDA_RST#_AUDIO 2 7HDA_RST# HDA_SDIN2 AR5 AZ_SDIN2/I2S_DATA_MIC[1]
3 6HDA_BITCLK HDA_RST# AU9 AZ_RST_L/I2S_LR_MIC GENINT1_L/AGPIO89 BB14 AGPIO89 RC101 1 @ 2 0_0402_5% +3VS
<22> HDA_BITCLK_AUDIO
4 5HDA_SDOUT HDA_SYNC AT9 AZ_SYNC/I2S_BCLK_PLAYBACK GENINT2_L/AGPIO90 BA19
<22> HDA_SDOUT_AUDIO DGPU_PW ROK <40>
HDA_SDOUT AR7 AZ_SDOUT/I2S_DATA_PLAYBACK
33_0804_8P4R_5% FANIN0/AGPIO84 BC18 BT_OFF# RC153 1 2 10K_0402_5%
TS_I2C_RST# <20>
I2C0_SCL BB10 BB19 W LAN_OFF# RC154 1 2 10K_0402_5%
G sensor I2C0_SDA BB9
I2C0_SCL/EGPIO145
I2C0_SDA/EGPIO146
FANOUT0/AGPIO85
TS_INT# <20>
SENSOR_EC_INT RC155 1 2 10K_0402_5%
I2C1_SCL BB7 UART0_CTS_L/EGPIO135 AY9 @
Touch Panel I2C1_SDA BC7
I2C1_SCL/EGPIO147
I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AW8 APU_SCLK0 RC62 1 2 2.2K_0402_5%
UART0_RTS_L/EGPIO137 AV5 BT_OFF# APU_SDATA0 RC63 1 2 2.2K_0402_5%
RTC_CLK AG7 RTCCLK UART0_TXD/EGPIO138 AV8
<24> RTC_CLK
UART0_INTR/AGPIO139 AW9 KB_RST# PXS_RST# RC150 1 2 10K_0402_5%
RC89 2 1 1K_0402_1% HDA_SYNC_AUDIO DGPU_PW R_EN RC51 1 2 10K_0402_5%

100P_0402_50V8J

100P_0402_50V8J
RC90 2 1 1K_0402_1% HDA_RST#_AUDIO 32K_X1 AT1 X32K_X1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140AV11 ESD@ 1 ESD@ 1 CR_CLKREQ# RC130 1 2 10K_0402_5%
RC92 2 1 1K_0402_1% HDA_BITCLK_AUDIO UART1_RXD/BT_I2S_SDI/EGPIO141AU7 CC133 CC132 W LAN_CLKREQ# RC53 1 2 10K_0402_5%
RC102 2 1 1K_0402_1% HDA_SDOUT_AUDIO UART1_RTS_L/EGPIO142 AT11 S0 domain LAN_CLKREQ# RC54 1 2 10K_0402_5%
UART1_TXD/BT_I2S_SDO/EGPIO143AR11

RC95 1
RC104 1
2 10K_0402_5% HDA_SDIN1
2 10K_0402_5% HDA_SDIN2
32K_X2 AT2 X32K_X2

FP4 REV 0.93

UART1_INTR/BT_I2S_LRCLK/AGPIO144AP9
ESD 2 2 VGA_CLKREQ#_R RC55 1 UMA@ 2 10K_0402_5%

RC56 1 DIS@ 2 10K_0402_5%

@ FP4_BGA968

+3VS
+1.8VS MEM_VOLT_SEL1/AGPIO3 RTC_CLK BLINK/AGPIO11 SYS_RST#
RPC4 RC64 1 2 10K_0402_5% GATEA20 CLK_LPC_EC LPC_CLK1 LPC_FRAME#
1 8 I2C1_SCL RC65 1 2 10K_0402_5% KB_RST#
<INT PU> <INT PU> <INT PU> <INT PU>
3 3
2 7 I2C1_SDA LDT_RST#/PG
3 6 I2C0_SDA +3VALW BOOT FAIL CLKGEN SPI ROM COIN BATT NORMAL
OUTPUT TO
4 5 I2C0_SCL

2.2K_0804_8P4R_5%
RC143 1
RC60 1
@ 2
2
10K_0402_5% EC_SCI#
10K_0402_5% APU_PCIE_W AKE#
H TIMER
ENABLED
ENABLE
(DEFAULT)
(DEFAULT) ENHANCED RESET
LOGIC (quick S5)
ON BOARD
(DEFAULT)
APU
(DEFAULT)
RESET MODE
(DEFAULT)
RC61 1 2 100K_0402_5% USB_OC0#
RC99 1 2 100K_0402_5% USB_OC1# BOOT FAIL
TIMER CLKGEN TRADITION AL COIN BATT OUTPUT SHORT RST
I2C Port0: G sensor
1
RC151
2 I2C0_SCL +1.8VALW +3VS
L DISABLED
(DEFAULT)
DISABLED LPC ROM RESET LOGIC NOT ON
BOARD
TO PADS MODE
<30> EC_SMB_CK3
0_0402_5%
YOGA@ +3VS +3VALW
CHECK

1
2

1
2

1
RC152
1 2 I2C0_SDA RC68 @
<30> EC_SMB_DA3
YOGA@ 0_0402_5% 47K_0402_5% RC100 RC70 RC71 RC72 RC73 RC74 RC75 RC76
SCS00005C00 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
DC1
4.7K_0402_5%
1

2
2

2
1

2
1 2EC_RSMRST#_R
<9,30> LPC_FRAME#
<9,30> CLK_LPC_EC
RB751V-40TE17_SOD323-2
<9> LPC_CLK1
MEM_VOLT_SEL1
<30> EC_RSMRST# DC2
SCS00005C00 RTC_CLK
1 2PW R_GOOD_APU SYS_RST#
<30> SYS_PW RGD_EC
1 AGPIO11
RB751V-40TE17_SOD323-2
I2C Port1: Touch Panel 1

1
1

1
+1.8VS CC26
+3VS 1 2 1U_0402_6.3V6K CC27 @ @ @ @ @ @
4 2 4
RC146 1 YOGA@ 2 2.2K_0402_5% @ RC142 1U_0402_6.3V6K RC77 RC78 RC79 RC80 RC81 RC82 RC83
RC147 1 2 2.2K_0402_5% 0_0402_5% 2 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
2

YOGA@ YOGA@
G

2
2
2

2
2
1 3 I2C1_SCL
<20> I2C1_SCL_TS
Compal Electronics, Inc.
D

Security Classification Compal Secret Data

2

MESS138W -G_SOT323-3
G

QC13 2015/10/01 2016/10/01 Title

1 3 I2C1_SDA
Issued Date Deciphered Date
<20> I2C1_SDA_TS FP4 GPIO/AZ/MISC/STRAPS
D

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
YOGA@ MESS138W -G_SOT323-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
QC14 Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 8 of 43
A B C D E
 A B C D E

UAPU1E
+3VS CLK/SATA/USB/SPI/LPC 48MHz CRYSTAL
DIS/UMA <23> SATA_ATX_DRX_P0
<23> SATA_ATX_DRX_N0
AU3
AU4
SATA_TX0P
SATA_TX0N
USBCLK/25M_48M_OSC AP8
48M_X2

2
HDD USB_ZVSS AP5 USB_ZVSS RC85 1 2 11.8K_0402_1%
RC39 AV1 SATA_RX0N 1 RC86 2 48M_X1
<23> SATA_DTX_C_ARX_N0 AV2 AR2
UMA@ 10K_0402_5% SATA_RX0P USB_HSD0P 1M_0402_5%
<23> SATA_DTX_C_ARX_P0 AR1 USB20_P0 <27>
USB_HSD0N
USB20_N0 <27> USB2 IO Board(Charger)
AY2 SATA_TX1P

1
AY1 SATA_TX1N USB_HSD1P AR3
1 USB20_P1 <20> 1
DIS_ID# USB_HSD1N AR4 Touch Screen 2 1
AW4 USB20_N1 <20> 2 1
SATA_RX1N

2
AW3 SATA_RX1P USB_HSD2P AN2
USB20_P2 <24>
RC40 USB_HSD2N AN1 WLAN/BT combo
USB20_N2 <24>
DIS@ 10K_0402_5% RC87 2 1 1K_0402_1% SATA_ZVSS AW1 SATA_ZVSS

+0.95VS RC88 2 1 1K_0402_1% SATA_ZVDD AW2 SATA_ZVDDP USB_HSD3P AN3 YC2

AT17 AN4 USB20_P3 <20>
UMA: HIGH DEVSLP0 DEVSLP[0]/EGPIO67 USB_HSD3N CAMERA
USB20_N3 <20>
1 DEVSLP1 AT12
DIS: LOW SATA_ACT_L BB15
DEVSLP[1]/EGPIO70
SATA_ACT_L/AGPIO130 USB_HSD4P AM1
USB_HSD4N AM2
AU2 SATA_X1 3 4
AL2 3 4
SATA_X1, SATA_X2 USB_HSD5P

1
USB_HSD5N AL1
Not support in Type3. AU1 AL3
CC30
4.7P_0402_50V
CC31
4.7P_0402_50V
SATA_X2 USB_HSD6P
USB20_P6 <27>

2
2
+3VS USB_HSD6N AL4 MB USB3.0 port0
USB20_N6 <27>
RPC13
U4 GFX_CLKP USB_HSD7P AK2 Part Number = SJ10000S400
<13> CLK_PEG_VGA USB20_P7 <27>
1 8 DEVSLP0 U3 GFX_CLKN USB_HSD7N AJ2 MB USB3.0 port1 48MHZ_8PF_7V48000010
2 7 <13> CLK_PEG_VGA# USB20_N7 <27>
SATA_ACT_L
3 6 DEVSLP1 U1 GPP_CLK0P BOT side
4 5 <27> CLK_PCIE_CR U2 GPP_CLK0N
<27> CLK_PCIE_CR#
10K_0804_8P4R_5% W4 GPP_CLK1P
2 <28> CLK_PCIE_LAN W3
2
GPP_CLK1N
<28> CLK_PCIE_LAN#
W1 GPP_CLK2P
<24> CLK_PCIE_WLAN W2 GPP_CLK2N
<24> CLK_PCIE_WLAN#
Y2 GPP_CLK3P
Y1 GPP_CLK3N

RPC14 BC10 X25M_48M_OSC

APU_SPI_AOSI_U 1 8 APU_SPI_AOSI USB_SS_ZVSS AD2 USBSS_ZVSS RC93 1 2 1K_0402_1%
APU_SPI_CLK_U
APU_SPI_CS1#_U
APU_SPI_AISO_U
2
3
4
7
6
5
APU_SPI_CLK
APU_SPI_CS1#
APU_SPI_AISO
RF 48M_X1 T2 X48M_X1
USB_SS_ZVDDP AD1 USBSS_ZVDD RC96 1

AA3
2 1K_0402_1%
+0.95VALW
USB_SS_0TXP
CC68 RF@ USB_SS_0TXN AA4
33_0804_8P4R_5% 22P_0402_50V8J
2 1 48M_X2 T1 X48M_X2 USB_SS_0RXP W9
USB_SS_0RXN W8

RC97 1 RF@ 233_0402_5% CLK_LPC_EC_R AW14 AA2

Need check R value <8,30> CLK_LPC_EC
<8> LPC_CLK1
RC98 1 EMI@ 233_0402_5% LPC_CLK1_R AY13
LPCCLK0/EGPIO74
LPCCLK1/EGPIO75
USB_SS_1TXP
USB_SS_1TXN AA1

BB11 LAD0 USB_SS_1RXP W5

<30> LPC_AD0 BA11 W6
LAD1 USB_SS_1RXN
<30> LPC_AD1 AY11
3 <30> LPC_AD2 LAD2 3
BA13 LAD3 USB_SS_2TXP AC1
<30> LPC_AD3 AV14 AC2 USB30_MTX_C_DRX_P2 <27>
LFRAME_L USB_SS_2TXN
<8,30> LPC_FRAME# USB30_MTX_C_DRX_N2 <27>
BA1 ESPI_ALERT_L/LDRQ0_L
BC14 SERIRQ/AGPIO87 USB_SS_2RXP Y6 MB USB3.0 port0
<30> SERIRQ BC11 Y7 USB30_MRX_DTX_P2 <27>
RPC12 LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN
+1.8VS USB30_MRX_DTX_N2 <27>
1 2 LPC_PD# AE9 LPC_PD_L/AGPIO21
APU_SPI_WP# 1 8 RC141 10K_0402_5% USB_SS_3TXP AC4
USB30_MTX_C_DRX_P3 <27>
APU_SPI_CS1#_U 2 7 USB_SS_3TXN AC3
3 6 BC6 USB30_MTX_C_DRX_N3 <27>
APU_SPI_HOLD# APU_SPI_CLK SPI_CLK/ESPI_CLK/EGPIO117 MB USB3.0 port1
4 5 APU_SPI_CS1# BB8 SPI_CS1_L/EGPIO118 USB_SS_3RXP AB5
USB30_MRX_DTX_P3 <27>
2 1 APU_SPI_CS2# AW7 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN AB6
BA9 USB30_MRX_DTX_N3 <27>
10K_0804_8P4R_5% RC91 APU_SPI_AISO SPI_DI/ESPI_DATA/EGPIO120
10K_0402_5% APU_SPI_AOSI AY7 SPI_DO/EGPIO121
APU_SPI_WP# AW11 SPI_WP_L/EGPIO122
APU_SPI_HOLD# BA7 SPI_HOLD_L/EGPIO133
DIS_ID# AW12 SPI_TPM_CS_L/AGPIO76
+1.8VS
8MB SPI ROM @
FP4 REV 0.93

FP4_BGA968

UC1
APU_SPI_CS1#_U1 8
APU_SPI_AISO_U 2 /CS VCC 7 APU_SPI_HOLD#
4 APU_SPI_WP# 3 DO(IO1) /HOLD(IO3) 6 APU_SPI_CLK_U 4
4 /WP(IO2) CLK 5 APU_SPI_AOSI_U
GND DI(IO0) 1
W25Q64FWSSIQ_SO8 CC32
0.1U_0201_10V6K
Security Classification Compal Secret Data Compal Electronics, Inc.
APU_SPI_CLK 1 2 1 2 2
Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title
RC105 @EMI@ CC33 @EMI@
10_0402_5% 10P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP4 SATA/CLK/USB/SPI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 9 of 43
A B C D E
 A B C D E

+1.2V
+APU_CORE_NB Under APU +APU_CORE

CC89

CC90

CC91

CC92

CC93

CC56

CC57

CC58

CC52

CC59

CC60

CC61

CC62

CC63
+1.2V

CC34

CC35

CC36

CC37

CC38

CC39

CC40

CC41

CC42

CC43

CC44

CC45

CC46

CC47

CC48

CC49

CC50

CC51
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
@
1
@
1
@
1 1 1 1 1 1 1 22u*8 DIMMS/GND +APU_CORE

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

180P_0402_50V8J

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K
22U_0603_6.3V6M 22u*3 (un-pop) 2 2 2 2 2 2 2 2 2 2 2 2 2 2

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

180P_0402_50V8J
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0.22u*6 22u*9->on PWR side
180P*1 0.22u*8
180P*1

1 Under APU UAPU1F 1

POWER +APU_CORE_NB
+1.2V +1.2V P25 VDDIO_MEM_S3_1 VDDCR_CPU_1 U8 +APU_CORE

CC74

CC75

CC76

CC77

CC78

CC79

CC80

CC81

CC82
P28 W7
2.5A VDDIO_MEM_S3_2 VDDCR_CPU_2
25A
CC66
CC53

CC54

CC64

CC65

CC55

T24 VDDIO_MEM_S3_3 VDDCR_CPU_3 W12 1 1 1 1 1 1 1 1 1

T27 W15
1 1 1 1 1 1
U25
VDDIO_MEM_S3_4
VDDIO_MEM_S3_5
VDDCR_CPU_4
VDDCR_CPU_5 W18 +APU_CORE_NB

180P_0402_50V8J

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K
U28 W21
VDDIO_MEM_S3_6 VDDCR_CPU_6
22u*4->on PWR side 2 2 2 2 2 2 2 2 2
180P_0402_50V8J
0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

180P_0402_50V8J

V30 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y8

2 2 2 2 2 2 V33
W24
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDCR_CPU_8
VDDCR_CPU_9
Y10
Y13
0.22u*8
W27
Y25
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDCR_CPU_10
VDDCR_CPU_11
Y16
Y19
180P*1
Y28 VDDIO_MEM_S3_12 VDDCR_CPU_12 Y22
Y30 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB7
AB24 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB9
AB27 AB12
DIMMS/GND AB30
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDCR_CPU_15
VDDCR_CPU_16 AB15
AB33 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB18
AD25 VDDIO_MEM_S3_18 VDDCR_CPU_18 AB21
+1.8V_1.5V_AUDIO AD28 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD6 +APU_CORE_NB QC8 QC9
AD30
AE24
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDCR_CPU_20
VDDCR_CPU_21
AD10
AD13 0.9A AO3416L_SOT23-3 AO3416L_SOT23-3
0.9A +APU_FCH_ALW

D
RC148 1 2 0_0402_5% AE27 AD16 1 3 3 1

S
+1.8VS VDDIO_MEM_S3_22 VDDCR_CPU_22 1
AF30 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD19 CC120 1 1

22U_0603_6.3V6M

22U_0603_6.3V6M

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1

1
AF33 AD22 4.7U_0603_6.3V6K

CC124
CC123
VDDIO_MEM_S3_24 VDDCR_CPU_24
AG25 AE7

CC121

CC122
G
G
VDDIO_MEM_S3_25 VDDCR_CPU_25

2
2
AG28 VDDIO_MEM_S3_26 VDDCR_CPU_26 AE12 2

2
AH24 VDDIO_MEM_S3_27 VDDCR_CPU_42 AK9 2 2
AH27 VDDIO_MEM_S3_28 VDDCR_CPU_31 AG10
AH30 VDDIO_MEM_S3_29 VDDCR_CPU_43 AK10 CORE_NB_GATE
1 2 AK25 VDDIO_MEM_S3_30 VDDCR_CPU_32 AG13
+3VALW +3VS +3VS_APU +1.8V_1.5V_AUDIO
AK28 VDDIO_MEM_S3_31 VDDCR_CPU_44 AK13
CC83

CC84

CC67

RC106 AK30 VDDIO_MEM_S3_32 VDDCR_CPU_33 AG16

CC71

CC72

CC73
1 1 0_0402_5% 1 AK33 VDDIO_MEM_S3_33 VDDCR_CPU_45 AK16
AL27 AG19 +0.775VALW QC10 QC11
1 1 1 VDDIO_MEM_S3_34 VDDCR_CPU_34
AM30 VDDIO_MEM_S3_35 VDDCR_CPU_46 AK19
0.2A AO3416L_SOT23-3 AO3416L_SOT23-3
10U_0603_6.3V6M

0.22U_0402_10V6K

10U_0603_6.3V6M

2 VDDCR_CPU_35 AG22 2
2 2 2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

D
AR19 AK22 1 3 3 1

S
2 2 2 +1.8V_1.5V_AUDIO VDDIO_AUDIO VDDCR_CPU_47 1
AH7 CC128
0.2A AE6
VDDCR_CPU_36
AE18 4.7U_0603_6.3V6K
VDDP_GFX_2 VDDCR_CPU_28 1
AE5 AE21

G
G
VDDP_GFX_1 VDDCR_CPU_29

2
VDDCR_CPU_40 AH21 2 CC125
AP19 VDD_33_1 VDDCR_CPU_30 AG6 4.7U_0603_6.3V6K
+3VS_APU 2
AP21 AH12
0.2A VDD_33_2 VDDCR_CPU_37
VDDCR_CPU_49 AN6 0.775VALW_GATE
AP16 VDD_18_1 VDDCR_CPU_38 AH15
+1.8VS
AP18 AH18
1.5A VDD_18_2 VDDCR_CPU_39
VDDCR_CPU_48 AL7
+1.8VALW AP10 VDD_18_S5_1 VDDCR_CPU_41 AK6
AR9 AE15 +5VALW
0.5A VDD_18_S5_2 VDDCR_CPU_27

+1.8VALW +1.8VS +0.95VALW +APU_FCH_ALW +APU_CORE_NB +5VALW

+3VALW AP15 VDD_33_S5_1
CC139
CC86

CC69

CC88
CC85

CC70

CC87

CC137

CC138

AR15 L8
0.2A VDD_33_S5_2 VDDCR_GFX_14

8
1 1 1 1 1 1 1 1 1 VDDCR_GFX_15 L13 UC1103A
AN12 L16 3

P
+0.95VALW VDDP_S5_1 VDDCR_GFX_16
AP12 L19 + 1 CORE_NB_GATE RC126 1 2 1K_0402_1%
0.8A VDDP_S5_2 VDDCR_GFX_17
O
10U_0603_6.3V6M
0.22U_0402_10V6K

10U_0603_6.3V6M

0.22U_0402_10V6K
10U_0603_6.3V6M

0.22U_0402_10V6K

10U_0603_6.3V6M

0.22U_0402_10V6K

10U_0603_6.3V6M

VDDCR_GFX_18 L22 0.775MOS 2

-

G
2 2 2 2 2 2 2 2 2 AP13 VDDCR_FCH_S5_1 VDDCR_GFX_19 N7 +5VALW
+APU_FCH_ALW AR12 VDDCR_FCH_S5_2 VDDCR_GFX_20 N12 LM393DGKR_VSSOP8

4
N15
0.9A VDDCR_GFX_21

8
AW19 VDDP_6 VDDCR_GFX_22 N18 UC1103B
+0.95VS
AU17 N21 5
7A

P
VDDP_1 VDDCR_GFX_23
AU19 P8 + 7 0.775VALW_GATE RC121 1 2 1K_0402_1%
VDDP_2 VDDCR_GFX_24
AV17 P13 6 O
VDDP_3 VDDCR_GFX_25
-

G
AV19 VDDP_4 VDDCR_GFX_26 P16
AW17 VDDP_5 VDDCR_GFX_27 P19 LM393DGKR_VSSOP8

4
VDDCR_GFX_28 P22
AL12 VDDCR_NB_1 VDDCR_GFX_29 T7
+APU_CORE_NB
AL13 F12
14A AL15
VDDCR_NB_2
VDDCR_NB_3
VDDCR_GFX_1
VDDCR_GFX_2 F15
AL18 G11 +3VALW +5VALW +0.775VALW
+0.95VALW/+0.95VS OF APU AL21
AN13
VDDCR_NB_4
VDDCR_NB_5
VDDCR_GFX_3
VDDCR_GFX_4 G14
J8
VDDCR_NB_6 VDDCR_GFX_5

2
AN16 VDDCR_NB_7 VDDCR_GFX_6 J9
3 3
AN19 J11 RC113
VDD_095 AN22
VDDCR_NB_8 VDDCR_GFX_7
K7
Under APU VDDCR_NB_9 VDDCR_GFX_8

6
+0.95VS K12 100K_0402_5%
RTC OF APU VDDCR_GFX_9
VDDCR_GFX_10 K13 RC114 QC7A

1
+RTCBATT_R +RTCBATT_R AR17 VDDBT_RTC_G VDDCR_GFX_11 K15 ME2N7002D1KW-G 2N_SOT363-6
VDDCR_GFX_12 K16 100K_0402_5% 2
CC99

CC144

CC145
CC143
CC141

CC142
CC100

CC104
CC101

CC102

CC140

CC98

VDDCR_GFX_30 T12

1
1 1 1 1 1 1 1 1 1 1 1 1 VDDCR_GFX_31 T15

1
3
VDDCR_GFX_32 T18
VDDCR_GFX_33 T21 QC7B 0.775MOS
10U_0603_6.3V6M

0.22U_0402_10V6K

0.22U_0402_10V6K
0.22U_0402_10V6K
10U_0603_6.3V6M

0.22U_0402_10V6K

0.22U_0402_10V6K

180P_0402_50V8J
10U_0603_6.3V6M

10U_0603_6.3V6M

0.22U_0402_10V6K

0.22U_0402_10V6K

VDDCR_GFX_34 U13 ME2N7002D1KW-G 2N_SOT363-6

2
2 2 2 2 2 2 2 2 2 2 2 2 VDDCR_GFX_35 U16 5
<8> S5_MUX_CTRL
VDDCR_GFX_36 U19 RC123
VDDCR_GFX_37 U22

4
VDDCR_GFX_13 K19 100K_0402_5%

1
FP4 REV 0.93
@ FP4_BGA968

+0.95VS
+RTCBATT_3V
10u*4 RTC OF APU VDDBT_RTC_G
0.22u*6 VDDBT_RTC_G +RTCBATT +RTCBATT 3
UC3
Vout
180P*1 2 Vin
1

0.1U_0603_25V7K
+RTCBATT_R 1 2 1K_0402_1% GND
W=20mils RC107

680P_0603_50VK
1

CC107
2

1
AP2138N-1.5TRG1_SOT23-3

CC108
1
@ RC119

2
1

CC109 0_0402_5%

2
0.22U_0402_10V6K CLRP1
Need OPEN
1

2 D @ SHORT PADS
1

2
<30> EC_CLEAR_CMOS#
4 G 4
1

S QC12 for Clear CMOS

3

RC94 2N7002H_SOT23-3
10K_0402_5%
@
2

Need use+3.3V transfer to +1.5V LDO to APU side for Beema

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title
FP4 PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 10 of 43
A B C D E
 5 4 3 2 1

D D

UAPU1G UAPU1H
UAPU1J
GND GND
A8 VSS_1 VSS_63 L28 AE10 VSS_125 VSS_187 AV30
A12 VSS_2 VSS_64 M4 AE13 VSS_126 VSS_188 AV33 TPC23 U30 RSVD_2
A16 VSS_3 VSS_65 M30 AE16 VSS_127 VSS_189 AW22 TPC22 U31 RSVD_3
A20 VSS_4 VSS_66 N10 AE19 VSS_128 VSS_190 AY4 TPC24 AN30 RSVD_4
A24 VSS_5 VSS_67 N13 AE22 VSS_129 VSS_191 AY6
A28 VSS_6 VSS_68 N16 AF1 VSS_130 VSS_192 AY8
A32 VSS_7 VSS_69 N19 AF4 VSS_131 VSS_193 AY10
B2 VSS_8 VSS_70 N22 AG9 VSS_132 VSS_194 AY12
B8 VSS_9 VSS_71 N27 AG12 VSS_133 VSS_195 AY14
B12 VSS_10 VSS_72 P1 AG15 VSS_134 VSS_196 AY16
B33 VSS_11 VSS_73 P2 AG18 VSS_135 VSS_197 AY20
C3 VSS_12 VSS_74 P4 AG21 VSS_136 VSS_198 AY22 FP4 REV 0.93
D4 VSS_13 VSS_75 P5 AH4 VSS_137 VSS_199 AY24
D6 VSS_14 VSS_76 P12 AH10 VSS_138 VSS_200 AY26 FP4_BGA968
D8 VSS_15 VSS_77 P15 AH13 VSS_139 VSS_201 AY28 @
D10 VSS_16 VSS_78 P18 AH16 VSS_140 VSS_202 AY30
D12 VSS_17 VSS_79 P21 AH19 VSS_141 VSS_203 BB1
D14 VSS_18 VSS_80 P30 AH22 VSS_142 VSS_204 BB33
D16 VSS_19 VSS_81 P33 AK1 VSS_143 VSS_205 BC4
D18 VSS_20 VSS_82 T4 AK4 VSS_144 VSS_206 BC8
D20 VSS_21 VSS_83 T10 AK12 VSS_145 VSS_207 BC12
D22 VSS_22 VSS_84 T13 AK15 VSS_146 VSS_208 BC16
D24 VSS_23 VSS_85 T16 AK18 VSS_147 VSS_209 BC20
D26 VSS_24 VSS_86 T19 AL16 VSS_148 VSS_210 BC24
C D28 T22 AL19 BC28 C
VSS_25 VSS_87 VSS_149 VSS_211
D30 VSS_26 VSS_88 T30 AL22 VSS_150 VSS_212 BC32
F1 VSS_27 VSS_89 U5 AM4 VSS_151
F2 VSS_28 VSS_90 U12 AN9 VSS_152
F4 VSS_29 VSS_91 U15 AN10 VSS_153
F9 VSS_30 VSS_92 U18 AN15 VSS_154
F19 VSS_31 VSS_93 U21 AN18 VSS_155
F22 VSS_32 VSS_94 U24 AN21 VSS_156
F25 VSS_33 VSS_95 V1 AN25 VSS_157
F30 VSS_34 VSS_96 V2 AN28 VSS_158
F33 VSS_35 VSS_97 V4 AP1 VSS_159
G7 VSS_36 VSS_98 W10 AP2 VSS_160
G17 VSS_37 VSS_99 W13 AP4 VSS_161
G20 VSS_38 VSS_100 W16 AP7 VSS_162
G23 VSS_39 VSS_101 W19 AP22 VSS_163
G26 VSS_40 VSS_102 W22 AP27 VSS_164
H4 VSS_41 VSS_103 Y4 AP30 VSS_165
H30 VSS_42 VSS_104 Y5 AP33 VSS_166
J5 VSS_43 VSS_105 Y12 AR6 VSS_167
J15 VSS_44 VSS_106 Y15 AR25 VSS_168
J19 VSS_45 VSS_107 Y18 AR28 VSS_169
J22 VSS_46 VSS_108 Y21 AT4 VSS_170
J25 VSS_47 VSS_109 Y24 AT19 VSS_171
J28 VSS_48 VSS_110 AB1 AT22 VSS_172
K1 VSS_49 VSS_111 AB2 AT30 VSS_173
K2 VSS_50 VSS_112 AB4 AU5 VSS_174
K4 VSS_51 VSS_113 AB10 AU8 VSS_175
K10 VSS_52 VSS_114 AB13 AU11 VSS_176
K22 VSS_53 VSS_115 AB16 AU14 VSS_177
K27 VSS_54 VSS_116 AB19 AU20 VSS_178
K30 VSS_55 VSS_117 AB22 AU23 VSS_179
K33 VSS_56 VSS_118 AD4 AU27 VSS_180
B L5 VSS_57 VSS_119 AD9 AV4 VSS_181
B
L12 VSS_58 VSS_120 AD12 AV7 VSS_182
L15 VSS_59 VSS_121 AD15 AV9 VSS_183
L18 VSS_60 VSS_122 AD18 AV12 VSS_184 VSS_213 L24
L21 VSS_61 VSS_123 AD21 AV15 VSS_185 VSS_215 AL10
L25 VSS_62 VSS_124 AD24 AV25 VSS_186 VSS_214 AK21

FP4 REV 0.93 FP4 REV 0.93

FP4_BGA968 FP4_BGA968

@ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP3 GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 11 of 43
5 4 3 2 1
 A B C D E

<6> DDRAB_SDQS#[0..7] Reverse Type

<6> DDRAB_SDQ[0..63]
2-3A to 1 DIMMs/channel
<6> DDRAB_SDQS[0..7]

+1.2V +1.2V
<6> DDRAB_SMA[0..13]

<6> JDIMM1
DDRAB_SDM[0..7]
1 2
DDRAB_SDQ5 3 VSS VSS 4 DDRAB_SDQ4
5 DQ5 DQ4 6
DDRAB_SDQ1 7 VSS VSS 8 DDRAB_SDQ0
9 DQ1 DQ0 10
DDRAB_SDQS#0 11 VSS VSS 12 DDRAB_SDM0
DDRAB_SDQS0 13 DQS0_C DM0*/DBI0* 14
15 DQS0_T VSS 16 DDRAB_SDQ6
DDRAB_SDQ7 17 VSS DQ6 18
19 DQ7 VSS 20 DDRAB_SDQ2
1 1
DDRAB_SDQ3 21 VSS DQ2 22
23 DQ3 VSS 24 DDRAB_SDQ12
DDRAB_SDQ13 25 VSS DQ12 26
27 DQ13 VSS 28 DDRAB_SDQ8
DDRAB_SDQ9 29 VSS DQ8 30
31 DQ9 VSS 32 DDRAB_SDQS#1
DDRAB_SDM1 33 VSS DQS1_C 34 DDRAB_SDQS1
35 DM1*/DBI1* DQS1_T 36
DDRAB_SDQ15 37 VSS VSS 38 DDRAB_SDQ14
39 DQ15 DQ14 40
DDRAB_SDQ10 41 VSS VSS 42 DDRAB_SDQ11
43 DQ10 DQ11 44
DDRAB_SDQ21 45 VSS VSS 46 DDRAB_SDQ20
47 DQ21 DQ20 48
DDRAB_SDQ17 49 VSS VSS 50 DDRAB_SDQ16
51 DQ17 DQ16 52
DDRAB_SDQS#2 53 VSS VSS 54 DDRAB_SDM2 +1.2V
DDRAB_SDQS2 55 DQS2_C DM2*/DBI2* 56
57 DQS2_T VSS 58 DDRAB_SDQ22
DDRAB_SDQ23 59 VSS DQ22 60
61 DQ23 VSS 62 DDRAB_SDQ18
DDRAB_SDQ19 63 VSS DQ18 64 +DIMM_VREF_DQ
65 DQ19 VSS 66 DDRAB_SDQ28
VSS DQ28

2
DDRAB_SDQ29 67 68
69 DQ29 VSS 70 DDRAB_SDQ24 RD194
DDRAB_SDQ25 71 VSS DQ24 72 1K_0402_1%
73 DQ25 VSS 74 DDRAB_SDQS#3
DDRAB_SDM3 75 VSS DQS3_C 76 DDRAB_SDQS3

1
77 DM3*/DBI3* DQS3_T 78
DDRAB_SDQ30 79 VSS VSS 80 DDRAB_SDQ31
Note: DQ30 DQ31
Layout Note: 81 82
Check voltage tolerance of DDRAB_SDQ26 83 VSS VSS 84 DDRAB_SDQ27
Place near JDIMM1 VREF_DQ at the DIMM socket 85 DQ26 DQ27 86
87 VSS VSS 88
89 CB5_NC CB4_NC 90
91 VSS VSS 92
93 CB1_NC CB0_NC 94
VSS VSS

2
1 @ 2 95 96
+1.2V 6/16 INTEL suggest RD165
1 240_0402_1%
2 97 DQS8_C DM8*/DBI8* 98 RD199
RD166 @ 240_0402_1% 99 DQS8_T VSS 100
VSS CB6_NC 1K_0402_1%
101 102
103 CB2_NC VSS 104

1
VSS CB7_NC
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

105 106
107 CB3_NC VSS 108
2 1 1 1 1 1 1 1 1 VSS RESET* MEM_MAB_RST# <6> 2
DDRAB_CKE0 109 110 DDRAB_CKE1
<6> DDRAB_CKE0 CKE0 CKE1 DDRAB_CKE1 <6>
CD4

CD5

CD7

CD8

CD9
CD6

CD17

CD18

111 112
113 VDD1 VDD2 114
2 2 2 2 2 2 2 2 <6> DDRAB_BG1 BG1 ACT* DDRAB_ACT# <6>
<6> 115 116 RD202 2 1
DDRAB_BG0 BG0 ALERT*
117 118 1K_0402_1%
DDRAB_SMA12 119 VDD3 VDD4 120 DDRAB_SMA11
DDRAB_SMA9 121 A12 A11 122 DDRAB_SMA7
123 A9 A7 124
DDRAB_SMA8 125 VDD5 VDD6 126 DDRAB_SMA5 MEM_MAB_RST#
4 as near side of the DIMM close to VDD pins A8 A5
DDRAB_SMA6 127 128 DDRAB_SMA4
A6 A4

100P_0402_50V8J
129 130 CC136 1
+1.2V DDRAB_SMA3 131 VDD7 VDD8 132 DDRAB_SMA2
DDRAB_SMA1 133
135
A3
A1
A2
EVENT*
134
136
MEM_MAB_EVENT#
MEM_MAB_EVENT# <6>
@ESD@
close to DDR
VDD9 VDD10 2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDRA_CLK0 137 138 DDRA_CLK1

<6> DDRA_CLK0 CK0_T CK1_T DDRA_CLK1 <6>
DDRA_CLK0# 139 140 DDRA_CLK1#
<6> DDRA_CLK0# CK0_C CK1_C DDRA_CLK1# <6>
1 141 142
@ 2 RD139 1 143 VDD11 VDD12 144 DDRAB_SMA0
1 1 1 1 1 1 1 1 PARITY A0
ESD
CD11

CD12

CD19

CD20
CD10

CD13

CD14

CD15

+ CD35
330U_D3_2.5VY_R6M 0_0201_5%
2 2 2 2 2 2 2 2 2 DDRAB_SBS1# 145 146 DDRAB_SMA10
<6> DDRAB_SBS1# BA1 A10_AP
147 148
DDRA_SCS0# 149 VDD13 VDD14 150 DDRAB_SBS0#
<6> DDRA_SCS0# S0* BA0 DDRAB_SBS0# <6>
DDRAB_SWE# 151 152 DDRAB_SRAS#
<6> DDRAB_SWE# A14_WE* A16_RAS* DDRAB_SRAS# <6>
153 154
DDRA_ODT0 155 VDD15 VDD16 156 DDRAB_SCAS#
<6> DDRA_ODT0 ODT0 A15_CAS* DDRAB_SCAS# <6>
DDRA_SCS1# 157 158 DDRAB_SMA13
<6> DDRA_SCS1# S1* A13 +DIMM_VREF_DQ
159 160
DDRA_ODT1 161 VDD17 VDD18 162
+3VS <6> DDRA_ODT1 ODT1 S2*/C0
163 164
165 VDD19 VREFCA 166
Place these caps on the VTT plane close to DIMM S3*/C1 SA2 1
167 168
DDRAB_SDQ37 169 VSS VSS 170 DDRAB_SDQ36 CD34
+0.6VS 171 DQ37 DQ36 172
VSS VSS .1U_0402_16V7K
DDRAB_SDQ33 173 174 DDRAB_SDQ32 2
+3VS_DIMM 175 DQ33 DQ32 176
DDRAB_SDQS#4 177 VSS VSS 178 DDRAB_SDM4
DDRAB_SDQS4 179 DQS4_C DM4*/DBI4* 180
181 DQS4_T VSS 182 DDRAB_SDQ39
1 1 1 1
4.7U_0603_6.3V6K

DDRAB_SDQ38 183 VSS DQ39 184

CD30

CD31 C2142 CD28 185 DQ38 VSS 186 DDRAB_SDQ35

2.2U_0402_6.3V6M DDRAB_SDQ34 187 VSS DQ35 188
.1U_0402_16V7K .1U_0402_16V7K
2 2 2 2 189 DQ34 VSS 190 DDRAB_SDQ45
DDRAB_SDQ44 191 VSS DQ45 192
3 3
193 DQ44 VSS 194 DDRAB_SDQ41
DDRAB_SDQ40 195 VSS DQ41 196
197 DQ40 VSS 198 DDRAB_SDQS#5
close to DIMM VSS DQS5_C
DDRAB_SDM5 199 200 DDRAB_SDQS5
201 DM5*/DBI5* DQS5_T 202
DDRAB_SDQ46 203 VSS VSS 204 DDRAB_SDQ47
205 DQ46 DQ47 206
DDRAB_SDQ42 207 VSS VSS 208 DDRAB_SDQ43
209 DQ42 DQ43 210
DDRAB_SDQ52 211 VSS VSS 212 DDRAB_SDQ53
213 DQ52 DQ53 214
DDRAB_SDQ49 215 VSS VSS 216 DDRAB_SDQ48
217 DQ49 DQ48 218
DDRAB_SDQS#6 219 VSS VSS 220 DDRAB_SDM6
DDRAB_SDQS6 221 DQS6_C DM6*/DBI6* 222
223 DQS6_T VSS 224 DDRAB_SDQ54
DDRAB_SDQ55 225 VSS DQ54 226
+2.5V 227 DQ55 VSS 228 DDRAB_SDQ50
DDRAB_SDQ51 229 VSS DQ50 230
231 DQ51 VSS 232 DDRAB_SDQ60
DDRAB_SDQ61 233 VSS DQ60 234
235 DQ61 VSS 236 DDRAB_SDQ57
DDRAB_SDQ56 237 VSS DQ57 238 +3VS
239 DQ56 VSS 240 DDRAB_SDQS#7
+2.5V DDRAB_SDM7 241 VSS DQS7_C 242 DDRAB_SDQS7 +0.6VS
243 DM7*/DBI7* DQS7_T 244
VSS VSS

2
10U_0603_6.3V6M

1 1 DDRAB_SDQ62 245 246 DDRAB_SDQ63

C2140 CD29 247 DQ62 DQ63 248 RD108
DDRAB_SDQ58 249 VSS VSS 250 DDRAB_SDQ59 10K_0402_5%
DQ58 DQ59
1U_0402_6.3V6K

251 252
2 2 APU_SCLK0 253 VSS VSS 254 APU_SDATA0
<8> APU_SCLK0 APU_SDATA0 <8>

1
+3VS_DIMM 255 SCL SDA 256
257 VDDSPD SA0 258
259 VPP1 VTT 260
VPP2 SA1

1
RD138
261 0_0402_5%
GND 262
GND @

2
DEREN_40-42271-26001RHF
LTCX006KS00
ME@

4 4
ADDRESS: A2

Security Classification
2015/10/01
Compal Secret Data
2016/10/01 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_DIMM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-D541P 0.2

Date: Thursday, December 17, 2015 Sheet 12 of 43

A B C D E
 1 2 3 4 5

UV1A
A A

DIS@
AF30 AH30 PCIE_PRX_C_DTX_P0 CV1 1 2 0.22U_0402_6.3V6K
<5> PCIE_PTX_C_DRX_P0 PCIE_RX0P PCIE_TX0P PCIE_PRX_DTX_P0 <5>
AE31 AG31 PCIE_PRX_C_DTX_N0 CV2 1 2 0.22U_0402_6.3V6K
<5> PCIE_PTX_C_DRX_N0 PCIE_RX0N PCIE_TX0N PCIE_PRX_DTX_N0 <5>
DIS@
DIS@
AE29 AG29 PCIE_PRX_C_DTX_P1 CV3 1 2 0.22U_0402_6.3V6K
<5> PCIE_PTX_C_DRX_P1 PCIE_RX1P PCIE_TX1P PCIE_PRX_DTX_P1 <5>
AD28 AF28 PCIE_PRX_C_DTX_N1 CV4 1 2 0.22U_0402_6.3V6K
<5> PCIE_PTX_C_DRX_N1 PCIE_RX1N PCIE_TX1N PCIE_PRX_DTX_N1 <5>
DIS@

AD30 AF27
AC31 PCIE_RX2P PCIE_TX2P AF26
PCIE_RX2N PCIE_TX2N

AC29 AD27
AB28 PCIE_RX3P PCIE_TX3P AD26
PCIE_RX3N PCIE_TX3N

AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N

AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27
B
V28 PCIE_RX7P PCIE_TX7P Y26 B
PCIE_RX7N PCIE_TX7N

V30 W24
U31 NC#V30 NC#W24 W23
NC#U31 NC#W23

U29 V27
T28 NC#U29 NC#V27 U26
NC#T28 NC#U26

PCI EXPRESS INTERFACE

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
No Use GPU Display Port outpud
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 UV1F @

P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23 AB11
VARY_BL AB12
N29 P27 DIGON
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24 AL15

L31 NC#M30 NC#P24 P23 TXCAP_DPA3P AK14
NC#L31 NC#P23 TXCAM_DPA3N
AH16
L29 M27 TX0P_DPA2P AJ15
K30 NC#L29 NC#M27 N26 TX0M_DPA2N
NC#K30 NC#N26 AL17
TX1P_DPA1P AK16
C C
TX1M_DPA1N
CLOCK AH18
CLK_PEG_VGA AK30 TX2P_DPA0P AJ17
<9> CLK_PEG_VGA PCIE_REFCLKP TX2M_DPA0N
CLK_PEG_VGA# AK32
<9> CLK_PEG_VGA# PCIE_REFCLKN +0.95VGS AL19
+3VGS NC_TXOUT_L3P AK18
CALIBRATION NC_TXOUT_L3N
Y22 RV1 1 DIS@ 2 1.69K_0402_1%
PCIE_CALR_TX TMDP
RV2 1 DIS@ 2 1K_0402_5% N10 AA22 RV3 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
5

UV2 DIS@ AH20

APU_PCIE_RST# 2 TXCBP_DPB3P AJ19
P

<8,24,27,28> APU_PCIE_RST# B TXCBM_DPB3N

4 GPU_RST# AL27
PXS_RST# 1 Y PERSTB AL21
<8> PXS_RST# A TX3P_DPB2P
G

AK20
TX3M_DPB2N
1
3

RV4 216-0841018 A0 SUN PRO S3 @ AH22

MC74VHC1G08DFT2G_SC70-5 100K_0402_5% TX4P_DPB1P AJ21
DIS@ TX4M_DPB1N
UV1 AL23
2

SA000087T80 TX5P_DPB0P AK22

S IC 216-0867-030 R16M-M1-30 FCBGA C38 TX5M_DPB0N
DIS@ AK24
NC_TXOUT_U3P AJ23
NC_TXOUT_U3N

216-0841018 A0 SUN?PRO S3

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(1/5)_PCIE/DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 13 of 43
1 2 3 4 5
 1 2 3 4 5

+3VGS

+1.8VGS
PS_0[3:1]=001 Strap Name :

1
DIS@ DIS@ UV1B U?

2
RV157 RV158 PS_0[5:4]=11

1
47K_0402_5% 47K_0402_5% PS_0[1] ROM_CONFIG[0]
DIS@
AF2 RV12 PS_0[2] ROM_CONFIG[1]

2
6 1 VGA_SMB_DA2 NC#AF2 AF4 8.45K_0402_1%

S
<7,25,30> EC_SMB_DA2 NC#AF4

D
PS_0[3] ROM_CONFIG[2]

2
5
DIS@ QV9A N9 AG3 PS_0

G
2N7002KDW_SOT363-6 L9 DBG_DATA16 NC#AG3 AG5
DBG_DATA15 NC#AG5 Resistor Divider Lookup Lable PS_0[4] N/A

1
AE9 1

0.68U_0402_10V
DPA
Y11 DBG_DATA14 AH3 DIS@
3 4 VGA_SMB_CK2 AE8 DBG_DATA13 NC#AH3 AH1 CV30 RV7
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
R_pu (ohm) R_pd (ohm) Bitd [3:1]

S
<7,25,30> EC_SMB_CK2 DBG_DATA12 NC#AH1
AD9 2K_0402_1%

D
A AC10 DBG_DATA11 AK3 @ 2 A

2
DIS@ QV9B AD7 DBG_DATA10 NC#AK3 AK1
2N7002KDW_SOT363-6 AC8 DBG_DATA9 NC#AK1 NC 4.75k 000
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3
8.45k 2k 001
AB8 DBG_DATA6 NC#AM3
AB7 DBG_DATA5 AK6
4.53k 2k 010
AB4 DBG_DATA4 NC#AK6 AM5
AB2 DBG_DATA3 NC#AM5 6.98k 4.99k 011 +1.8VGS
Y8 DBG_DATA2 DPB
AJ7
PS_1[3:1]=001 Strap Name :
Y7 DBG_DATA1 NC#AJ7 AH6
4.53k 4.99k 100
DBG_DATA0 NC#AH6 PS_1[5:4]=11

1
AK8
3.24k 5.62k 101 DIS@
PS_1[1] STRAP_BIF_GEN3_EN_A
NC#AK8 AL7 RV9
NC#AL7 3.4k 10k 110 8.45K_0402_1%
PS_1[2] TRAP_BIF_CLK_PM_EN
4.75k NC 111 PS_1[3] N/A

2
W6 PS_1
V6 NC#W6
NC#V6 0402 1% resistors are equired PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING

1
V4 1

0.68U_0402_10V
AC6 NC#V4 U5 DIS@
AC5 NC#AC5 NC#U5 CV31 RV14
PS_1[5] STRAP_TX_DEEMPH_EN
NC#AC6 W3 2K_0402_1%
AA5 NC#W3 V2 @ 2
Capacitor Divider Lookup Lable

2
AA6 NC#AA5 NC#V2
DPC
NC#AA6 Y4
NC#Y4 W5
NC#W5 Cap (nF) Bitd [5:4]
U1 AA3 PLL_ANALOG_OUT 1 DIS@ 2
1 FB_VDDCI W1 NC#U1 NC#AA3 Y2 RV17
TV23 U3 NC#W1 NC#Y2 16.2K_0402_1%
680nF 00
Y6 NC#U3 J8 +1.8VGS
1 PLL_ANALOG_IN AA1 NC#Y6 NC#J8 82nF 01 PS_2[3:1]=000 Strap Name :
TV18 NC#AA1
10nF 10 PS_2[5:4]=11

1
AMD recommend 09/25 @
PS_2[1] N/A
NC 11 RV57
8.45K_0402_1%
PS_2[2] N/A
I2C
GPU_SVD RV182 2 1 0_0402_5% GPU_VID3 PS_2[3] STRAP_BIOS_ROM_EN
<40> GPU_SVD

2
B R1 PS_2 B
GPU_SVC RV183 2 1 0_0402_5% GPU_VID1 R3 SCL
<40> GPU_SVC SDA PS_2[4] STRAP_BIF_VGA_DIS

1
1

0.68U_0402_10V
+3VGS AM26 @ DIS@
REAK CURRENT CONTROL ( M2 only ) R AK26 CV32 RV19
PS_2[5] N/A
GENERAL PURPOSE I/O AVSSN#AK26
U6 +3VGS 4.75K_0402_1%
GPIO_0
2

U10 AL25 2

2
RV10 T10 GPIO_1 G AJ25
GPIO_2 AVSSN#AJ25

2
10K_0402_5% VGA_SMB_DA2 U8
VGA_SMB_CK2 U7 SMBDATA AH24 RV371
@ SMBCLK B
RV15 DV1 1 2 GPU_GPIO5 T9 AG25 4.7K_0402_5%
<30> GPU_GPIO5_VGA
1

1K_0402_5% GPU_GPIO6 T8 GPIO_5_AC_BATT AVSSN#AG25 @

GPU_GPIO6 1 2 GPU_PROCHOT# RB751V_SOD323 T7 GPIO_6 DAC1 AH26
GPU_PROCHOT# <40>

1
@ P10 GPIO_7_BLON HSYNC AJ27
1 DIS@ GPIO_8_ROMSO VSYNC
P4 +1.8VGS
GPIO_9_ROMSI PS_3[3:1]=000 Strap Name :

2
CV17 1 2 P2
N6 GPIO_10_ROMSCK AD22 RV372
0.1U_0201_10V7K GPIO_11 RSET PS_3[5:4]=11

1
2 @ RV195 N5
@
0_0402_5% N3 GPIO_12 AG24
4.7K_0402_5%
DIS@ X76@
PS_3[1] BOARD_CONFIG[0] (Memory ID)
Y9 GPIO_13 AVDD AE22 RV21 PS_3[2] BOARD_CONFIG[1] (Memory ID)

1
GPU_VID3 N1 GPIO_14_HPD2 AVSSQ 8.45K_0402_1%
M4 GPIO_15_PWRCNTL_0 AE23 Pull down for none OBFF design
PS_3[3] BOARD_CONFIG[2] (Memory ID)

2
FOR TOPAS CORE POWER USE THM_ALERT# RV194 1 2 0_0402_5% THM_ALERT#_R R6 GPIO_16 VDD1DI AD23 PS_3
<25> THM_ALERT# GPIO_17_THERMAL_INT VSS1DI
W10 PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
GPIO_18

1
EX_THM@ GPIO19_CTF M2 1

0.68U_0402_10V
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
GPU_VID1 P8 AM12

CV33
X76@ PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
+1.8VGS P7 GPIO_20_PWRCNTL_1 CEC_1 @ RV24
N8 GPIO_21 2K_0402_1%
1 RV13 2 GPIO19_CTF AK10 GPIO_22_ROMCSB AK12 2

2
10K_0402_5% AM10 GPIO_29 RSVD#AK12 AL11 FOR M2
@ N7 GPIO_30 RSVD#AL11 AJ11 M1 doesn't have native SVI2
<8> VGA_CLKREQ# CLKREQB RSVD#AJ11
2

RV22 JTAG_TRSTB L6
JTAG_TDI L5 JTAG_TRSTB
10K_0402_5% JTAG_TDI
JTAG_TCK L3
DIS@ 1 @ 2 JTAG_TMS L1 JTAG_TCK AL13
+3VGS
1

RV26 5.11K_0402_5% 1 JTAG_TDO K4 JTAG_TMS GENLK_CLK AJ13

TV24 JTAG_TDO GENLK_VSYNC
+3VGS 1 DIS@ 2 TESTEN K7
C RV27 1K_0402_5% AF24 TESTEN C
RV18 2 DIS@ 1 4.7K_0402_5% THM_ALERT#_R NC#AF24 AG13
SWAPLOCKA AH12
AB13 SWAPLOCKB
W8 GENERICA
W9 GENERICB
W7 GENERICC AC19 PS_0
AD10 GENERICD PS_0
AJ9 GENERICE AD19 PS_1
+3VGS 1 AL9 NC#AJ9 PS_1
TV22 NC#AL9 AE17 PS_2
AC14 PS_2
1 PX_EN AB16 HPD1 AE20 PS_3
TV25 PX_EN PS_3
RV58 2 DIS@ 1 4.7K_0402_5% GPU_GPIO5 RV373 2 @ 1 4.7K_0402_5%

RV20 1 @ 2 JTAG_TDO AE19 ZZZ

10K_0402_5% AC16 TS_A
DBG_VREFG
VGA_AC_BATT
Hynix 2G
pull up DDC/AUX
+3VGS AE6
PLL/CLOCK DDC1CLK AE5 H2G@
DDC1DATA Part Number = X7667238L01
RPV1 @ AD2 OPTIAN FOR 3.3V tolerance VR,
1 8 JTAG_TRSTB AUX1P AD4 Check with VR vendor ZZZ
2 7 JTAG_TDI AUX1N +3VGS
3 6 JTAG_TMS AC11
4 5 JTAG_TCK DDC2CLK AC13
DDC2DATA Samsung 2G

2
2
10K_8P4R_5% XTALIN AM28 AD13
XTALOUT AK28 XTALIN AUX2P AD11 RV164 RV163
XTALOUT AUX2N 10K_0402_5% 10K_0402_5% S2G@
RV28 RV29 1 DIS@ 2 10K_0402_5% AC22 AD20 DIS@ @ Part Number = X7667238L02
XTALIN 1M_0402_5% XTALOUT RV31 1 DIS@ 2 10K_0402_5% AB22 XO_IN NC#AD20 AC20

1
1
DIS@ XO_IN2 NC#AC20 GPU_SVD ZZZ
AE16 GPU_SVC
NC#AE16 AD16
NC#AD16

2
D YV1 DIS@ D
4 3 SEYMOUR/FutureASIC AC1 Micron 2G
NC OSC REMOTE1+ T4 DDCVGACLK AC3 @ DIS@
<25> REMOTE1+ DPLUS THERMAL DDCVGADATA
1 2 TO EXTERNAL THERMAL SENSOR REMOTE1- T2 RV165 RV184
OSC NC <25> REMOTE1- DMINUS 10K_0402_5% 10K_0402_5% M2G@

1
27MHZ 10PF +-10PPM 7V27000050 +1.8VGS Part Number = X7667238L03
2 2
SJ10000G300 Enable MLPS RV33 1 DIS@ 2 10K_0402_5% GPIO28 R5
DIS@ CV19 DIS@ CV20 AD17 GPIO28_FDO
LV4 1 2 0_0402_5% +TSVDD AC17 TSVDD
10P_0402_50V8J 10P_0402_50V8J
1 1 TSVSS
1
CV21
1U_0402_6.3V6K Security Classification Compal Secret Data Compal Electronics, Inc.
DIS@ 2015/10/01 2016/10/01 Title
2 216-0841018 A0 SUN PRO ?S3 @
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(2/5)_MSIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 14 of 43
1 2 3 4 5
 1 2 3 4 5

+1.8VALW TO +1.8VGS
+0.95VALW TO +0.95VGS UV1E @ U?

Load switch
+1.8VGS
No Use GPU Display Port outpud AA27
AB24
AB32
GND
GND
GND
GND
A3
A30
AA13
AC24 GND GND AA16
UV1G @ AC26 GND GND AB10
U?
AC27 GND GND AB15
AD25 GND GND AB6

CV23

CV24
DP POWER NC/DP POWER
AD32 GND GND AC9
1 1 GND GND
A AG15 AE11 AE27 AD6 A
AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
+0.95VALW AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7

1U_0402_6.3V6K

10U_0603_6.3V6M
2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10

DIS@

DIS@
C29 AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
DP_VDDR#AF14 GND GND
1U_0402_6.3V6K

1 M32 B12
@ N25 GND GND B14
N27 GND GND B16
+0.95VGS P25 GND GND B18
2 U1895V AG20 AF6 P32 GND GND B20
1 14 +0.95VGS_LS RV5 1 2 0_0603_5% AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
DIS@ 2 VIN1 VOUT1 13 +0.95VGS AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
R1642 VIN1 VOUT1 AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
DP_VDDC#AG22 NC#AF9 GND GND

2
DGPU_PWR_EN 2 1 DGPU_PWR_EN_R 3 12 @ 1 2 DIS@ AD14 U25 B6
150K_0402_5% ON1 CT1 2200P_0402_50V7K C28 C32 DP_VDDC#AD14 U27 GND GND B8
4 11 V32 GND GND C1

CV28

CV29
+VL 0.1U_0201_10V7K

1
VBIAS GND W25 GND GND C32
1 1 GND GND
0.1U_0402_16V7K
DIS@

5 10 @ 1 2 AG14 AE1 W26 E28

ON2 CT2 DP_VSSR NC#AE1 GND GND
1

2200P_0402_50V7K C27 +1.8VGS AH14 AE3 W27 F10

+1.8VALW 6 9 AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12

1U_0402_6.3V6K

0.1U_0201_10V7K
7 VIN2 VOUT2 8 +1.8VGS_LS RV6 1 2 0_0603_5% 2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
2

VIN2 VOUT2 DP_VSSR NC#AG6 GND GND

C1380

AM18 AH5 F16

DIS@

DIS@
15 AF23 DP_VSSR NC#AH5 AF10 GND F18
GPAD DP_VSSR NC#AF10 GND

2
DIS@ AG23 AG9 F2
APE8990GN3B DFN 14P C31 AM20 DP_VSSR NC#AG9 AH8 GND F20
DIS@ AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
0.1U_0201_10V7K

1
SA00007PM00 AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
1 DP_VSSR NC#AM8 GND GND
@ C30 AF19 AG7 N16 F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
DP_VSSR NC#AG11 GND GND
1U_0402_6.3V6K

AE14 N21 GND F8

2 DP_VSSR P6 GND GND G10
P9 GND GND G27
R12 GND GND G31
B
AF17 AE10 R15 GND GND G8 B
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
216-0841018 A0 SUN PRO? S3 T18 GND GND H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
T11 GND VSS_MECH AM1
AA11 GND VSS_MECH AM32
+3VS to +3VGS M12
N11
GND
GND
GND
VSS_MECH

V11
GND

?
216-0841018 A0 SUN PRO S3

C C

+3VALW DIS@ +3VGS

S

3 1 4.7U_0603_6.3V6K
1
1U_0402_6.3V6K

1 1 @
QV16 CV36 RV40
G
2

CV37

ME2301DC-G_SOT23-3 680_0603_5%
SB000013I00 DIS@ @ +0.95VGS
3VGS_EN#

2 2 +VGA_CORE +1.8VGS
1 2

+5VALW

2
2

2
D RV56
2 RV39 RV53 470_0603_5%
DIS@ G 470_0603_5% 470_0603_5% @
RV42 DIS@ DGPU_PWR_EN# 1 2 S @ DIS@ @

1
RV43 10K_0402_5% 2N7002K_SOT23-3
3

1 1

6 1
20K_0402_5% QV17
1

3
D D
D 1 D 2 DGPU_PWR_EN# 5 DGPU_PWR_EN#
DIS@
R1640 2 1 0_0402_5% DGPU_PWR_EN_3VGS 2 DGPU_PWR_EN# DGPU_PWR_EN# 2 G G
<8,30,40> DGPU_PWR_EN CV38
G G
DIS@ QV18 0.1U_0201_10V7K DIS@ QV11 S QV21A @ S QV21B @
S S

4
1
2N7002K_SOT23-3 2 2N7002K_SOT23-3 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
3

D
3 D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(3/5)_PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 15 of 43
1 2 3 4 5
 1 2 3 4 5

A A

+1.5VGS
UV1D @ +1.8VGS
U?

AM30
MEM I/O PCIE_PVDD

PCIE

CV47

CV48
H13 AB23 1 1
H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24

CV75

CV88

CV74

CV80

CV83

CV87

CV76

CV77

CV78

CV79

CV81

CV82

CV89

CV86

CV85

CV84
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0201_10V7K

0.1U_0201_10V7K

0.1U_0201_10V7K

0.1U_0201_10V7K

0.1U_0201_10V7K
220U_B2_2.5VM_R35
J10 VDDR1 NC#AD24 AE24
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

1U_0402_6.3V6K
+ J23 VDDR1 NC#AE24 AE25 2 2
@ J24 VDDR1 NC#AE25 AE26

DIS@

DIS@
J9 VDDR1 NC#AE26 AF25
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDR1 NC#AF25

@
K10 AG26

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
K23 VDDR1 NC#AG26
K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +0.95VGS
L21 VDDR1 PCIE_VDDC N22
L22 VDDR1 PCIE_VDDC N23
VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22

CV49

CV50

CV51

CV52

CV53

CV54
+1.8VGS LEVEL PCIE_VDDC U22
TRANSLATION PCIE_VDDC 1 1 1 1 1 1
V22
AA20 PCIE_VDDC
AA21 VDD_CT

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AB20 VDD_CT AA15 2 2 2 2 2 2

CV55
B VDD_CT CORE VDDC B

@
AB21 N15

DIS@

DIS@

DIS@

DIS@

DIS@
1 VDD_CT VDDC N17
+3VGS VDDC R13
I/O VDDC R16

1U_0402_6.3V6K
2 AA17 VDDC R18
AA18 VDDR3 VDDC Y21

DIS@
AB17 VDDR3 VDDC T12

CV56
AB18 VDDR3 VDDC T15 +VGA_CORE
1 VDDR3 VDDC T17
V12 VDDC T20
Y12 VDDR4 VDDC U13

1U_0402_6.3V6K
2 U12 VDDR4 VDDC U16
VDDR4 VDDC U18

DIS@
VDDC V21 VGA_CORE Caps in power side sheet
VDDC V15
VDDC V17
VDDC V20
VDDC

POWER
Y13
VDDC Y16
VDDC Y18
VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDC
+1.8VGS
PLL
LV1 1 2 0_0603_5% +MPLL_PVDD

+0.95VGS
R21
CV39

CV40

CV41
10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

BIF_VDDC U21
1 1 1 BIF_VDDC
L8
+1.8VGS MPLL_PVDD
C C
2 2 2 +VGA_CORE

CV62
DIS@

DIS@

DIS@

ISOLATED
LV2 1 2 0_0402_5% +SPLL_PVDD CORE I/O 1
M13
H7 VDDCI M15

CV42

CV43
10U_0603_6.3V6M

1U_0402_6.3V6K
SPLL_PVDD VDDCI M16
1 1

1U_0402_6.3V6K
VDDCI M17 2
+0.95VGS VDDCI

@
M18
VDDCI M20
2 2 LV3 1 2 0_0402_5% +SPLL_VDDC H8 VDDCI M21
DIS@

DIS@
SPLL_VDDC VDDCI N20
J7 VDDCI
SPLL_PVSS

CV46

CV90
VGA_CORE Caps in power side sheet

1U_0402_6.3V6K

0.1U_0201_10V7K
1 1

216-0841018 A0 SUN PRO S3?

2 2

DIS@

DIS@
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(4/5)_PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 16 of 43
1 2 3 4 5
 1 2 3 4 5

@
M_DA[63..0] UV1C U?
<18,19> M_DA[63..0]
M_MA[15..0] GDDR5/DDR3 GDDR5/DDR3
<18,19> M_MA[15..0]
A M_DA0 K27 K17 M_MA0 A
M_DQM[7..0] M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
<18,19> M_DQM[7..0] DQA0_1 MAA0_1/MAA_1
M_DA2 H30 H23 M_MA2
M_DQS[7..0] M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
<18,19> M_DQS[7..0] DQA0_3 MAA0_3/MAA_3
M_DA4 G29 G24 M_MA4
M_DQS#[7..0] M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
<18,19> M_DQS#[7..0] DQA0_5 MAA0_5/MAA_5
M_DA6 F32 J19 M_MA6
M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
M_DA11 C28 DQA0_10 J14 M_MA8
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2
DQA0_16 MAA1_5/MAA_BA2 M_BA2 <18,19>
M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <18,19>
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <18,19>
M_DA19 D24 G14 M_MA14
M_DA20 E23 DQA0_19 MAA1_8/MAA_14 L16

MEMORY INTERFACE
M_DA21 F23 DQA0_20 MAA1_9/RSVD
M_DA22 D22 DQA0_21 E32 M_DQM0
+1.5VGS M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3
M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
DQA0_26 WCKA1_0/DQMA1_0
1

M_DA27 A19 D12 M_DQM5

DIS@ M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
RV44 M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
40.2_0402_1% M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
2

M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1

M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
B
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4 B
DQA1_3 EDCA1_0/QSA1_0
1

1 M_DA36 D14 D10 M_DQS5

DIS@ DIS@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV46 CV65 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
100_0402_1% 1U_0402_6.3V6K M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
2 M_DA40 E11 DQA1_7 H27 M_DQS#0
2

M_DA41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 M_DQS#1

M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
M_DA43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 M_DQS#3
M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
+1.5VGS M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B
M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 <18>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <19>
M_DA51 F7
DQA1_19
1

M_DA52 A5 H26 M_CLK0

DQA1_20 CLKA0 M_CLK0 <18>
DIS@ M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 <18>
RV45 M_DA54 C3
40.2_0402_1% M_DA55 E1 DQA1_22 G9 M_CLK1
DQA1_23 CLKA1 M_CLK1 <19>
M_DA56 G7 H9 M_CLK#1
M_CLK#1 <19>
2

M_DA57 G6 DQA1_24 CLKA1B

M_DA58 G1 DQA1_25 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 <18>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <19>
M_DA60 J6
DQA1_28
1

1 M_DA61 J1 G19 M_CAS#0

DQA1_29 CASA0B M_CAS#0 <18>
DIS@ DIS@ M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <19>
RV47 CV66 M_DA63 J5
100_0402_1% 1U_0402_6.3V6K DQA1_31 H22 M_CS0B#0
2 CSA0B_0 M_CS0B#0 <18>
+MVREFDA K26 J22
2

+MVREFSA J26 MVREFDA CSA0B_1

MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS1B#0 <19>
J25 K13
RV52 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1
C C
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <18>
DIS@ DIS@ J17 M_CKE1
CKEA1 M_CKE1 <19>
RV48 RV49
49.9_0402_1% 10_0402_1% G25 M_WE#0
WEA0B M_WE#0 <18>
1 2 2 1 DRST L10 H10 M_WE#1
<18,19> DRAM_RST DRAM_RST WEA1B M_WE#1 <19>

1 RV54 @ 1 2 51.1_0402_1% CV69 @1 2 0.1U_0201_10V7K K8

CLKTESTA
1

1 @ RV55 @ 1 2 51.1_0402_1% CV70 @1 2 L7

DIS@ DIS@ CV67 0.1U_0201_10V7K CLKTESTB
CV68 RV50 68P_0402_50V8J
120P_0402_50V8J 5.1K_0402_1% 2 Route 50ohms single-ended/100ohm diff and keep short
2 debug only, for clock observation,if not need, DNI. 216-0841018 A0 SUN PRO S3
?
2

Place close to GPU (within 25mm)

and place componment close to each other

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO(5/5)_MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 17 of 43
1 2 3 4 5
 1 2 3 4 5

DDR3 Memory Channel Rank 0:A0

M_DA[63..0]
<17,19> M_DA[63..0]
M_MA[15..0]
<17,19> M_MA[15..0]
M_DQM[7..0] +1.5VGS +1.5VGS
<17,19> M_DQM[7..0]
M_DQS[7..0]
<17,19> M_DQS[7..0]

1
A M_DQS#[7..0] DIS@ DIS@ A
<17,19> M_DQS#[7..0]
RV63 RV62
4.99K_0402_1% UV5 4.99K_0402_1% UV6

2
+FBA_VREF0 M8 E3 M_DA8 +FBA_VREF1 M8 E3 M_DA19
H1 VREFCA DQL0 F7 M_DA14 H1 VREFCA DQL0 F7 M_DA21
VREFDQ DQL1 F2 M_DA11 VREFDQ DQL1 F2 M_DA22
DQL2 DQL2

1
1 M_MA0 N3 F8 M_DA13 1 M_MA0 N3 F8 M_DA16
DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA10 DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA23
RV75 CV72 M_MA2 P3 A1 DQL4 H8 M_DA12 RV66 CV71 M_MA2 P3 A1 DQL4 H8 M_DA18
4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA9 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA20
2 M_MA4 P8 A3 DQL6 H7 M_DA15 2 M_MA4 P8 A3 DQL6 H7 M_DA17

2
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
M_MA6 R8 A5 M_MA6 R8 A5
M_MA7 R2 A6 D7 M_DA6 M_MA7 R2 A6 D7 M_DA25
M_MA8 T8 A7 DQU0 C3 M_DA2 M_MA8 T8 A7 DQU0 C3 M_DA29
M_MA9 R3 A8 DQU1 C8 M_DA5 M_MA9 R3 A8 DQU1 C8 M_DA26
M_MA10 L7 A9 DQU2 C2 M_DA0 M_MA10 L7 A9 DQU2 C2 M_DA28
M_MA11 R7 A10/AP DQU3 A7 M_DA4 M_MA11 R7 A10/AP DQU3 A7 M_DA27
M_MA12 N7 A11 DQU4 A2 M_DA1 M_MA12 N7 A11 DQU4 A2 M_DA30
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA24
M_MA14 T7 A13 DQU6 A3 M_DA3 M_MA14 T7 A13 DQU6 A3 M_DA31
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS

M_BA0 M2 B2 M_BA0 M2 B2
<17,19> M_BA0 BA0 VDD BA0 VDD
M_BA1 N8 D9 M_BA1 N8 D9
<17,19> M_BA1 BA1 VDD BA1 VDD
M_BA2 M3 G7 M_BA2 M3 G7
<17,19> M_BA2 BA2 VDD BA2 VDD
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK0 M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
<17> M_CLK0 CK VDD CK VDD
M_CLK#0 M_CLK#0 K7 R1 M_CLK#0 K7 R1
<17> M_CLK#0 CK VDD CK VDD
M_CKE0 K9 R9 M_CKE0 K9 R9
<17> M_CKE0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
1
1

B B
DIS@ DIS@
RV102 RV103 VRAM_ODT0 K1 A1 VRAM_ODT0 K1 A1
<17> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
40.2_0402_1% 40.2_0402_1% M_CS0B#0 L2 A8 M_CS0B#0 L2 A8
<17> M_CS0B#0 CS/CS0 VDDQ CS/CS0 VDDQ
M_RAS#0 J3 C1 M_RAS#0 J3 C1
<17> M_RAS#0 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9
<17> M_CAS#0
2
2

M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2

<17> M_WE#0 WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
M_DQS1 F3 VDDQ H2 M_DQS2 F3 VDDQ H2
1 DQSL VDDQ DQSL VDDQ
DIS@ M_DQS0 C7 H9 M_DQS3 C7 H9
CV73 DQSU VDDQ DQSU VDDQ
0.01U_0402_16V7K
2 M_DQM1 E7 A9 M_DQM2 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#1 G3 VSS J2 M_DQS#2 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#3 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST T2 VSS P9 DRAM_RST T2 VSS P9
<17,19> DRAM_RST RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1
DIS@ L1 NC/ODT1 VSSQ B9 DIS@ L1 NC/ODT1 VSSQ B9
RV111 J9 NC/CS1 VSSQ D1 RV110 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
SINGLE RANK:RV102,RV103 install 40.2 ohms
2

2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
C C
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
X76@ X76@

+1.5VGS +1.5VGS +1.5VGS

10U_0603_6.3V6M
CV105

1U_0402_6.3V6K
CV106

1U_0402_6.3V6K
CV107

1U_0402_6.3V6K
CV108

1U_0402_6.3V6K
CV113

10U_0603_6.3V6M
CV115

1U_0402_6.3V6K
CV120

1U_0402_6.3V6K
CV126

1U_0402_6.3V6K
CV123
1U_0402_6.3V6K
CV109

1U_0402_6.3V6K
CV112

1U_0402_6.3V6K
CV121
0.1U_0201_10V7K
CV125

10U_0603_6.3V6M
CV116

1U_0402_6.3V6K
CV117

1U_0402_6.3V6K
CV122

1U_0402_6.3V6K
CV124
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
DIS@

DIS@

DIS@
@

DIS@

DIS@

DIS@

@
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO_DDR3L_A1 Rank 0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 18 of 43
1 2 3 4 5
 1 2 3 4 5

DDR3 Memory Channel Rank 0:A1

+1.5VGS
+1.5VGS

1
1
DIS@
DIS@ RV119
RV118 4.99K_0402_1% UV4
4.99K_0402_1% UV3

2
A M_DA[63..0] +FBA_VREF3 M8 E3 M_DA35 A
<17,18> M_DA[63..0]

2
+FBA_VREF2 M8 E3 M_DA58 H1 VREFCA DQL0 F7 M_DA37
M_MA[15..0] H1 VREFCA DQL0 F7 M_DA61 VREFDQ DQL1 F2 M_DA34
<17,18> M_MA[15..0] VREFDQ DQL1 DQL2

1
F2 M_DA57 1 M_MA0 N3 F8 M_DA36
DQL2 A0 DQL3

1
M_DQM[7..0] 1 M_MA0 N3 F8 M_DA62 DIS@ DIS@ M_MA1 P7 H3 M_DA32
<17,18> M_DQM[7..0] A0 DQL3 A1 DQL4
DIS@ DIS@ M_MA1 P7 H3 M_DA59 RV127 CV118 M_MA2 P3 H8 M_DA38
M_DQS[7..0] RV126 CV119 M_MA2 P3 A1 DQL4 H8 M_DA63 4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 A2 DQL5 G2 M_DA33
<17,18> M_DQS[7..0] A2 DQL5 2 A3 DQL6
4.99K_0402_1% 0.1U_0201_10V7K M_MA3 N2 G2 M_DA56 M_MA4 P8 H7 M_DA39

2
M_DQS#[7..0] 2 M_MA4 P8 A3 DQL6 H7 M_DA60 M_MA5 P2 A4 DQL7
<17,18> M_DQS#[7..0]

2
M_MA5 P2 A4 DQL7 M_MA6 R8 A5
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA47
M_MA7 R2 A6 D7 M_DA52 M_MA8 T8 A7 DQU0 C3 M_DA43
M_MA8 T8 A7 DQU0 C3 M_DA50 M_MA9 R3 A8 DQU1 C8 M_DA46
M_MA9 R3 A8 DQU1 C8 M_DA55 M_MA10 L7 A9 DQU2 C2 M_DA42
M_MA10 L7 A9 DQU2 C2 M_DA49 M_MA11 R7 A10/AP DQU3 A7 M_DA44
M_MA11 R7 A10/AP DQU3 A7 M_DA54 M_MA12 N7 A11 DQU4 A2 M_DA41
M_MA12 N7 A11 DQU4 A2 M_DA51 M_MA13 T3 A12 DQU5 B8 M_DA45
M_MA13 T3 A12 DQU5 B8 M_DA53 M_MA14 T7 A13 DQU6 A3 M_DA40
M_MA14 T7 A13 DQU6 A3 M_DA48 M_MA15 M7 A14 DQU7
M_MA15 M7 A14 DQU7 A15/BA3 +1.5VGS
A15/BA3 +1.5VGS
M_BA0 M2 B2
M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
<17,18> M_BA0 BA0 VDD BA1 VDD
M_BA1 N8 D9 M_BA2 M3 G7
<17,18> M_BA1 BA1 VDD BA2 VDD
M_BA2 M3 G7 K2
<17,18> M_BA2 BA2 VDD VDD
M_CLK1 K2 K8
M_CLK#1 VDD K8 VDD N1
VDD N1 M_CLK1 J7 VDD N9
M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
<17> M_CLK1 CK VDD CK VDD
1

DIS@ DIS@ M_CLK#1 K7 R1 M_CKE1 K9 R9

<17> M_CLK#1 CK VDD CKE/CKE0 VDD +1.5VGS
RV139 RV140 M_CKE1 K9 R9
<17> M_CKE1 CKE/CKE0 VDD +1.5VGS
40.2_0402_1% 40.2_0402_1%
VRAM_ODT1 K1 A1
VRAM_ODT1 K1 A1 M_CS1B#0 L2 ODT/ODT0 VDDQ A8
<17> VRAM_ODT1
2

M_CS1B#0 L2 ODT/ODT0 VDDQ A8 M_RAS#1 J3 CS/CS0 VDDQ C1

B <17> M_CS1B#0 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 M_CAS#1 K3 C9
<17> M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
<17> M_CAS#1 CAS VDDQ WE VDDQ
1 M_WE#1 L3 D2 E9
<17> M_WE#1 WE VDDQ VDDQ
DIS@ E9 F1
CV154 VDDQ F1 M_DQS4 F3 VDDQ H2
0.01U_0402_16V7K M_DQS7 F3 VDDQ H2 M_DQS5 C7 DQSL VDDQ H9
2 M_DQS6 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
M_DQM4 E7 A9
M_DQM7 E7 A9 M_DQM5 D3 DML VSS B3
M_DQM6 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 M_DQS#4 G3 VSS J2
M_DQS#7 G3 VSS J2 M_DQS#5 B7 DQSL VSS J8
M_DQS#6 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
VSS P1 DRAM_RST T2 VSS P9
DRAM_RST T2 VSS P9 RESET VSS T1
<17,18> DRAM_RST RESET VSS VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS

1
J1 B1
NC/ODT1 VSSQ
1

J1 B1 DIS@ L1 B9
DIS@ L1 NC/ODT1 VSSQ B9 RV138 J9 NC/CS1 VSSQ D1
RV137 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2

2
NCZQ1 VSSQ E2 VSSQ E8
SINGLE RANK:RV139,RV140 install 40.2 ohms
2

VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 C
H5TC2G63FFR-11C_FBGA96 X76@
X76@

+1.5VGS +1.5VGS +1.5VGS

1U_0402_6.3V6K
CV152

1U_0402_6.3V6K
CV135

10U_0603_6.3V6M
CV138

1U_0402_6.3V6K
CV148
1U_0402_6.3V6K
CV145
10U_0603_6.3V6M
CV128

1U_0402_6.3V6K
CV132

1U_0402_6.3V6K
CV164
1U_0402_6.3V6K
CV158

0.1U_0201_10V7K
CV134

1U_0402_6.3V6K
CV136

10U_0603_6.3V6M
CV139

1U_0402_6.3V6K
CV141

1U_0402_6.3V6K
CV144

1U_0402_6.3V6K
CV146

1U_0402_6.3V6K
CV193
0.1U_0201_10V7K
CV147
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@

DIS@

DIS@
DIS@
DIS@

DIS@

DIS@

DIS@
DIS@

DIS@

DIS@

DIS@

DIS@

@
@
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EXO/MESO_DDR3L_A2 Rank 0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 19 of 43
1 2 3 4 5
 5 4 3 2 1

LCD Power Circuit

R-short W=60mils
+3VS +LCDVDD_CONN
Camera
D R3110 D
W=60mils U5
5 1 +LCDVDD 1 2 +3VS

4.7U_0603_6.3V6K
IN OUT
2 0_0805_5% R318 1 @ 2 0_0603_5% +3VS_CMOS

C128
GND 1
R3114 1 2 0_0402_5% 4 3 Q4
<7,30> SOC_ENVDD EN OC ME2301DC-G_SOT23-3
EM5203AJ-20 SOT23 5P 2
W=20mils W=20mils

D
SA00008R900 3 1
@
R3111 1 2 0_0402_5%
<30> EC_ENVDD

G
1 1

2
R119 C2143 C2144

1
1 150K_0402_5% 0.1U_0201_10V K X5R 10U_0603_6.3V6M
R120 C1220 CMOS_ON#_R 2 2
1U_0402_6.3V6K <30> CMOS_ON#
100K_0402_5%
2 1
@

2
C132
0.1U_0201_10V K X5R
2

+3VS

@
5

U15
From PCH 2
P

<7,30> ENBKL B 4 DISPOFF#

1 Y
From EC <30> BKOFF# A
eDP CONN.
G

C C

2
+LEDVDD
3
2

R124 B+
R211 TC7SH08FUF_SSOP5 100K_0402_5%
W=100mils
100K_0402_5% @ R121 2 1 0_0805_5%
1
1
@
1

C133
R123 1 2 0_0402_5% 4.7U_0805_25V6-K
2 R-short
JEDP1
1
2 1
follow CZ 3 2
3
4
5 4
<7> INVT_PWM 5
DISPOFF# 6
7 6
<7> EDP_HPD 7
8
W=60mils +LCDVDD_CONN
9 8
C134 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 10 9
<7> EDP_AUXN 10
eDP C135 1 2 0.1U_0201_10V K X5R EDP_AUXP_C 11
<7> EDP_AUXP 11
12
C136 1 2 0.1U_0201_10V K X5R EDP_TXP0_C 13 12
<7> EDP_TXP0 13
C137 1 2 0.1U_0201_10V K X5R EDP_TXN0_C 14
<7> EDP_TXN0 15 14
C138 1 2 0.1U_0201_10V K X5R EDP_TXP1_C 16 15
<7> EDP_TXP1 16
C139 1 2 0.1U_0201_10V K X5R EDP_TXN1_C 17
<7> EDP_TXN1 18 17

EMI C1211 1 2 10P_0402_50V8J

+3VS_CMOS
+3VS
USB20_N3_R
19
20
21
18
19
20
@EMI@ USB20_P3_R 22 21
Camera W=20mils 23 22
DMIC 24 23
<22> DMIC_CLK 25 24
<22> DMIC_DAT 25
26
B
EMI <30> TS_DISABLE#
R2013 1 @
R122 1

2 0_0402_5%
2 0_0402_5% TS_DISABLE#_R
+3VS

USB20_N1_R
27
28
29
26
27
28
B

Touch <9> USB20_N1

R130 1 2 0_0402_5% USB20_P1 30 29
<8> TS_I2C_RST# <9> USB20_P1 30
31
YOGA@ 32 31
<8> I2C1_SCL_TS 32
R125 1 2 0_0402_5% 33
<8> I2C1_SDA_TS 33
<8> 34
TS_INT# 35 34
+3VS 35
L6 @EMI@ 36 41
<23,30> EC_SMB_DA4 36 G1
1 2 USB20_N3_R 37 42
<9> USB20_N3 <23,30> EC_SMB_CK4 38 37 G2 43
R3115 1 2 0_0402_5% TAB_SW#_SB 39 38 G3 44
Camera 4 3 USB20_P3_R
G sensor /Hall sensor <30> TAB_SW# 40 39 G4 45
<9> USB20_P3 +3VALW 40 G5
@
MCM1012B900F06BP_4P ACES_50398-04041-001
SP010013I00
R127 1 2 0_0402_5% R3116 1 2 0_0402_5% ME@
YOGA@

RHS280
1 2
+3VALW
100K_0402_5%
2

YOGA@ 1
VDD

CHS250
0.1U_0201_10V K X5R 3 TAB_SW#_MB
2 OUTPUT
GND

2
YOGA@
UHS17 CHS251
1

APX8132 SOT-23F 3P 10P_0402_50V8J

A SA00008K800 1 A
YOGA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP / Camera
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 20 of 43
5 4 3 2 1
 5 4 3 2 1

EMI Near JHDMI1

RH326 1 @EMI@ 2 0_0402_5%

MCM1012B900F06BP_4P
CH229 1 2 0.1U_0201_10V K X5R HDMI_CLK+_CK_C 4 3 HDMI_CLK+_CONN +5V_Display
<7> HDMI_CLK+_CK
UH6

CH230 1 2 0.1U_0201_10V K X5R HDMI_CLK-_CK_C 1 2 HDMI_CLK-_CONN +5VS 3

<7> HDMI_CLK-_CK OUT W=40mils
1

1
LH8 EMI@ CH2143 CH2144 1
EMI@ EMI@ IN CH140
1
RH330 1 @EMI@ 2 0_0402_5% 3.3P_0402_50V8J 3.3P_0402_50V8J 2 0.1U_0201_10V K X5R

2
CH141 GND 2
RH332 1 @EMI@ 2 0_0402_5% 0.1U_0201_10V K X5R
D 2 D
G5250Q1T73U_SC59-3

MCM1012B900F06BP_4P
<7> HDMI_TX0+_CK CH231 1 2 0.1U_0201_10V K X5R HDMI_TX0+_CK_C 4 3 HDMI_TX0+_CONN For HDMI

CH232 1 2 0.1U_0201_10V K X5R HDMI_TX0-_CK_C 1 2 HDMI_TX0-_CONN

<7> HDMI_TX0-_CK

1
LH9 EMI@ CH2145 CH2146
EMI@ EMI@
RH333 1 @EMI@ 2 0_0402_5% 3.3P_0402_50V8J 3.3P_0402_50V8J

2
RH334 1 @EMI@ 2 0_0402_5%

MCM1012B900F06BP_4P
CH233 1 2 0.1U_0201_10V K X5R HDMI_TX1+_CK_C 4 3 HDMI_TX1+_CONN
<7> HDMI_TX1+_CK
+3VS
<7> HDMI_TX1-_CK CH234 1 2 0.1U_0201_10V K X5R HDMI_TX1-_CK_C 1 2 HDMI_TX1-_CONN

1
LH10 EMI@ CH2147 CH2148
EMI@ EMI@
RH335 1 @EMI@ 2 0_0402_5% 3.3P_0402_50V8J 3.3P_0402_50V8J ME@

1
C RH133 JHDMI1
RH336 1 @EMI@ 2 0_0402_5% QH5 2HDMI_DET_R 1 2 HDMI_DET 19
MMBT3904_NL_SOT23-3 B 150K_0402_5% 18 HP_DET
+5V_Display +5V
E 17

3
DDC/CEC_GND

2
MCM1012B900F06BP_4P HDMIDAT_R 16
CH235 1 2 0.1U_0201_10V K X5R HDMI_TX2+_CK_C 4 3 HDMI_TX2+_CONN @ HDMICLK_R 15 SDA
<7> HDMI_TX2+_CK SCL
HDMI_HPD_R RH138 14
<7> HDMI_HPD 13 Utility
RH338 200K_0402_5%
CH236 1 2 0.1U_0201_10V K X5R HDMI_TX2-_CK_C 1 2 HDMI_TX2-_CONN 15K_0402_5% HDMI_CLK-_CONN 12 CEC
<7> HDMI_TX2-_CK

1
11 CK-
CK_shield

1
LH11 EMI@ HDMI_CLK+_CONN 10
RH339 HDMI_TX0-_CONN 9 CK+
RH337 1 @EMI@ 2 0_0402_5% RH137 8 D0-
68K_0402_5% D0_shield

1
1
C CH2149 CH2150 100K_0402_5% HDMI_TX0+_CONN 7 C
EMI@ EMI@ @ HDMI_TX1-_CONN 6 D0+

2
3.3P_0402_50V8J 3.3P_0402_50V8J 5 D1-

2
2
HDMI_TX1+_CONN 4 D1_shield 23
HDMI_TX2-_CONN 3 D1+ GND1 22
2 D2- GND2 21
RPH29 HDMI_TX2+_CONN 1 D2_shield GND3 20
5 4 D2+ GND4
6 3 ACON_HMRBL-AK120D
7 2
8 1 DC232004700
499 +-1% 8P4R

RPH30
5 4
6 3
7 2
8 1 +3VS

499 +-1% 8P4R

1

D
2
G
S QH7
3

2N7002K_SOT23-3

+3VS +3VS +5V_Display

2.2K_0402_5%

2.2K_0402_5%
1

B B

RH144 RH143
QH6A
RH145

RH146

4.7K_0402_5% 4.7K_0402_5%
2

2N7002KDW 2N SC88-6 @ESD@ DH1 @ESD@ DH2 @ESD@ DH3

HDMICLK_R 9 10 1 1 HDMICLK_R HDMI_TX1-_CONN 9 10 1 1 HDMI_TX1-_CONN HDMI_TX0-_CONN 9 10 1 1 HDMI_TX0-_CONN
1
2

1 6 HDMICLK_R
<7> HDMICLK_NB
HDMIDAT_R 8 9 2 2 HDMIDAT_R HDMI_TX1+_CONN 8 9 2 2 HDMI_TX1+_CONN HDMI_TX0+_CONN 8 9 2 2 HDMI_TX0+_CONN
5

HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX2-_CONN 7 7 4 4 HDMI_TX2-_CONN HDMI_CLK-_CONN 7 7 4 4 HDMI_CLK-_CONN

<7> HDMIDAT_NB 4 3 HDMIDAT_R
+5V_Display 6 6 5 5 +5V_Display HDMI_TX2+_CONN 6 6 5 5 HDMI_TX2+_CONN HDMI_CLK+_CONN 6 6 5 5 HDMI_CLK+_CONN
QH6B
2N7002KDW 2N SC88-6 3 3 3 3 3 3

8 8 8

L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title
HDMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 21 of 43
5 4 3 2 1
 A B C D E

+5VS
ALC3240 +5VS_PVDD 1
RA1
2 Input

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
+3VDD_CODEC 0_0805_5%
2 1 2 1
+1.8VS

CA3
CA1

CA2
CA32
1 2 1 2
2 place close audio codec
CA17
4.7U_0603_6.3V6K +3VDD_CODEC
1
@
Combo Jack

2
29

34
39
1
UA1
RA38 (Normal Open)

PVDD1
PVDD2
CPVDD
DVDD
<8> HDA_SDIN0 33_0402_5% 2 1 RA12 HDA_SDIN0_AUDIO 7 100K_0402_5%
1
4 SDATA-IN 25 HP_OUTL 1
<8> HDA_SDOUT_AUDIO Headphone

1
SDATA-OUT HPOUT-L(PORT-I-L) 26 HP_OUTR PLUG_IN_R RA13 1 2 200K_0402_1%~N
HPOUT-R(PORT-I-R) PLUG_IN <27>

EMI PC_BEEP 11

5
PCBEEP
VREF
22
27 CPVEE
CA27 1

2
2 1U_0402_6.3V6K

1
AGND

Place RA10 & CA12 on AGND moat <8> SM010016720

22P_0402_50V8J @EMI@ CA12

HDA_BITCLK_AUDIO
33_0402_5% 2 @EMI@ 1 RA10
BCLK CPVEE
CA20 1U_0402_6.3V6K EXT_MIC_SLEEVE EMI@
SM010016720
RA19 2 1 FBMA-L11-160808-121LMT 0603
EMI HGNDB
W=40mils HGNDB <27>
W=40mils EXT_MIC_RING2 EMI@ RA20 2 1 FBMA-L11-160808-121LMT 0603 HGNDA HGNDA <27>
RA6 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R HP_OUTL EMI@ RA22 1 2 47_0402_5% HPOUT_L
wide 40MIL 1 2 2.2K_0402_5% EXT_MIC_SLEEVE 14 MIC2-L(PORT-F-L)/RING
MIC2-R(PORT-F-R)/SLEEVE
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
18 LINE1-L
EMI HP_OUTR EMI@ RA23 1 2 47_0402_5% HPOUT_R
HPOUT_L <27>
HPOUT_R <27>
AGND

RA7 CA19 2 1 2.2U_0402_6.3V6M 15 24

+LINE1-VREFO-R SD028470A80
23 MIC2-CAP LINE1-VREFO-L 12 PLUG_IN_R SD028470A80
+MIC2-VREFO MIC2-VREFO HP/ LINE1-JD(JD1) SM01000NY00
SPK_L2+ 35 2
External DMIC
For Universal Audio Jack

470P_0402_50V7K

470P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
SPK-OUT-LP GPIO0/DMIC-DATA12

2
2
SPK_L1- 36 3 DMIC_CLK_R 220_0402_5% 2 1 LA1 DMIC_DAT <20>
SPK-OUT-LN GPIO1/DMIC-CLK 1 1

2
SPK_R1- 37 EMI@ DMIC_CLK <20> LINE1-L CA21 2 1 1U_0402_6.3V6K

RA27
RA26

CA35

CA36
10K_0402_5%
10K_0402_5%
SPK_R2+ 38 SPK-OUT-RN 8 @ @

CA33

CA34
SPK-OUT-RP DVDD-IO +IOVDD_CODEC
AGND AGND

LINE1-R CA22 2 1 1U_0402_6.3V6K

1
2.2U_0402_6.3V6M 1 2 CA26 2 2
1

1
1
LDO1 21 28
2.2U_0402_6.3V6M 1 2 CA16 LDO2 32 LDO1-CAP CBN 30 CA15
LDO3 6 LDO2-CAP CBP RA29 1 2 4.7K_0402_5% AGND AGND AGND AGND AGND AGND
LDO3-CAP 1U_0402_6.3V6K
2.2U_0402_6.3V6M 1 2 CA13 2
40 1 2 EC_MUTE# <30> +LINE1-VREFO-R RA32 1 2 4.7K_0402_5% EMI@ EMI@ EMI@ EMI@
10 PDB 0_0402_5% RA11 2 1

VD33STB
9 DC DET 41

AVDD1
AVDD2
AVSS1
AVSS2
<8> HDA_SYNC_AUDIO SYNC THERMAL PAD RA8 10K_0402_5%
@

20
33
19
31

16
2
Output 2

+5VDDA_CODEC
AGND +3VALW
+1.8VS EMI
RA5 1 2
SPEAK 4 ohm 40MIL
0_0402_5% SPEAK 8 ohm 20MIL ME@
Place RA5 on AGND moat EMI@ JSPK1
SPK_R1- LA5 1 2 FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 1
CA8 1 2 1U_0402_6.3V6K SPK_R2+ LA6 1 EMI@ 2 FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 2 1
AGND 2
SPK_L1- LA7 1 EMI@ 2 FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN 3
SPK_L2+ LA8 1 2 FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 4 3
Place near Pin33 EMI@ 5 4
6 G1
120 Ohm bead: SM010016720

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
G2
1 1 1 1 ACES_50278-00401-001

@EMI@ CA28

@EMI@ CA29

@EMI@ CA30

@EMI@ CA31
+5VS +5VDDA_CODEC Each Plajorm Power Net Support List
2 2 2 2

+5VS +5VDDA_CODEC
+1.5VS +1.8VS +3VS +5VS +3VALW
RA4 ESD protection needs to be placed near connector side
2 1 1.5V(S0) 1.8V(S0) 3.3V(S0) 5V(S0) 3.3V(S0~S5)
0_0603_5% Intel Broadwell V X V V V ESD
0.1U_0201_10V K X5R

1 1
1U_0402_6.3V6K

CA7

Intel Skylake X V V V V
CA11

Place RA4 on AGND moat +5VS

2 2 @ESD@ DA3
SPK_R1-_CONN 6 3 SPK_L2+_CONN
I/O4 I/O2

3 3
5 2
AGND VDD GND

Place near Pin20

SPK_R2+_CONN 4 1 SPK_L1-_CONN
I/O3 I/O1

Each Pla(orm HDA Link Voltage Support (Pin 8) AZC099-04S.R7G_SOT23-6

3.3V 1.5V
Intel Broadwell V (default) V
Intel Skylake V (default) V

+1.8VS +IOVDD_CODEC +3VS +3VDD_CODEC PC Beep EMI

+IOVDD_CODEC +3VS +3VDD_CODEC
place close audio codec

RA3 2 1 0_0603_5% RA40 1 2 47K_0402_5% BEEP_N CA37 2 1 1U_0402_6.3V6K PC_BEEP RA42 1 2 0_0201_5%
+1.8VS EC Beep <30> BEEP#
RA2 2 1 0_0603_5% RA41 1 2 47K_0402_5%
APU Beep <8> APU_SPKR
RA43 1 2 0_0201_5%
1U_0402_6.3V6K
0.1U_0201_10V K X5R

100P_0402_50V8J
CA40 @ESD@

1 1
0.1U_0201_10V K X5R

1
CA5
CA4

1
RA39 @EMI@ CA41 1 2 0.1U_0201_10V K X5R
CA6

4 4
27K_0402_5%
2

2 2
Place near Pin8 2 @EMI@ CA42 1 2 0.1U_0201_10V K X5R
2

update from 4K7 to 27K

Place near Pin1

GND AGND
AGND

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC3240
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 22 of 43
A B C D E
 A B C D E F G H

HDD SATA HDD Conn.

Near Connector JHDD1

1
CH142 2 1 0.01U_0402_16V7K SATA_ATX_C_DRX_P0 2 GND
<9> SATA_ATX_DRX_P0 A+
<9> SATA_ATX_DRX_N0 CH143 2 1 0.01U_0402_16V7K SATA_ATX_C_DRX_N0 3
4 A-
CH144 1 2 0.01U_0402_16V7K SATA_DTX_ARX_N0 5 GND
<9> SATA_DTX_C_ARX_N0 CH145 1 2 0.01U_0402_16V7K SATA_DTX_ARX_P0 6 B-
<9> SATA_DTX_C_ARX_P0 7 B+
GND
1 1

RH141 1 @ 2 0_0805_5% +3V_HDD 8

+3VS V33
9
10 V33
R-short 11 V33
GND
12
13 GND
RH142 1 2 0_0805_5% +5V_HDD 14 GND
+5VS 15 V5
16 V5
Near HDD 17 V5
18 GND
+5V_HDD 19 Reserved
20 GND
1 V12
@ESD@ 21 24
CH199 22 V12 GND 23
1 1 1 V12 GND
RFS@ 0.1U_0201_10V K X5R
CH146 CH147 CH148 2
22P_0402_50V8J 0.1U_0201_10V K X5R 10U_0603_6.3V6M SDAN_603006-022041
2 2 2
ESD ME@
DC01000CE00

RF for S-series

2 2

(G-Sensor for 360-degree reverse)

3 3

+3VS +3VS
UGS2 YOGA@
RGS2 1 2 0_0402_5% +3VS_GS_R 7 3
10 VDD VDDIO 11
CSB PS

0.1U_0201_10V K X5R
0.1U_0201_10V K X5R

TP1 5 4
TP2 6 INT1 NC
2 INT2 2

@
YOGA@

1
SDO

CGS4
CGS3

2 9
<20,30> EC_SMB_DA4 12 SDx GND 8
1 <20,30> EC_SMB_CK4 SCx GNDIO 1
BMA250E_LGA12

SMB Address: 0001 1000

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/TPM/APS/NFC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 23 of 43
A B C D E F G H
 A B C D E

1 1

+3VS R-short +3VS_WLAN

NGFF for WLAN / BT(Key E)

RWL153
1 2
+3VS_WLAN
0_0805_5%
JWLAN1
1 2 1 1
3 GND 3.3VAUX 4 CWL155 CWL156
<9> USB20_P2 USB_D+ 3.3VAUX
BT 5 6
<9> USB20_N2 7 USB_D- LED1# 8 4.7U_0603_6.3V6K 0.1U_0201_10V K X5R
9 GND PCM_CLK 10 2 2
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
2 2
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22
23 SDIO_WAKE# UART_RX
SDIO_RESET#

24
25 UART_TX 26
27 GND UART_CTS 28
<5> PCIE_ATX_C_DRX_P2 29 PETP0 UART_RTS 30 1 2 0_0402_5%
RWL155
<5> PCIE_ATX_C_DRX_N2 PETN0 RESERVED EC_TX <26,30>
31 32 RWL156 1 2 0_0402_5%
GND RESERVED EC_RX <26,30>
33 34
<5> PCIE_DTX_C_ARX_P2 35 PERP0 RESERVED 36
WLAN <5> PCIE_DTX_C_ARX_N2
37 PERN0 COEX3 38
39 GND COEX2 40
<9> CLK_PCIE_WLAN REFCLKP0 COEX1
41 42 SUSCLK_R RWL157 1 2 0_0402_5%
<9> CLK_PCIE_WLAN# REFCLKN0 SUSCLK RTC_CLK <8>
43 44 WL_RST# RWL164 1 2 0_0402_5%
GND PERST0# APU_PCIE_RST# <8,13,27,28>
<8> WLAN_CLKREQ# RWL158 1 2 0_0402_5% WLAN_CLKREQ#_R 45 46 BT_OFF#_R RWL159 1 2 0_0402_5%
CLKEQ0# W_DISABLE2# BT_OFF# <8>
RWL162 1 2 0_0402_5% WAKE#_R 47 48 WLAN_OFF#_R
@ 49 PEWAKE0# W_DISABLE1# 50
51 GND I2C_DATA 52 RWL161 1 2 0_0402_5%
RSRVD/PETP1 I2C_CLK WLAN_OFF# <8>
53 54
55 RSRVD/PETN1 ALERT 56
@ 57 GND RESERVED 58
RWL510 1 2 0_0402_5% 59 RSRVD/PERP1 RESERVED 60
Note: The real behavior of BT_OFF# are
<8> APU_PCIE_WAKE#
61 RSRVD/PERN1 RESERVED 62 BT_OFF#=LOW, BT=OFF
RWL511 1 2 0_0402_5% 63 GND RESERVED 64 BT_OFF#=HIGH, BT=ON
<30> EC_PCIE_WAKE# RESERVED 3.3VAUX
65 66
67 RESERVED 3.3VAUX
<28> PCIE_WAKE# GND

69 68
MTG77 MTG76
R-short
BELLW_80152-3221
ME@
3 3
SP070013E00

2
@
RWL507 RWL508
100K_0402_5% 100K_0402_5%

4 4

Security Classification
2015/10/01
Compal Secret Data
2016/10/01 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF WLAN / BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 24 of 43
A B C D E
 5 4 3 2 1

+3VGS +3VS

Thermal Sensor

1
D D
EX_THM@ @

RTS186 RTS176
0_0402_5%
0_0402_5%
DDR VRAM

2
Close to UTS17 +3V_Thermal GPU +EC_VCCA +EC_VCCA

UTS17 EX_THM@

16.5K_0402_1%

16.5K_0402_1%
<14> REMOTE1+

1
1 1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 <7,14,30>
EX_THM@

RTS336

RTS337
CTS587 REMOTE1+ 2 7 EC_SMB_DA2 DIS@
D+ SDA EC_SMB_DA2 <7,14,30>
2200P_0402_50V7K
2 REMOTE1- 3 6 THM_ALERT#
<14> REMOTE1- THM_ALERT# <14>

2
RTS335 D- ALERT#
1 2 T_CRIT# 4 5
+3V_Thermal T_CRIT# GND
<30> DDR_TEMP <30> VRAM_TEMP
EX_THM@ 4.7K_0402_5%
NCT7718W_MSOP8

1
RTS338 RTS339
SMB Address: 1001100x 100K +-1% 0402 B25/50 4250K DIS@ 100K +-1% 0402 B25/50 4250K
REMOTE1+/-:
Trace width/space:10/10 mil

2
Trace length:<8"
ECAGND ECAGND

REMOTE1+
Close to CPU
1
1

C
@ CTS588 2 QTS1 @
C 100P_0402_50V8J B MMST3904-7-F_SOT323-3 C
2 E
3

REMOTE1-

+3VS
CPU VGA LAN NGFF Shielding Clip
B
FAN Conn Larger B

H1 H2 H3 H14 H18 H15 H16

R-short
1

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA CLIP1 CLIP10 CLIP11
R235 HOLEA HOLEA HOLEA
+5VS 10K_0402_5%
JFAN1

1
1

1
H17 @ @ @
2

1
1
R168 2 1 0_0603_5% +5VS_FAN 5 7 HOLEA
4 5 G2 6 LANGAN LANGAN
<30> EC_FAN_SPEED1 4 G1
<30> EC_FAN_PWM1 3 H_3P3-G H_3P3-G H_3P3-G H_3P3 H_3P3 H_3P3 H_2P5
2 3

1
1 2
2 <30> EC_FAN_REVERSE
C162
1
H4 H6 H7 H8 H19 H20
Smaller
10U_0603_6.3V6M ACES_87213-0500G HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H_3P2 CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 CLIP9 CLIP12 CLIP14
1 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
ME@
1
1

1
@ @ @ @ @ @ @ @ @ @

1
H_5P9X4P6-G H_2P5-G H_4P6-G H_2P5-G H_4P6-G H_2P5-G

H9 H10 H11 H12 H13

FD1 FD2 FD3 FD4 HOLEA HOLEA HOLEA HOLEA HOLEA
1
1

1
H_3P5X2P5N H_1P5N H_1P5N H_2P5N H_3P5X2P5N

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title
FAN / Thermal Senser
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 25 of 43
5 4 3 2 1
Power Button LED Keyboard
+3VS
JKB2

R263 2 1 470_0402_5% CAPS_LED#_R 1

2 1
Power (White) SS@ SS@
<30> CAPS_LED#
KSO15 3 2
LED3 KSO10 4 3
R175 KSI[0..7] KSO11 5 4
KSI[0..7] <30> 5

0.1U_0201_10V K X5R
PWR_LED# 1 2 1 2 1 KSO14 6
<30> PWR_LED#
100_0402_1% +3VL KSO[0..17] KSO13 7 6
KSO[0..17] <30> 7
C201 KSO12 8
19-217-T1D-DP1Q2QY-3T_WHITE KSO3 9 8
ESD@ 9
2 KSO6 10
KSO8 11 10
KSO7 12 11
12

3
KSO4 13
R177 13
KSO2 14
1 2 1 2 KSI0 15 14
KSO1 16 15
KSO5 17 16
YOGA@ 160_0402_1% KSI3 18 17
LED4 YOGA@ KSI2 19 18
LTW-110DC5-C_WHITE KSO0 20 19
KSI5 21 20
+3VS KSI4 22 21
KSO9 23 22
For S15 KSI6 24 23
24
KSI7 25
KSI1 26 25
KSO16 27 26
@ KSO17 28 27
R264 2 1 470_0402_5% NUM_LED#_R 29 28
29

Touch Pad
30
<30> NUM_LED# 30
31
<30> EC_GPIO72 32 31
1 32
C1379 @ESD@ 33
0.1U_0201_10V K X5R GND 34
2 GND

+3VS RTP258 1 2 0_0402_5%

@ ACES_51510-0320N-P01
CTP163
0.1U_0201_10V K X5R
ME@
JTP1
8
7 GND
GND
TP_VCC 6
6

Hall Senser & Button

TP_CLK 5
<30> TP_CLK 5
TP_DATA 4
<30> TP_DATA 3 4
RTP260 1 2 0_0402_5% TP_SMB_CLK 2 3
<8> APU_SCLK1_TP 2
RTP261 1 2 0_0402_5% TP_SMB_DATA 1
<8> APU_SDATA1_TP 1
ACES_88514-00601-071 RHS279
ME@ 1 2
+3VALW
SP010014M00 100K_0402_5%
3

2
1 1 1

VDD
@ @ @ESD@
CTP164 CTP165 DTP5 CHS248
100P_0402_50V8J 100P_0402_50V8J PSOT24C_SOT23-3 0.1U_0201_10V K X5R 3
2 2 2 OUTPUT LID_SW# <30>
1

GND
2
UHS16 CHS249

1
APX8132 SOT-23F 3P 10P_0402_50V8J
ESD SA00008K800 1

For Debug
Keyboard Backlight +3VALW 1
2
JP3
1
<24,30> EC_TX 3 2
<24,30> EC_RX 3
4
4
ACES_85205-0400
ME@
+5VS +VCC_KB_LED

+5VS +5VALW ME@

KBL@
QKBL121 ACES_51512-0040N-P01
1
1

KBL@ @ 3 1 4 6
RKBL1 RKBL2 3 4 G2 5
10K_0402_5% 10K_0402_5% ME2301DC-G_SOT23-3 2 3 G1
KBL@ CKBL906

KBL@ CKBL908
10U_0603_6.3V6M

0.1U_0201_10V K X5R

1 2
G

1 2
Power Botton Power Botton
2

2
2

KBL@ 1 +3VL
1 2 JKBL1

RKBL3 1
2 1
For S Series For YOGA

2
KBL@ 0_0402_5% @
CKBL907 SS@ ON/OFF#
1 2 0.01U_0402_16V7K R170
2 SW6 100K_0402_5%
1

RKBL4 SMT1-05_4P
5
6

1
0_0402_5%
OUT

3
4 2 SW8
ON/OFF# G 7
2 3 1 ON/OFF# <30> 6
<30> KB_BL_PWM G TSS31-EG2-160-T18-S017_3P
IN @ 5
GND

G
YOGA@ 4
G
QKBL122
DTC124EKAT146_SC59-3
3

2
ESD
3

2
D24
MESC5V02BD03 3P C/A SOT23 ESD
ESD@
1

Security Classification Compal Secret Data Compal Electronics, Inc.

2015/10/01 2016/10/01 Title
Issued Date Deciphered Date KBL/KBD/LED/TP/HS Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 26 of 43
 5 4 3 2 1

ESD
D6 D7 D8 D9
U3RXDN3 9 10 1 1U3RXDN3 U3RXDN2 9 10 1 1 U3RXDN2 U2DP7 3 6 U2DP6 3 6

USB Charge
I/O2 I/O4 I/O2 I/O4
U3RXDP3 8 9 2 2U3RXDP3 U3RXDP2 8 9 2 2 U3RXDP2

U3TXDN3 7 7 4 4U3TXDN3 U3TXDN2 7 7 4 4 U3TXDN2 2 5 +USB3_VCCA 2 5 +USB3_VCCA

GND VDD GND VDD
U3TXDP3 6 6 5 5U3TXDP3 U3TXDP2 6 6 5 5 U3TXDP2

3 3 3 3 1 4 U2DN7 1 4 U2DN6
USB Charge switch ESD@
8 ESD@ 8
I/O1 I/O3 I/O1 I/O3

+5VALW_CHG AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6

D
+3VL +VL +5VALW_CHG +5VALW ESD@ ESD@ D
R220 @ L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD
2 1

0_0603_5%

10K_0402_5%
R221

2
1 2 3 1
USB3.0_Port EMI

D
+5V_CHGUSB 1

10K_0402_5%
1 Q31

ME2301DC-G_SOT23-3
R2011
0_0603_5% C455

R2012
C456 4.7U_0603_6.3V6K

G
2
4.7U_0603_6.3V6K 2

Add resistor
1

1
@ APU_USB2.0
U9 80mil L12
1 12 1 4 U2DN6 W=80mils
IN OUT +VL <9> USB20_N6 1 4
<30> USB_CHG_STATUS# USB_CHG_STATUS# 9 10 USB20_P0_C
R181 2 @ 1 0_0402_5% USB_OC0#_U9 13 STATUS# DP_IN 11 USB20_N0_C R131 +USB3_VCCA
<8> USB_OC0# FAULT# DM_IN
4 2 USB20_N0 1 2 2 3 U2DP6
ILIM_SEL DM_OUT USB20_N0 <9> <9> USB20_P6 2 3
USB_CHG_EN 5 3 USB20_P0
<30>
<30>
USB_CHG_EN
USB_CHG_CTL1
USB_CHG_CTL1
USB_CHG_CTL2
6
7
EN
CTL1
DP_OUT
ILIM_LO
15
16
R182 1
R184 1
@ 2 20K_0402_1%
2 16.5K_0402_1%
USB20_P0 <9>
@
100K_0402_5%
@
MCM1012B900F06BP_4P
EMI@
USB3.0 CONN
<30> USB_CHG_CTL2 CTL2 ILIM_HI 1
<30> USB_CHG_CTL3 8 14 JUSB1
USB_CHG_CTL3 CTL3 GND

1
17 R3118 D C101 U3TXDP2 9
T-PAD SSTX+
10K_0402_5%

1 1 2 EC_ON_R 2 0.1U_0201_10V K X5R 1

<30,34> EC_ON VBUS
2

PI5USB2546ZHEX TQFN 16P @ G Q30 2 U3TXDN2 8

1 SSTX-
R2014

C176 470K_0402_1% S 2N7002K_SOT23-3

APU_USB3.0 R223 1 @EMI@ 2 0_0402_5% U2DP6 3

3
C174 7 D+
470P_0402_50V7K
0.1U_0201_10V K X5R 2 L13 EMI@ U2DN6 2 GND 10
2 1 2 2 3 U3RXDN2 U3RXDP2 6 D- GND 11
<34> 5V_PGD <9> USB30_MRX_DTX_N2
1

2 3 4 SSRX+ GND 12
R183 U3RXDN2 5 GND GND 13
0_0402_5% @ 1 4 U3RXDP2 SSRX- GND
1 <9> USB30_MRX_DTX_P2 1 4 ACON_TARBA-9U1393
C2145 MCF12102G900-T_4P ME@
0.1U_0201_10V K X5R DC231508280
2 R224 1 @EMI@ 2 0_0402_5%
C C

R225 1 @EMI@ 2 0_0402_5%

EMI C168
0.1U_0201_10V K X5R
1 2U3TXDN2_L 2
L15 EMI@
3 U3TXDN2
<9> USB30_MTX_C_DRX_N2 2 3
C169
MCM1012B900F06BP_4P 0.1U_0201_10V K X5R
USB20_P0_C 2 3 USB20_P0_R 1 2U3TXDP2_L 1 4 U3TXDP2
2 3 <9> USB30_MTX_C_DRX_P2 1 4
MCF12102G900-T_4P
USB20_N0_C 1 4 USB20_N0_R
1 4 R226 1 @EMI@ 2 0_0402_5%
L19
EMI@

IO CONN APU_USB2.0
+3VL +3VS +5V_CHGUSB L16
W=80mils
1 4 U2DN7
<9> USB20_N7 1 4 +USB3_VCCA

2 3 U2DP7 Layout JUSB2 close end user

W=100mils <9> USB20_P7 2 3
JIO1 MCM1012B900F06BP_4P
1 EMI@ JUSB2
2 1 U3TXDP3 9
3 2 1 SSTX+
4 3 R231 1 @EMI@ 2 0_0402_5% U3TXDN3 8 VBUS
5 4 U2DP7 3 SSTX-
6 5 APU_USB3.0 7 D+
7 6 L17 EMI@ U2DN7 2 GND 10
8 7 2 3 U3RXDN3 U3RXDP3 6 D- GND 11
BATT LED <30> BATT_LOW_LED#
9 8 <9> USB30_MRX_DTX_N3 2 3 4 SSRX+ GND 12
B <30> BATT_CHG_LED# 9 GND GND 13 B
10 U3RXDN3 5
11 10 1 4 U3RXDP3 SSRX- GND
<5> PCIE_DTX_C_ARX_N0 11 <9> USB30_MRX_DTX_P3 1 4
12 ACON_TARBA-9U1393
<5> PCIE_DTX_C_ARX_P0 12
13 MCF12102G900-T_4P ME@
14 13 DC231508280
<9> CLK_PCIE_CR# 14
<9> CLK_PCIE_CR
15 R232 1 @EMI@ 2 0_0402_5%
16 15
Card Reader 17 16
<5> PCIE_ATX_C_DRX_N0 17
<5> PCIE_ATX_C_DRX_P0
18 R233 1 @EMI@ 2 0_0402_5%
19 18 C172
<8,13,24,28> APU_PCIE_RST# 19
20 0.1U_0201_10V K X5R L18 EMI@
<8> CR_CLKREQ# 20
USB20_N0_R 21 1 2 U3TXDN3_L 2 3 U3TXDN3
21 <9> USB30_MTX_C_DRX_N3 2 3
USB2 For Charge USB20_P0_R 22 C173
23 22 0.1U_0201_10V K X5R
<30> NOVO# 23
24 1 2 U3TXDP3_L 1 4 U3TXDP3
<22> HGNDB 24 <9> USB30_MTX_C_DRX_P3 1 4
25
40mil 26 25 MCF12102G900-T_4P
<22> HGNDA 26
27
28 27 R234 1 @EMI@ 2 0_0402_5%
<22> HPOUT_L 28
MIC/HP 29 Place TX AC coupling Cap (C168,169~171& 173). Close to connector
30 29
31 30 33
<22> HPOUT_R 31 GND 34
32
<22> PLUG_IN 32 GND
ACES_51547-03201-P01 +USB3_VCCA
SP01001PC00 2A/Active Low
+5VALW
ME@ W=80mils U10 W=80mils
1
AGND 5 OUT
IN 2 R185
USB_EN# 4 GND 0_0402_5%
<30> USB_EN# EN 3 USB_OC1#_U10 1 @ 2
OCB USB_OC1# <8>
1
C196 SY6288D20AAC_SOT23-5
0.1U_0201_10V K X5R 1
A
2 1 A
C178 + @
220U_6.3V_M C177
SF000006R00 470P_0402_50V7K
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2015/10/01 2016/10/01 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB2 / USB3 / FP / IO Board
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 27 of 43
5 4 3 2 1
 5 4 3 2 1

+3VALW +3V_LAN

RL18 1 2 0_0603_5%

60mil W=60mil +LAN_VDD

W=60mils
+LAN_SROUT1.05 RL11 1 2 0_0603_5%
2
R-short
CL1 1
1U_0402_6.3V6K
1 CL15
0.1U_0201_10V K X5R
2
D D

LL1, CL16, and CL17 close to Pin24

( Should be place within 200 mils )

+3VS
RJ-45 CONN.
Rising time (10%~90%) 0.5ms => +3V_LAN <=100ms W=40mils +LAN_VDD JLAN2

1
+3V_LAN RL1
1 2 +LAN_VDDREG RL8 12
+3V_LAN 1K_0402_5% RJ45_TX3- 8 GND
W=60mils

4.7U_0603_6.3V6K

0.1U_0201_10V K X5R
0_0603_5% PR4- 11
1 1

1U_0402_6.3V6K
GND

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
CL9 CL10 1 1 1 1 1 RJ45_TX3+ 7

2
PR4+

@
@ CL4 CL5 CL6 CL7 CL8 ISOLATE#
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 RJ45_RX1- 6
PR2-
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R

@ @ 2 2
CL2 CL3 CL20 CL21 2 2 2 2 2 RJ45_TX2- 5
RL10 PR3-
2 2 2 2 15K_0402_5% RJ45_TX2+ 4
PR3+
RJ45_RX1+ 3
PR2+
Close to Pin23 RJ45_TX0- 2
Pin3 Pin8 Pin22 Pin30 Pin22 PR1- 10
Pin20 RJ45_TX0+ 1 GND
PR1+ 9
GND
CL2 close to Pin 11, only 8107E LDO mode unpop PS_601012-008041
CL3 close to Pin 32
ME@
C DC234007L00 LANGAN C

+LAN_VDD +LAN_VDD
UL2 @ Close to Pin17 Pin18
LAN_MDIP0 1 17 PCIE_DTX_ARX_P1 CL11 1 2 0.1U_0201_10V K X5R
MDIP0 HSOP PCIE_DTX_C_ARX_P1 <5>
LAN_MDIN0 2 18 PCIE_DTX_ARX_N1 CL12 1 2 0.1U_0201_10V K X5R
MDIN0 HSON PCIE_DTX_C_ARX_N1 <5>
3 19
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE# APU_PCIE_RST# <8,13,24,27>
LAN_MDIN1 5 MDIP1 ISOLATEB 21
MDIN1 LANWAKEB PCIE_WAKE# <24>
LAN_MDIP2 6 22
LAN_MDIN2 7 MDIP2 DVDD10 23 +LAN_VDDREG
8 MDIN2 VDDREG 24 +LAN_SROUT1.05 +3V_LAN
LAN_MDIP3 9 AVDD10 REGOUT 25 LED2 TPL1
LAN_MDIN3 10 MDIP3 LED2 26 LED1_GPIO 1 @ 2
11 MDIN3 LED1/GPO 27 LED0 RL17 10K_0402_5%
+3V_LAN AVDD33 LED0
12 28 XTLO TPL2
EMI <8> LAN_CLKREQ#
<5> PCIE_ATX_C_DRX_P1
<5> PCIE_ATX_C_DRX_N1
13
14
15
CLKREQB
HSIP
HSIN
CKXTAL1
CKXTAL2
AVDD10
29
30
31
XTLI

2.49K_0402_1% 2 1 RL9
reserved GPIO pin
RL20 1 2 0_0402_5% <9> CLK_PCIE_LAN 16 REFCLK_P RSET 32
<9> CLK_PCIE_LAN# REFCLK_N AVDD33 +3V_LAN
33
RL21 1 2 0_0402_5% GND

RTL8111H-CG_QFN32_4X4

LANGAN

@EMI@ CL32 1 2 0.1U_0201_10V K X5R

B B

@EMI@ CL33 1 2 0.1U_0201_10V K X5R

UL2
SA000080P00
S IC RTL8111H-CG QFN 32P E-LAN CTRL
LANGAN 8111H@

+V_DAC 1
TL1
24 MCT
EMI
CL13
ESD EMI LAN_MDIP3 2
TCT1

TD1+
MCT1

MX1+
23 RJ45_TX3+ 1
RL19
2
CL19
1 2

1 2 XTLO SC300001G00 LAN_MDIN3 3 22 RJ45_TX3- 75_0805_5% 10P_0603_50V

AZC099-04S.R7G_SOT23-6 EMI@ CL18 TD1- MX1- EMI@ EMI@
10P_0402_50V8J LAN_MDIN3 3 6 LAN_MDIP2 1 2 +V_DAC 4 21
I/O2 I/O4 TCT2 MCT2 LANGAN
0.01U_0402_16V7K LAN_MDIP2 5 20 RJ45_TX2+
TD2 MX2+
1

YL1 2 5 LAN_MDIN2 6 19 RJ45_TX2-

OSC

NC

25MHZ_10PF_7V25000014 GND VDD TD2- MX2-

+V_DAC 7 18 2 1
SJ10000E800 TCT3 MCT3
OSC

LAN_MDIP3 1 4 LAN_MDIN2 LAN_MDIP1 8 17 RJ45_RX1+ DL3

NC

I/O1 I/O3 TD3+ MX3+ BS4200N-C-LV_SMB-F2

DL1 LAN_MDIN1 9 16 RJ45_RX1-
DL1 Only For GIGA EMI@
2

@ESD@ TD3- MX3-

CL14
+V_DAC 10 15
1

10P_0402_50V8J
2 XTLI
SC300001G00
AZC099-04S.R7G_SOT23-6
LAN_MDIP0 11
TCT4

TD4+
MCT4

MX4+
14 RJ45_TX0+ EMI
LAN_MDIN1 3 6 LAN_MDIP0 LAN_MDIN0 12 13 RJ45_TX0-
I/O2 I/O4 TD4- MX4-

NS892407
2 5 TL1 GIGA@
GND VDD S0 X'FORM_ HH-065 10/100
A 100@ A

LAN_MDIP1 1 4 LAN_MDIN0 FOR 10/100 data transferring 2013/08/27

I/O1 I/O3
DL2
@ESD@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_RTL8111H / RTL8107E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 28 of 43
5 4 3 2 1
 A B C D E

+5VALW TO +5VS VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+3VALW TO +3VS
Load switch
+5VALW VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
U13 J5 @
+5VS
RF for YOGA RF
1 14 +5VS_LS 1 2
2 VIN1 VOUT1 13
VIN1 VOUT1 C10 180P_0402_50V8J PAD-OPEN 4x4m +3VS +5VALW
1

2
@ C11 SUSP# 3 12 1 2
ON1 CT1 C14

1U_0402_6.3V6K
+VL 4 11 0.1U_0201_10V6K

1
2 VBIAS GND C9 330P_0402_50V7K +3VS
+3VALW

22P_0402_50V8J

22P_0402_50V8J

0.1U_0201_10V6K

0.1U_0201_10V6K

22P_0402_50V8J
SUSP# 5 10 1 2 1 1 1
ON2 CT2

1
J4 @ C1265 C1266 C1267 C1268 C1269
6 9 +3VS_LS 1 2
VIN2 VOUT2

1U_0402_6.3V6K
7 8 RFY@ RFY@ RFY@ RFY@ RF@

2
1 VIN2 VOUT2 PAD-OPEN 4x4m 2 2 2 1

2
1 C12 15
@ GPAD C13
EM5209VF DFN 14P 0.1U_0201_10V6K

1
2

+1.8VALW VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+1.8VS
+1.8VALW TO +1.8VS J18V @
1U_0402_6.3V6K

U18
1 14 +1.8VS_LS 1 2
+0.95VALW TO +0.95VS @
1 C24 2 VIN1
VIN1
VOUT1
VOUT1
13
C21 180P_0402_50V8J PAD-OPEN 4x4m

2
Load switch 2
SUSP# 3

4
ON1 CT1
12

11
1
@
2
C26
+VL 0.1U_0201_10V6K

1
VBIAS GND C15 330P_0402_50V7K
R1643 1 2 0_0402_5% 5 10 1 2
<30> PWR_095VS_EN ON2 CT2 +0.95VS
@
6 9 J95V @
SUSP# R1644 1 @ 2 0_0402_5% +0.95VALW 7 VIN2 VOUT2 8 +0.95VS_LS 1 2
VIN2 VOUT2
15 PAD-OPEN 4x4m
GPAD

2
EM5209VF DFN 14P C25
1 0.1U_0201_10V6K

1
@ C22
1U_0402_6.3V6K

2 2
2

+1.2V +0.6VS

1
R1627 R1629
470_0603_5% 470_0603_5%
@ @

1 2

1 2
only for Beema D D
2 SYSON# 2 SUSP
G Q25 G Q21
+1.5VS discharge circuit only for Beema S 2N7002H_SOT23-3 S 2N7002H_SOT23-3

3
@ @
only 1.5VS from PWR +3VL

2
+1.8VS R1636
@ 100K_0402_5%
+5VALW
1
SUSP

1
1

Q101 DTC124EKAT146_SC59-3 @

1
R1638
R1461 @ 100K_0402_5%

OUT
@ 220_0603_5%

2
3 3
SYSON#
2

SUSP# 2
<30,35> SUSP# IN

1
GND
1

OUT
2 SUSP
G Q23 Q24
3

S 2N7002H_SOT23-3 SYSON 2 DTC124EKAT146_SC59-3

<30,35> SYSON
3

@ IN @

GND
1
@ R239

3
100K_0402_5%

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/01 Deciphered Date 2016/10/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 29 of 43
A B C D E
 5 4 3 2 1
+3VL
+3VALW_EC +1.8VALW
+3VALW_EC
L20 KBL_SELECT

1
FBM-11-160808-601-T_0603 +3VL Function KBL_ID
+3VS

R311 0_0402_5%

R310 0_0402_5%
1 2
+EC_VCCA

C179
1 1 1 @ KBL 1
C185
C184 @ R189 1 2 0_0603_5% @ NO KBL 0

2
2
0.1U_0201_10V6K 1000P_0402_50V7K 100P_0402_50V8J EC_SMB_CK3 R3119 1 @ 2 2.2K_0402_5%
1 2 2 ECAGND 2 +3VALW_EC 2
L21 1 1 1 1 EC_SMB_DA3 R3120 1 @ 2 2.2K_0402_5%
+3VS +3VALW

0.1U_0201_10V6K
C180

0.1U_0201_10V6K
C181

1000P_0402_50V7K
C182

1000P_0402_50V7K
C183
FBM-11-160808-601-T_0603
EC_SMB_CK4 R3121 1 YOGA@ 2 2.2K_0402_5%
D ECAGND +EC_VCCA @ D
2 2 @ 2 @ 2 EC_SMB_DA4 R3122 1 YOGA@ 2 2.2K_0402_5% R2002 1 2 1K_0402_1%

111
125
22
33
96

67
9
@
1 2 NOVO# KB_BL_PWM R2000 1 2 1K_0402_1%

VCC1/LPC
VCC2
VCC3
VCC4
VSBY
VCC5/SPI

AVCC
+3VALW_EC
R208 100K_0402_5% R2001 1 2 10K_0402_5%

NOKBL@
NOVO# 1 21 VGATE
RF <27> NOVO#
<8> KB_RST#
<9> SERIRQ
KB_RST#
SERIRQ
LPC_FRAME#
2
3
4
GPIO85/GA20
GPIO86/KBRST#
SERIRQ/GPIOF0 PWM Output
GPIO15/A_PWM
GPIO21/B_PWM
GPIO32/D_PWM
23
26
27
BEEP#
EC_FAN_PWM1
GATEA20
VGATE <38>
BEEP# <22>
EC_FAN_PWM1 <25>
<8,9> LPC_FRAME# 5 LFRAME#/GPIOF6 GPIO45/E_PWM GATEA20 <8>
RF@ RF@ LPC_AD3
<9> LPC_AD3 LAD3/GPIOF4 +3VS
2 1 2 1 LPC_AD2 7
<9> LPC_AD2 8 LAD2/GPIOF3 63
C1263 R1560 LPC_AD1 VCIN1_BATT_TEMP
<9> LPC_AD1 10 LAD1/GPIOF2 GPIO90/AD0 64 VCIN1_BATT_TEMP <32,33>
22P_0402_50V8J 10_0402_5% LPC_AD0 VCIN1_BATT_DROP
<9> LPC_AD0 LAD0/GPIOF1 LPC & MISC GPIO91/AD1 65 VCIN1_BATT_DROP <34>
GPIO92/AD2 ADP_I <33>
CLK_LPC_EC 12 AD Input 66
<8,9> CLK_LPC_EC LCLK/GPIOF5 GPIO93/AD3 DCHG_I <33>
LPC_RST# 13 75
<8> LPC_RST# LRESET#/GPIOF7 GPIO05/AD4
+3VALW_EC R192 2 1 47K_0402_5% EC_RST# 37 76 VRAM_TEMP TP_CLK R260 1 2 4.7K_0402_5%
20 ECRST# GPIO04/AD5 VRAM_TEMP <25>
EC_SCI#
<8> EC_SCI# 38 GPIO54/ECSCI#
<8> SENSOR_EC_INT GPIO11/CLKRUN# 68
GPIO94/DA0 TAB_SW# <20>
1

C187 70 TS_DISABLE# TP_DATA R261 1 2 4.7K_0402_5%

GPIO95/DA1 71 TS_DISABLE# <20>
DA Output GPIO96/DA2 DGPU_PWR_EN <8,15,40>
0.1U_0201_10V6K KSI0 55 72 USB_EN#
USB_EN# <27>
2

KSI1 56 KBSIN0/GPIOA0 GPIO97/DA3

KSI2 57 KBSIN1/GPIOA1 +5VALW
KSI3 58 KBSIN2/GPIOA2 83
59 KBSIN3/GPIOA3 GPIO31/SCL3/PSCLK1 84 EC_SMB_CK3 <8>
C KSI4 HID over I2C C
60 KBSIN4/GPIOA4/N2TCK GPIO23/SDA3/PSDAT1 85 EC_SMB_DA3 <8>
KSI5
61 KBSIN5/GPIOA5/N2TMS GPIO47/SCL4/PSCLK2 86 EC_SMB_CK4 <20,23> Sensor Slave bus
KSI6 PS2 Interface
62 KBSIN6/GPIOA6 GPIO53/SDA4/PSDAT2 87 EC_SMB_DA4 <20,23>
KSI7 TP_CLK R194
KBSIN7/GPIOA7 GPIO50/PSCLK3 TP_CLK <26>
KSO0 39 88 TP_DATA USB_EN# 1 2
KSO[0..17] 40 KBSOUT0/GPIOB0/SOUT_CR/JENK# GPIO52/PSDAT3 TP_DATA <26>
KSO1
KSO[0..17] <26> 41 KBSOUT1/GPIOB1/TEST#
KSO2 10K_0402_5%
KSI[0..7] KSO3 42 KBSOUT2/GP(I)OB2/TRIST# 97 ENBKL
KSI[0..7] <26> 43 KBSOUT3/GP(I)OB3/XORTR# GPIO02 98 ENBKL <7,20> +3VS
KSO4
KBSOUT4/GPIOB4/SDP_VIS# GPIO75 EC_ENVDD <20>
KSO5 44 GPIO 99 PWR_095VS_EN
45 KBSOUT5/GPIOB5/TDO GPIO76 109 PWR_095VS_EN <29>
KSO6 VCIN0_PH1 VCIN0_PH1 <32>
KSO7 46 KBSOUT6/GPIOB6/RDY# VCIN1/GPIO16 EC_GPIO72 R216 1 2 10K_0402_5%
KBSOUT7/GPIOB7 Int. K/B
KSO8 47
+3VALW_EC KSO9 48 KBSOUT8/GPIOC0 Matrix 119 EC_FAN_SPEED1 R214 1 2 10K_0402_5%
KSO10 49 KBSOUT9/GPIOC1 F_SDI&F_SDIO1/GPO80 120
KSO11 50 KBSOUT10&P80_CLK/GPIOC2 F_SDIO&F_SDIO0/GPIOC6 126 +3VALW
KSO12 51 KBSOUT11&P80_DAT/GPIOC3 F_CLK/GPIOC4 128
KBSOUT12/GPIO64/TCK SPI Flash ROM F_CS0#/GPIOC5
R201 1 2 2.2K_0402_5% EC_SMB_CK1 KSO13 52
KSO14 53 KBSOUT13/GPIO63/TMS PBTN_OUT# R215 1 2 10K_0402_5%
R202 1 2 2.2K_0402_5% EC_SMB_DA1 KSO15 54 KBSOUT14/GPIO62/TDI 73
KBSOUT15/GPIO61/XOR_OUT GPIO03/AD6/CIRRXM DDR_TEMP <25>
KSO16 81 74 EC_MUTE# R198 1 @ 2 10K_0402_5%
82 GPIO60/KBSOUT16 GPIO07/AD7/CIRTX1 89 CMOS_ON# <20>
KSO17 EC_MUTE#
GPIO57/KBSOUT17 GPIO67/N2TMS EC_MUTE# <22>
90 BATT_CHG_LED# EC_PCIE_WAKE# R212 1 2 10K_0402_5%
GPIO51/N2TCK 91 BATT_CHG_LED# <27>
CAPS_LED#
GPIO36 CAPS_LED# <26>
EC_SMB_CK1 77 GPIO 92 PWR_LED# LID_SW# R344 1 2 47K_0402_5%
<32,33> EC_SMB_CK1 78 GPIO17/SCL1/N2TCK GPIO40/F_PWM 93 PWR_LED# <26>
EC_SMB_DA1 BATT_LOW_LED# @
<32,33> EC_SMB_DA1 79 GPIO22/SDA1/N2TMS GPIO35 95 BATT_LOW_LED# <27>
EC_SMB_CK2 SYSON TAB_SW# R3117 1 2 47K_0402_5%
<7,14,25> EC_SMB_CK2 80 GPIO73/SCL2 GPIO06/IOX_DOUT 121 SYSON <29,35>
EC_SMB_DA2 SM Bus @
<7,14,25> EC_SMB_DA2 GPIO74/SDA2 GPIO81/F_WP# 127
B GPIO84/IOX_SCLK EC_FAN_REVERSE<25> B
EC_RSMRST# <8>
6 100 EC_RSMRST#
<27> USB_CHG_STATUS# 14 GPIO24 GPIO26/RSMRST# 101 GPU_GPIO5_EC R1568 1 @ 2 0_0402_5%

ESD <27> USB_CHG_CTL1

<10> EC_CLEAR_CMOS#
<27> USB_CHG_CTL3
15
16
17
GPIO10/LPCPD#
GPIO65/SMI#
GPIO34/1_WIRE/CIRRXL
GPIO20/TA2/IOX_DIO
VC_IN2/GPIO72
VC_OUT2/GPIO37
102
103
104
EC_GPIO72 <26>
VCOUT1_PROCHOT# <33>
GPU_GPIO5_VGA <14>
PWR_095VS_EN
R207
1 2
100K_0402_5%
<27> USB_CHG_EN 18 GPIO01/TB2 VC_OUT1/GPIO25 105 VCOUT0_MAIN_PWR_ON <34>
GPIO BKOFF#
<27> USB_CHG_CTL2 19 GPIO43 GPIO77 106 BKOFF# <20> 1 2
BATT_LOW_LED# GPIO PM_SLP_S3# VCIN1_BATT_TEMP
<24> EC_PCIE_WAKE# 25 GPIO42/CIRTX2 GPIO44 107 PM_SLP_S3# <8>
KB_BL_PWM PWR_095VALW_EN <35,36,37,38> C189 100P_0402_50V8J
<26> KB_BL_PWM GPIO13/C_PWM GPIO12 PWR_095VALW_EN
<25> EC_FAN_SPEED1 EC_FAN_SPEED1 28 108 VR_ON VR_ON <38> VCIN1_AC_IN 1 2
BATT_CHG_LED# 29 GPIO56/TA1 GPIO30/F_WP# C190 100P_0402_50V8J
<7,20> SOC_ENVDD 30 GPIO14/TB1
EC_TX R1569 1 2 0_0402_5% GPU_GPIO5_VGA 1 @ 2
<24,26> EC_TX GPIO83/SOUT_CR/P80_DATA
100P_0402_50V8J

100P_0402_50V8J

1 1 EC_RX 31 110 VCIN1_AC_IN R203 4.7K_0402_5%

<24,26> EC_RX 32 GPIO87/SIN_CR/P80_CLK AC_IN/GPIO41/F_WP# 112 VCIN1_AC_IN <33>
C199 C200 SYS_PWRGD_EC EC_ON
<8> SYS_PWRGD_EC GPIO27/RSMRST# EC_ON/GPIO71 EC_ON <27,34>
34 GPIO 114 ON/OFF# PWR_095VALW_EN R213 1 2 10K_0402_5%
36 GPIO66/G_PWM ON_OFFBTN#/GPIO70 115 ON/OFF# <26>
@ESD@ @ESD@ NUM_LED# LID_SW#
2 2 <26> NUM_LED# GPIO33/H_PWM GPO82/IOX_LDSH/LIDIN 116 LID_SW# <26>
SUSP#
GPIO46/CIRRXM/PLCIN 117 SUSP# <29,35>
NUVOTON_VTT
VTT 118
PECI PECI

1
PBTN_OUT# 122 VCOUT1_PROCHOT# R204 1 2 0_0402_5%
<8> PBTN_OUT# 123 GPIO00/EXTCLK 124
<8,33> PM_SLP_S5# PM_SLP_S5# +V18R
GPIO55/CLKOUT/IOX_DIO VCORF

C823 4.7U_0603_6.3V6K
1 R1639 R205 1 2 0_0402_5% H_PROCHOT# <7>
<38> PROCHOT#

1
AGND
GND2

GND4
GND5
GND1

GND3

100K_0402_5%
1 1

2
R1567 @ESD@ @
RF ESD ESD U11 2 0_0402_5% C121 C191
24

94
113

69
11

35

20mil 100P_0402_50V8J 47P_0402_50V8J

2

NPCE388NA0DX_LQFP128_14X14 2 2
A A
EC_TX EC_RSMRST# SYS_PWRGD_EC SYSON

R-short
ECAGND
100P_0402_50V8J
22P_0402_50V8J

100P_0402_50V8J

33P_0402_50V8J

1 1 1
1

C1264 C198 C197 C193

Security Classification Compal Secret Data Compal Electronics, Inc.
@RF@ ESD@ ESD@ @ESD@ 2015/10/01 2016/10/01 Title
Issued Date Deciphered Date
2

2 2 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC-Nuvoton 388N
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-D541P
Date: Thursday, December 17, 2015 Sheet 30 of 43
5 4 3 2 1
 5 4 3 2 1

ACES_50278-00401-001 EMI@ PL101

6
G2 5 PF101
HCB2012KF-121T50_0805
1 2
+19V_VIN
G1 4 APDIN 7A_32VDC_0437007.WRML
4 3 1 2 +19V_APDIN
3 2 EMI@ PL102
2 1 HCB2012KF-121T50_0805
1

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
1 2
@ JDCIN1

1
EMI@ PC101

EMI@ PC102

EMI@ PC103

EMI@ PC104
2

2
D D

C C
2

PR107
+CHGRTC
45.3K_0603_1%

PR108
1.5K_0603_5%
1

1 2
PD101
+3VL
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT_3V 1
3 PR109
1K_0603_5% JRTC1 @
1 2 1
2 1
3 2
4 GND
GND

ACES_50271-0020N-001

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SKL
Date: Thursday, December 17, 2015 Sheet 31 of 43
5 4 3 2 1
 5 4 3 2 1

EMI@ PL201
VMB2 +8.4V_VMB HCB2012KF-121T50_0805
PF201 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
1 1 2
1 2 +12.6V_BATT+
EMI@ PL202
2 3 EC_SMCA HCB2012KF-121T50_0805
3 4 EC_SMDA 1 2
4 5
5 6
6

1
7
7

1
100_0402_1%

100_0402_1%
8
8 9 PC201 EMI@ PC202 EMI@
D GND 10 1000P_0402_50V7K 0.01U_0402_25V7K D

2
GND

PR201

PR202
11

2
GND 12
GND
SUYIN_125022HB008M200ZL
CONN@

EC_SMB_CK1 <30,33>

EC_SMB_DA1 <30,33>
1 2
+3VL
PR203
1 2 200K_0402_1% +3VALW
PR204
@ 200K_0402_1%
1 2
PR205
VCIN1_BATT_TEMP <30,33> PH201 under CPU botten side :
10K_0402_5%
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

+EC_VCCA

16.5K_0402_1%
1
PR206
C C

2
<30> VCIN0_PH1

1
PH201
100K +-1% 0402 B25/50 4250K

2
ECAGND

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 32 of 43
5 4 3 2 1
 A B C D

0x3CH <BIT9> PSYS current gain **Design Notes**

Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 10mΩ and Rs2 = 10mΩ For 45W/65W /90W system, 2S/3S/4S battery
BIT0 = 1.14uA/W Maximum Charging current 3.5A
BIT1 = 0.285uA/W
========================================================= Maximum Battery discharge power 55W
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ #Register Setting
BIT0 = 2.28uA/W 1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function
BIT1 = 0.57uA/W 2. Disable turbo when AC only
#Circuit Design
1. ACLIM and CCLIM are devider voltage control.
Ipsys = KPSYS x ( VADP x IADP + VBAT x IBAT ) 2. Use 7X7 choke and 3X3 H/L side MOSFET
R_Psys = 1.2V / Ipsys Protection for reverse input Charge current 3A
KPSYS = 1.14uA/W Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)
adapter wattage = 45W Power density : 0.61 (23X16)
Battery wattage = 40Wh #Protect function
Ipsys = 1.14 x (45+40) = 96.9uA 1. ACOVP : VCC voltage > 24V
1
R_Psys = 1.2V / 96.9uA = 12.3K-ohm. Vgs = 20V 1

===================================== Vds = 60V 2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).
adapter wattage = 65W Id = 250mA 3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
4. CHGOCP : based on charge current setting

1
Battery wattage = 40Wh D
Ipsys = 1.14 x (65+40) = 119.7uA 2 PQ301 5. BATOVP : 4.6V/Cell
R_Psys = 1.2V / 96.9uA = 10K-ohm. G L2N7002WT1G_SC70-3 6. BATLOWV : No.
S max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W 7. TSHUT : 150C

3
Rds(on) = 15.8mohm max CSR rating: 1W
1 2 1 2
Vgs = 20V VCSIP-VCSIN spec < 81mV
PR301 PR302 Vds = 30V
1M_0402_1% 3M_0402_5% ID = 10.5A (Ta=70C) B+
PQ302 +19V_P1 PQ303
Need check the SOA for inrush MDU1512RH_POWERDFN56-8-5 AON7506_DFN33-8-5 PR303
1 1 +19V_P2 0.01_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30% +19VB_CHG
2 2 EMI@ PL301
5 3 3 5 1 4 1 2
+19V_VIN

EMI@

EMI@
2 3 Module model information

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V7K
4

1
PC203

PC204
CSIN_CHG_R
CSIP_CHG_R
ISL95520_Hybrid_Boost_V2.mdd

PC205

PC206
2

2
1
0_0402_5%
Co-lay jump and ISN choke.

PR305
0_0402_5%
PR304
1

PR306 @

2
392K_0402_1% ASGATE_CHG_R @

2
PC207
2

1 2 PQ304

4.02K_0402_1%

4.02K_0402_1%
2 2
AON7506_DFN33-8-5
1
0.1U_0402_25V6

1
2
5 3

PR309
PR729 and PR732 are ACDET setting base on your project to set. 100_0402_1%

4
PR307

PR308
1 2 +12.6V_BATT+ Rds(on) = 32mohm max
Vgs = 20V
0.22U_0402_16V7K Vds = 30V
1

CMSRC_CHG PC209 ID = 8A (Ta=70C) @ PC210

2200P_0402_50V7K
49.9K_0402_1%

1
PR310

PC208

1
ASGATE_CHG 1 2
2

BGATE_CHG
2

OPCN_CHG 2
0.1U_0402_25V7K

CSIN_CHG
CSIP_CHG

OPCP_CHG

VBAT_CHG
Rds(on) = 32mohm max
1 VDD_CHG

Vgs = 20V
Vds = 30V

5
PU301
ID = 8A (Ta=70C) PQ305
100K_0402_1%

support Turbo boost : 2200P Support max charge 3.5A

32

31

30

29

28

27

26

25
no support Turbo boost : 0.1u ISL95521HRZ-T QFN 32P CHARGER
AON7408L_DFN8-5 Power loss: 0.245W
PR311

7X7X3

CSIN

CMSRC

OPCN

VBAT
CSIP

ASGATE

QPCP

BGATE
PR312 PC211 4 CSR rating: 1W
2.2_0603_5% 0.22U_0603_25V7K
Isat: 6.5A VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2 DCR: 28mohm
2

ACIN BOOT PR315

PL302
2 23 UG_CHG 0.01_1206_1%

3
2
1
<30> VCIN1_AC_IN ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M +12.6V_BATT+
1

1 2 0_0402_5% 3 22 LX_CHG 1 2 +17.4V_BATT_CHG 1 4

158K_0402_1%

PR313
<30,32> EC_SMB_DA1 SDA PHASE
PR314

PR320 1 2 0_0402_5% 4 21 LG_CHG 2 3

680P_0603_50V7K 4.7_1206_5%
<30,32> EC_SMB_CK1 SCL LGATE

EMI@ PR317

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
5
3
5 20 VDDP_CHG PQ306 3
2

PROCHOT# VDDP

AON7752_DFN3X3EP8-5

1
19

PC212

PC213

PC214
PR318 1 2 0_0402_5% AMON_ISL95520 6 VDD_CHG 1 2
<30> ADP_I AMON VDD

2
PR321 1 2 0_0402_5% BMON_ISL95520 7 18 PR319 4.7_0402_5%
<30>

2
DCHG_I BMON DCIN

1
4
8 17

BATGONE
PC215 PC216
PMON_SKYLAKE PSYS NTC

EMI@ PC217
1U_0402_16V6K 1U_0402_16V6K

2
CCLIM

ACLIM
COMP
PROG
AGND

CSON

CSOP
FSET PR323

1
PC219 100K_0402_1%

2
3
2
1
1

2
0_0402_5%

PC218 1000P_0402_25V8J
PR322

PD102
33

10

11

12

13

14

15

16
1000P_0402_25V8J Follow adapter and PR324 10_1206_5% 3
+19V_VIN
2

battery wattage in 1 2 1

3
Close to Vsys current source. @ 2 @ PQ307
1

2
1

EC.
FSET_CHG

PC220
VF = 0.38V

1U_0603_25V6
Base on CPU Core VR design.
PR326 LRB715FT1G_SOT323-3 LMUN5113T1G_SOT323-3
The resistor is pop on CPU VR schematic.
1

0_0402_5% 2

1
@ PR325 @ PR316 0_0603_5%
10K_0402_1% 1 2
+12.6V_BATT+
2

1
VDD=5V VDD_CHG
2

1 2
BA

1
CCLIM_CHG
2
200K_0402_1%

@ PR339 0_0603_5% <8,30>

1

VCOUT1_PROCHOT# ACLIM_CHG PM_SLP_S5#

A31 connect to BA
PR328

<30> PR329
200K_0402_1% PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R Other team connect to batt conn @ PQ308

BA
3
COMP_CHG PR331 2_0402_5% LTC015EUBFS8TL_UMT3F
2

1
499_0402_1%

@ PR332 Fs=729KHZ ~ +/- 15% PC221

38.3K_0402_1%

BA
1

2 PR334 1

76.8K_0402_1% 0.1U_0402_25V6

2
1 2
PR333
1

CSON_CHG 1 2
182K_0402_1%

CSON_CHG_R
560P_0402_50V7K
1
PR335

PC222

@ PQ310 @ PR336 0_0402_5%

53.6K_0402_1%

2
1

D
4
Change net to PM_SLP_S5# for AMD platform 4
2
1

2
VCIN1_AC_IN PR338
2
PR337

G For A31 only.

0.022U_0402_25V7K

154K_0402_1%
1

S VCIN1_BATT_TEMP <30,32> Turn off Charger IC on battery only.

3

PC223

L2N7002WT1G_SC70-3 BATGONE(BATT_TEMP) Depend on customer design for

2

logic high: above 2.4V system power consumption.

2

(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ). Hybrid boost power mode logic low: under 0.8V
2

CC_LIM = VccLIM / 64 x Rs2 U45W@ Cell = 3s

============================================================= PC224
PR337 U65W@ 10P_0402_25V8J
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ).
1

76.8k_0402_1%
CC_LIM = VccLIM / 32 x Rs2
=============================================================
Security Classification Compal Secret Data Compal Electronics, Inc.
2015/07/27 2016/07/27 Title
AC_LIM = Vac_LIM / 32 x Rs1 Adapter current limimed:
For U22(45W)_adp: Battery current limimed by CCLIm ~ 3.89A.
Issued Date Deciphered Date
PWR_CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PR337=53.6k Adapter current limimed by ACLIm ~ 4.33A. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
For U23e(65W) and DIS_adp: (PR779 and PQ741 are for change ACLIm when AC in) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00(0.1)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PR337=76.8k Date: Thursday, December 17, 2015 Sheet 33 of 43
A B C D
 A B C D E

Module model information

SY8286B_V1.mdd

1 1

PU401
B+ EMI@ SY8286BRAC_QFN20_3X3 PR402
PL401
0_0603_5% PC402

2200P_0402_50V7K
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2

10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC401

EMI@ PC403
0.1U_0402_25V6
5A_Z120_25M_0805_2P 0.1U_0603_25V7K

1
PC429

PC404

BS
IN

IN

IN

IN
PL402

2
LX_3V6 20 LX_3V 1 2
@ LX LX +3VALWP

@EMI@

PR403
7 19 1.5UH_6A_20%_5X5X3_M
GND LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
680P_0603_50V7K 4.7_1206_5%

1
8 18
+3VLP GND GND

PC405

PC406

PC407

PC408
9 17
+3VLP

2
PG LDO

1 3V_SN
2
1
10 16
NC NC

1
Check pull up resistor of SPOK at HW side PC409

OUT
EN2

EN1
21

NC
4.7U_0603_6.3V6M

FF

2
PR401 GND

@EMI@

PC410
100K_0402_5%

11

12

13

14

15

2
3.3V LDO 150mA~300mA

2
Vout is 3.234V~3.366V Ipeak=4.65A
<35,36,37,38>
3V/5VALW_PG Imax=3.25A
2 ENLDO_3V5V PC411 PR404 2
1000P_0402_25V8J 1K_0402_1%
TDC=6A Iocp=10A
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2

EN :H>0.8V ; L<0.4V
EN1 and EN2 dont't be floating @ PJ401
1 2
+3VALWP 1 2 +3VALW
JUMP_43X118

Module model information @ PJP402

SY8286C_V1.mdd JUMP_43X39
1 2
+3VLP 1 2 +3VL

B+ +19VB_5V
EMI@ PR405
PL403 PC412
PR407 PU402 SY8286CRAC_QFN20_3X3 0_0603_5%
499K_0402_1% 1 2 +19VB_5V BST_5V1 2 BST_5V_R 1 2
1 2 ENLDO_3V5V
B+ 5

1
5A_Z120_25M_0805_2P
1
150K_0402_1%

0.1U_0603_25V7K

BS
IN

IN

IN

IN
1
PR408

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PC431 LX_5V 6 20 PL404

LX LX 2.2UH_7.8A_20%_7X7X3_M
1U_0402_16V6K
2

PC430

7 19 LX_5V 1 4 +5VALWP
2

GND LX
1

1
1
PC413

PC414

@EMI@ PC416
EMI@ PC415

PC432 RF@
8 18 2 3 @ @ @
GND GND

22P_0402_50V8J
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
3 @ PC417 4.7U_0603_6.3V6M 3
2

2
2

1
1

1
9 17 VCC_5V 1 2
PG VCC

PC418

PC420

PC421
PR406

PC419

PC423

PC422

PC428
4.7_1206_5%
@

@EMI@
10 16

2
2

2
2

2
PR410 NC NC
OUT

LDO
EN2

EN1

2.2K_0402_5% 21
FF

1 2 GND
<27,30> EC_ON <27>

2
@ PR411
11

12

13

14

15

5V_PGD
1

0_0402_5%
+5VLP

15V_SN
4.7U_0603_6.3V6M

1 2
<30> VCOUT0_MAIN_PWR_ON PR415 5V LDO 150mA~300mA
1

680P_0603_50V7K
PC424

100K_0402_5%
2

@EMI@

PC425
ENLDO_3V5V
2

5V_3V_EN

2
5V_3V_EN
+VL Vout is 4.998V~5.202V
1M_0402_1%

4.7U_0402_6.3V6M
1

1
PR413

PC427

EN :H>0.8V ; L<0.4V TDC=6A Ipeak=9A

PC426 PR412
1000P_0402_25V8J 1K_0402_1% Imax=6.25A
2

EN1 and EN2 dont't be floating 5V_FB 1 2 5V_FB_1 1 2

Iocp=10A
2

+19VB_5V

@ PJ403
1

1 2
PR341 +5VALWP 1 2 +5VALW
JUMP_43X118
560K_0402_5%
4 @ PJP404 4
2

JUMP_43X39
VCIN1_BATT_DROP <30> 1 2
+5VLP 1 2 +VL
1

PR342 PC327
1000P_0402_25V8J
2

105K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- 3VALW/5VALW-SY8286B&C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 34 of 43
A B C D E
 A B C D E

Pin19 need pull separate from +1.35VP. 0.675Volt +/- 5%

If you have +1.35V and +0.675V sequence question, TDC 0.7A
EMI@ PL501 you can change from +1.35VP to +1.35VS.
B+ HCB2012KF-121T50_0805 Peak Current 1A
1 2 +12.6VB_DDR PR501
2.2_0603_5%
BST_DDR_R 1 2 BST_DDR

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
+1.2VP

1
@EMI@ PC501

EMI@ PC502

PC503

PC504
UG_DDR +0.6VSP

2
1 1

5
LX_DDR

10U_0603_6.3V6M

10U_0603_6.3V6M
1

1
PC505
0.1U_0603_25V7K

PC506

PC507
16

17

18

19

20
2
PU501

2
PQ501 4

BOOT

VTT
VLDOIN
PHASE

UGATE
21
AON7408L_DFN8-5 PAD
LG_DDR 15 1
LGATE VTTGND

1
2
3
14 2
PL502 PR502 PGND VTTSNS
1UH_11A_20%_7X7X3_M 6.04K_0402_1%
1 2 1 2 CS_DDR 13 3
+1.2VP CS GND

5
PC508 RT8207PGQW_WQFN20_3X3

1
PQ502 1U_0402_10V6K
AON7506_DFN33-8-5 1 2 12 4 VTTREF_DDR
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@EMI@ PR503 PR504 VDDP VTTREF

1

4.7_1206_5% 5.1_0603_5%
PC509

PC510

PC511

PC512

PC513

PC514

4 1 2 VDD_DDR 11 5
+5VALW +1.2VP

1 2
VDD VDDQ

1
PGOOD
2

PC516
+5VALW PR505

TON
1
@EMI@ PC515 0.033U_0402_16V7K

FB
S5

S3

2
680P_0402_50V7K PC517 1 2

1
2
3
1U_0402_10V6K 5.1_0603_5%

10

6
FB_DDR
EN_DDR
TON_DDR

EN_0.6VSP
PR507
1 2 +1.2VP
PR508 470K_0402_1%
+12.6VB_DDR 1 2
6.04K_0402_1%

1
@ PR510 0_0402_1% PR509
10K_0402_1%
1 2
<29,30> SYSON

2
MOSFET: 3x3 DFN

1
@ PC518
2 H/S Rds(on): 27mohm(Typ), 34mohm(Max) 0.1U_0402_10V7K 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

2
L/S Rds(on): 19mohm(Typ), 23.5mohm(Max) PR511
Mode Level +0.675VSP VTTREF_1.35V Idsm: 11A@Ta=25C, 8.8A@Ta=70C 0_0402_5%
S5 L off off 1 2 @ PJ501
S3 L off on Choke: 7x7x3 <29,30> SUSP# +1.2VP 1 2 +1.2V
1 2
S0 H on on Rdc=6.7mohm(Typ), 7.4mohm(Max) JUMP_43X118
Note: S3 - sleep ; S5 - power off Switching Frequency:540kHz
Ipeak=8A

1
Iocp~9.6A @ PC519
OVP: 113%~120% 0.1U_0402_10V7K PJ503 @

2
VFB=0.75V, Vout=1.3545V 1 2
+0.6VSP 1 2 +0.6VS
JUMP_43X39

3 3

Module model information PR518

0_0402_5%
1 2
SY8003A_V1.mdd PWR_095VALW_EN <30,36,37,38>

@ PR512
0_0402_5%
+2.5VSP_ON 1 2
3V/5VALW_PG <34,36,37,38>
0.1U_0402_16V7K

1
PC520
1

PR514
@ 1M_0402_5%
Note:Iload(max)=2.5A
2

PU502
2

9 @
PGND PJ504
1 8
FB SGND 1 2
PJ505 @ 2 7 +2.5VP 1 2 +2.5V
PG EN PL503
+3VALW 1 2 3 6 LX_2.5V 1 2 JUMP_43X79
1 2 IN LX 1UH_2.8A_30%_4X4X2_F +2.5VP
1

4 5
68P_0402_50V8J

JUMP_43X79 PGND NC
1

PC521 PR516
4.7_0603_5%

1
PR515

PC522
22U_0603_6.3V6M

36.5K_0402_1%
Rup
22U_0603_6.3V6M

22U_0603_6.3V6M

SY8003ADFC_DFN8_2X2
@EMI@

PC523

PC524
2
2
2

2
2

FB_2.5V
1
1

FB=0.6V PR517
680P_0402_50V7K

Note:Iload(max)=3A Rdown
PC525

11.5K_0402_1%
2

@EMI@

4 4
Vout=0.6V* (1+Rup/Rdown)

Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.2VP/+0.6VSP/+2.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
AMD 0.1

Date: Thursday, December 17, 2015 Sheet 35 of 43

A B C D E
 A B C D

Module model information

SY8003A_V1.mdd

1 1

PR607

0_0402_5%
2 1
PWR_095VALW_EN <30,35,37,38>
PR602 @
0_0402_5%
+1.8VSP_ON 2 1
3V/5VALW_PG <34,35,37,38>

1
1

1M_0402_5%
0.1U_0402_16V7K
PC603

PR604
2
PU601

2
@
9
1 PGND 8
2 FB SGND 2

PJ601 @ 2 7
PG EN PL601
+3VALW 1 2 3 6 LX_1.8V 1 2
1 2 IN LX 1UH_2.8A_30%_4X4X2_F +1.8VALWP
1

4 5

68P_0402_50V8J
22U_0603_6.3V6M

JUMP_43X79 PGND NC

1
@EMI@ PR613
4.7_0603_5%

1
PC604

22U_0603_6.3V6M

22U_0603_6.3V6M
2

1
PR603
SY8003ADFC_DFN8_2X2 Rup
PC602

PC605

PC612
20K_0402_1%

2
2

2
2

2
PJ602
FB_1.8V @
+1.8VALWP 1 2 +1.8VALW
1 2

1
@EMI@ PC613
JUMP_43X79

680P_0402_50V7K
PR605
2
10K_0402_1%
Rdown

2
FB=0.6V
Note:Iload(max)=3A

3 3

2015/10/28 Delete +1.5VS power rail

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VALW_SY8003A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 36 of 43
A B C D
 5 4 3 2 1

D D

C C

Module model information

SY8288_V1.mdd

+19VB_1V @EMI@ PR703 @EMI@ PC702

4.7_1206_5% 680P_0603_50V7K
1 2 SNUB_1V 1 2
EMI@
PL701
PU701
B+ 1 2 +19VB_1V 2
IN PG
9 @ PR704
0_0402_5%
PC704
0.1U_0201_10V6K
(Common Part SH00000YE00)
10U_0805_25V6K
0.1U_0402_25V6

5A_Z120_25M_0805_2P 3 1 BST_1V 1 2 BST_1V_R 1 2 PL504

2200P_0402_50V7K
1

IN BS
1

1UH_11A_20%_7X7X3_M
EMI@ PC701

PC705
@EMI@ PC703

4
IN LX
6 LX_1V 1 2
+0.95VALWP
2

PR711 5 19

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
IN LX

1
0_0402_5%

12K_0402_1%

1
1 2 7 20

PR705

PC706

PC707

PC708

PC709

PC710

PC714

PC715
30,35,36,38> PWR_095VALW_EN GND LX
8 14 FB_1V
R1

2
2

2
GND FB

2
@ PR702 18 17 LDO_3V_1V
0_0402_5% GND VCC
1 2 EN_1V 11 10 1
<34,35,36,38> 3V/5VALW_PG EN NC PC711 FB=0.6V

1
@ PC712 ILMT_1V 13 12 2.2U_0402_6.3V6M
2

NC
1

ILMT
1

B B
0.22U_0402_10V6K
PR706 15 16 PR707
1M_0402_1% +3VALW BYP NC Vout=0.6V* (1+R1/R2) R2 20K_0402_1%
+3VALW
2

21 =0.6*(1+(12/20)) @ PJ702

2
PAD JUMP_43X118
+0.95VALWP
2

SY8288RAC_QFN20_3X3 1 2
Vout=0.96V 1 2 +0.95VALW
1

PC713
1

EN :H>0.8V ; L<0.4V 1U_0402_6.3V6K

2

@ PR708
0_0402_5%
EN pin don't floating
If have pull down resistor at HW side,
2

please delete PR601.

1

@ PR709
0_0402_5%
2

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+0.95VALW_SY8288RAC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 37 of 43
5 4 3 2 1
 5 4 3 2 1

CPU_B+ EMI@ PL801

HCB2012KF-121T50_0805
1 2
B+

10U_0805_25V6K

10U_0805_25V6K
22P_0402_50V8J

22P_0402_50V8J
MDU1516URH_POWERDFN56-8-5
1

1
+ PC802

RF@ PC840

RF@ PC838

PC804
PC801
PR1012=3.65K, PR1003=1.5K and

PC805
PR802 33U_25V_NC_6.3X4.5
330P_0402_50V7K 2K_0402_1%
PR1013=432 to set loadline -4mV/A PR803

2
1 2 1 2 2.2_0603_1% 2

PQ801
PR801 UGATE_NB1 1 2 4
<7> APU_VDDNB_SEN
PR804 PR805 PC806 PR806
10_0402_5% 1.5K_0402_1% 137K_0402_1% 390P_0402_50V7K 41.2K_0402_1%
1 2 1 2 1 2 1 2 1 2
+APU_CORE_NB

3
2
1
PL802
@ PR807 PC807 PC808 0.22UH_24A_20%_ 7X7X4_M
0_0402_5% 330P_0402_50V7K 120P_0402_50V8 PHASE_NB1 1 4

VSUMP_NB
1 2 1 2 1
PR808
2 1 2
PR809 PC809 2 3
+APU_CORE_NB

1
PC810 301_0402_1% 2.2_0603_1% 0.22U_0603_25V7K @EMI@
2.61K_0402_1%

D D
10K_0402_5%_B25/50 4250K
1

0.01U_0402_50V7K BOOT_NB1 1 2 1 2 PR811

PR810

PR1012=3.65K, PR1003=1.33K and 4.7_1206_5%

0.022U_0402_25V7K

MDU1511RH 1N POWERDFN56-8
1 2

0.1U_0402_25V6K
PR1013=374 to set loadline -4mV/A

PQ802

680P_0603_50V7K
11K_0402_1%

PC811

1 2
1

while PR1013=374 to set OCP 18.8A

PC812
PR813
1 2

for EDC 15A application. 3.65K_0603_1%

APU_CORE_NB
PR812

@EMI@ VSUMP_NB 1 2
4 TDC 12A
PH802

LGATE_NB1 PC813
2

2
PR814
Peak Current 17 A
2

PR815 1_0402_1%
PR814 set 390 ohm to OCP 19A
301_0402_1% VSUMN_NB 1 2 OCP current > 21.49A
2

VSUMN_NB 1 2
Load line -4mV/A

3
2
1
1

@ PR816 @PC815
PH1000 near APU_CORE_NB choke 100_0402_1% 220P_0402_50V7K LGATE_NB1
FSW=450kHz
1 2 1 2 DCR 1.4mohm +/-5%
2

PC814 PHASE_NB1
0.1U_0402_25V6K TYP MAX
VRHOT Assert Threshold : 0.64V
UGATE_NB1 H/S Rds(on) :11.7mohm , 14mohm
TSENSE Bias Current : 30uA PR817 BOOT_NB1 L/S Rds(on) :2.7mohm , 3.3mohm
PH1001=27.4K, 110C active 27.4K_0402_1%
Reset Threshold: 0.66V, 98C active 1
PH801
2
PR818 Module model information
20K_0402_1%

41

40

39

38

37

36

35

34

33

32

31
110C Assert Threshold: PR1016=27.4K 1 2 1 2 PU801
ISL62771_V1A.mdd for IC portion
100C Assert Threshold: PR1016=16.9K

TP

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
470K_0402_5%_B25/50 4700K
ISL62771_V1B.mdd for SW portion
PH1001 near APU_CORE_NB H/S mos 1
NTC_NB BOOT2
30

1 2 IMON_NB 2 29
PC816 1000P_0402_50V7K IMON_NB UGATE2
PR819 133K_0402_1%
3 28
1 2 <7> APU_SVC SVC PHASE2
4 27 +5VALW
<30> PROCHOT# VR_HOT_L LGATE2
@ PR820 100K_0402_1%
1 2 5 26
+3VS <7> APU_SVD SVD VDDP
@ PR821 0_0402_5% ISL62771HRTZ-T_TQFN40_5X5 PR822
+1.8VS 1 2 VDDIO 6 25 1 2
@ PR848 0_0402_5% VDDIO VDD 1_0603_5%

1U_0603_10V6K
1

1 2 7 24 LGATE1
<7> APU_SVT SVT LGATE1

1
C C
@ PR824 0_0402_5%

1U_0603_10V6K
PC817 1 2ENABLE 8 23

PC819
PHASE1
<30> VR_ON
2

ENABLE PHASE1

PC818
0.1U_0402_25V6K

2
VDDIO pin: 1.8VS for DDRII voltage level 9 22 UGATE1 CPU_B+
<7> APU_PWRGD PWROK UGATE1
1.5VS for DDRIII voltage level
1 2 APU_IMON 10 21 BOOT1
IMON BOOT1 +3VS

10U_0805_25V6K

10U_0805_25V6K
PR825

PGOOD
0918

0.1U_0402_25V6K
22P_0402_50V8J

22P_0402_50V8J
133K_0402_1%
ISUMN
ISUMP

COMP
ISEN2

ISEN1

SVC, SVD, SVT, ENABLE and

VSEN
NTC

RTN

2 PC820

MDU1516URH_POWERDFN56-8-5
PWROK no need pull high for 1

RF@ PC1473

RF@ PC824
FB

1
1

EMI@ PC823
AMD KABINI 1000P_0402_50V7K

PC821

PC822
PR828 PR827
11

12

13

14

15

16

17

18

19

Reserve PR823 connect to +1.2V for DDR4 27.4K_0402_1% 20K_0402_1% 20 PR826

2
2

2
1 2 1 2 100K_0402_1% PR829
2.2_0603_1%

2
1 2 4

PQ803
UGATE1
PH803
PH1002 near APU_CORE H/S mos 1 2 VGATE <30>

3
2
1
470K_0402_5%_B25/50 4700K PL803
VRHOT Assert Threshold : 0.64V
0.22UH_24A_20%_ 7X7X4_M
TSENSE Bias Current : 30uA +5VS
PHASE1 1 4
PH1002=27.4K, 110C active +APU_CORE
Reset Threshold: 0.66V, 98C active PR831 PC825 2 3
110C Assert Threshold: PR1031=27.4K 1 2 ISEN1 2.2_0603_1% 0.22U_0603_25V7K @EMI@

1
PR830 BOOT11 2 1 2 PR832
100C Assert Threshold: PR1031=16.9K 10K_0402_1% PC827 4.7_1206_5% PR835
PC826 PR833 100P_0402_50V8J @ PR834 3.65K_0603_1%

5
5
330P_0402_50V7K 301_0402_1% 95.3K_0402_1% VSUM+ 1 2

MDU1511RH_POWERDFN56-8-5
MDU1511RH_POWERDFN56-8-5
VSUM+ 1 2 1 2 1 2 1 2 @EMI@

1 2
PC829
330P_0402_50V7K
@ PC828

680P_0603_50V7K PR839
2.61K_0402_1%
1

PQ805
PQ804
PR837 PR838 PC832 1_0402_1%
0.1U_0402_25V6K
10K_0402_5%_B25/50 4250K

4 4 1 2
PR836

1.62K_0402_1% 137K_0402_1% 390P_0402_50V7K

0.022U_0402_25V7K

LGATE1 VSUM-
APU_core
11K_0402_1%

2
1

1 2 1 2 1 2
PC831
PC830

2
1
1

TDC 22A
PR840

Peak Current 35A

1 2

PR841 PC833

3
2
1
2

3
2
1
2

2K_0402_1% 330P_0402_50V7K OCP current > 46A

2

PR1039=3.65K, PR837=1.87K and

PH1003 near APU_CORE_NB choke PR842=536 to set loadline -4mV/A
1 2 1 2
Load line -2.1mV/A
PH804

B
PR842 PR843
FSW=450kHz B
2

619_0402_1% 10_0402_5% DCR 0.82mohm +/-5%

VSUM- 1 2 1 2
+APU_CORE TYP MAX
@ PR845
@ PC835 H/S Rds(on) :11.7mohm , 14mohm
0.1U_0402_25V6K

1
PC834

@ PR844 820P_0402_50V7K 0_0402_5%

100_0402_1% 1 2 L/S Rds(on) :2.7mohm , 3.3mohm
1 2 1 2 APU_VDD_SEN <7>
2

PR1046 set 536 ohm to OCP 26.32A 1 2

APU_VDD_RUN_FB_L <7>
0.01U_0402_50V7K

0_0402_5%
1

PC836

@ PR846
PR847
10_0402_5%
2

PR1039=3.65K, PR1040=1.58K and 1 2

PR1046=453 to set loadline -4mV/A
while PR1013=453 to set OCP 22.54A
for EDC 18A application.

+3VALW
@
PJ1103
+0.775VALWP 1 2 +0.775VALW
1

1 2
PJ1104 @
1

JUMP_43X39
JUMP_43X79
2

PU1103
2

VIN_0.775VALW 1
VIN NC
8 +3VALW
PC1132 2 7
2

4.7U_0603_6.3V6M GND NC
3.24K_0402_1%
1

3 6 PC1128
VREF VCNTL 1U_0402_6.3V6K
+3VALW
PR1142

2
1

4 5
VOUT NC
A 9 A
2
2

TP
PR1150 VREF_0.775VALW APL5336KAI-TRL_SOP8P8
100K_0402_1%
1

@ PR1151
0.1U_0402_16V7K
L2N7002WT1G_SC70-3

+0.775VALWP
1

D
PQ1108

PR1107

1K_0402_1%

0_0402_5%
1

<34,35,36,37> 3V/5VALW_PG 1 2 2
PC1131

G
2

S PC1116
L2N7002WT1G_SC70-3

2
1

D 10U_0805_6.3V6M
PQ1107

@ PR1116 0_0402_5%
2

<30,35,36,37> PWR_095VALW_EN 1 2 2
G
1

S Security Classification Compal Secret Data Compal Electronics, Inc.

3

PC1115
0.1U_0402_16V7K 2015/10/02 Title
Issued Date 2014/10/02 Deciphered Date PWR- APU_CORE/APU_CORE_NB
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 38 of 43
5 4 3 2 1
 A
B
C
D
PC1084
330U_D3_2.5VY_R6M PC1031 PC1001
22U_0603_6.3V6M 22U_0603_6.3V6M

2
1
+
2 1 2 1

PC1032 PC1002
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

2
1
+

5
5

+APU_CORE
+APU_CORE

PC1033 PC1003
PC1085 22U_0603_6.3V6M 22U_0603_6.3V6M
470U_X_2VY_R9M 2 1 2 1

2
1
+
PC1034 PC1004
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1086 2 1 2 1
470U_X_2VY_R9M
PC1035 PC1005
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

PC1036 PC1029
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

22uF*20
330uF*1
470uF*2
PC1037 PC1006
22U_0603_6.3V6M 22U_0603_6.3V6M

APU_CORE
2 1 2 1

PC1038 PC1007
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
+APU_CORE

PC1039 PC1008
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

PC1040 PC1009
10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1

4
4

PC1041 PC1010
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

2
1
+
PC1042 PC1011
22U_0603_6.3V6M 22U_0603_6.3V6M
PC1087 2 1 2 1
470U_X_2VY_R9M
PC1043 PC1012
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
+APU_CORE_NB

PC1044 PC1013
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

Issued Date
PC1045 PC1014
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

Security Classification
PC1015
22U_0603_6.3V6M
2 1

3
3

PC1016
22U_0603_6.3V6M
2 1
+APU_CORE_NB

PC1017
22U_0603_6.3V6M
22uF*15
470uF*1

2014/10/02
2 1

PC1018
22U_0603_6.3V6M
2 1
APU_CORENB

PC1019
22U_0603_6.3V6M
2 1

PC1088
22P_0402_50V8J
2 1

Compal Secret Data

Deciphered Date

2
2

2015/10/02

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Title

Date:
Custom
Document Number

Thursday, December 17, 2015

1

1
Sheet
39
+APU_CORE Cap
Compal Electronics, Inc.

of
43
Rev
0.1
A
B
C
D
 5 4 3 2 1

Module model information

VGA@ PR1403 10K_0402_1%

10K_0402_1%
VGA@ PR1402 41.2K_0402_1%
ISL62771_CZ_GFX35W_V1A.mdd for IC portion

2
ISL62771_CZ_GFX35W_V1B.mdd for SW portion

2
1

VGA@ PR1404
1

1
+5VS
+19VB_GFX VGA_EMI@ PL1401
VGA_M250=>Link +1.8VGS HCB2012KF-121T50_0805
D 1 2 B+ D

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6K
VGA_M130=>Link +3VGS

PC1404
41

40

39

38

37

36

35

34

33

32

31

1
1

PC1405
VGA@PC1402

PC1403
VGA@ PU1401

TP

ISUMP_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT_NB
UG1_GFX

2
2

2
VR_ON
VGA@ PR1401 1100K_0402_1%
2 1 30
High > 1.6V BST2_GFX

@VGA_EMI@
NTC_NB BOOT2

VGA@

VGA_EMI@
Low < 1V VGA@ 2
PR1405 1100K_0402_1% 2
IMON_NB UGATE2
29 UG2_GFX VGA@ PR1406 VGA@PC1406 VGA@
SH000010N00 (DCR:1.19mohm +/-5%)

1
2.2_0603_1% 0.22U_0603_25V7K PQ1401
3 28 LX2_GFX 1
BST1_GFX 2BST1_GFX_R 1 2

D1

G1
VGA@ <14> GPU_SVC SVC PHASE2 VGA@ PL1402
4 27 LG2_GFX +5VS 0.22UH_24A_20%_ 7X7X4_M
<14>GPU_PROCHOT# VR_HOT_L LGATE2
PR1407 LX1_GFX 7 LX1_GFX 1 4
+3VS
1 2
100K_0402_1%
<14> GPU_SVD
5
SVD ISL62771HRTZ-T_TQFN40_5X5 VDDP
26 D2/S1
2 3
+VGA_CORE
VDDIO_GFX 6 25 1 PR1409 2

@VGA_EMI@
G2
S2

S2

S2

1
VDDIO VDD

VGA@ PC1408
Delete GPU_SVT for R16M-M130 only(floating) PR1411 VGA@ PR1412

1U_0603_10V6K
1

@VGA@ PR1410 7 24 LG1_GFX VGA@ 1_0603_5% AON6992_DFN5X6D-8-7 4.7_1206_5% ISUMP_GFX1 2

6
SVT LGATE1

1
1 2 VGA@ @VGA@ PR1413 3.65K_0603_1%
+3VGS
1 2ENABLE_GFX 8 23 LX1_GFX
<8,15,30> DGPU_PWR_EN
2

ENABLE PHASE1

VGA@ PC1407
0_0402_5% PC1401 VGA@ PR1414

1U_0603_10V6K
2

2
0.1U_0402_25V6K <8> 0_0402_5% 9 22 UG1_GFX
DGPU_PWROK PWROK UGATE1

LG1_GFX
SNB_GFX ISEN1_GFX 1 2
1 2 IMON 10 21 BST1_GFX 10K_0402_1%
IMON BOOT1

1
+3VS
PR1415

PGOOD
133K_0402_1% @VGA_EMI@

ISUMN
ISUMP

COMP
ISEN2

ISEN1

VSEN
VGA@ VGA@ PC1409 VGA@ PR1416

NTC

RTN

2
1 2 PC1410 680P_0603_50V7K ISUMN_GFX_R 1 2

FB

1
1000P_0402_50V7K 1_0402_1%
VGA@ PR1418 VGA@ PR1419

11

12

13

14

15

16

17

18

19

20
10.5K_0402_1% 27.4K_0402_1% VGA@ PR1417
1 2 NTC_GFX_R 1 2 NTC_GFX 100K_0402_1%
+VGA_CORE

2
PH1402 GFX_core

ISUMN_GFX

COMP_GFX
PH1002 near APU_CORE H/S mos
ISEN2_GFX

ISEN1_GFX

VSEN_GFX
DGPU_PWROK

FB_GFX
RTN_GFX
1 2 TDC 30(1H1L)
VRHOT Assert Threshold : 0.64V Peak Current 45A
C TSENSE Bias Current : 30uA 470K_0402_5%_B25/50 4700K C
PH1002=27.4K, 110C active ISUMN_GFX_R
VGA@ PC1411
1 2
1 1 1 OCP current > 45A

330U_D1_2VY_R9M

330U_D1_2VY_R9M
330U_D1_2VY_R9M
Reset Threshold: 0.66V, 98C active + + + Load line -2.1mV/A

PC1413

VGA@ PC1414
PC1412
.22U_0402_6.3V6K
110C Assert Threshold: PR1031=27.4K VGA@ PC1415
FSW=400kHz
100C Assert Threshold: PR1031=16.9K 1 2 2 2 2 DCR 1.19mohm +/-5%
.22U_0402_6.3V6K
TYP MAX

VGA@
VGA@ PC1417
H/S Rds(on) :11.7mohm , 14mohm

VGA@
VGA@ PC1416 VGA@ PR1420 150P_0402_50V8J @VGA@ PR1421
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1%
ISUMP_GFX 1 2 1 2 1 2 1 2 L/S Rds(on) :2.7mohm , 3.3mohm
1 2ISUMP_GFX_NTC

PR1423
11K_0402_1%

330P_0402_50V7K
@VGA@ PC1418

VGA@ PR1422
0.15U_0402_10V6K
1

2.61K_0402_1% VGA@PR1425 VGA@ PC1419

VGA@

VGA@ PR1424 137K_0402_1% 390P_0402_50V7K

.022U_0402_25V4
10K_0402_5%_B25/50 4250K
1

1 2 1 2 1 2 +19VB_GFX
2
1
1

VGA@PC1421
VGA@ PC1420

1.37K_0402_1%
VGA@PR1426 VGA@PC1422

10U_0805_25V6K
10U_0805_25V6K
2
2

2K_0402_1% 330P_0402_50V7K
2

PH1003 near GFX_CORE choke 1 2 1 2

PH1401

1
1

PC1424
PR1058=3.65K, PR1040=2.1K and

VGA@ PC1423
VGA@ PR1427 VGA@ PR1428
PR1046=604 to set loadline -2.1mV/A
2

549_0402_1% 10_0402_5%

2
2
ISUMN_GFX_R 1 2 1 2 UG2_GFX
+VGA_CORE
@VGA@ PR1429
1

VGA@
@VGA@PR1431 @VGA@ 0_0402_5% VGA@
VGA@ PC1425 100_0402_1% PC1426 1 2 VGA@ PR1430 VGA@PC1427
SH000010N00 (DCR:1.19mohm +/-5%)

1
0.1U_0402_25V6 1 2 1 2 GPU_VDD_SEN 2.2_0603_1% 0.22U_0603_25V7K PQ1402
2

820P_0402_25V7 BST2_GFX 1 2BST2_GFX_R 1 2

D1

G1
VGA@ PL1403
PR1046 set 750 ohm to OCP 43.75A 1 2 0.22UH_24A_20%_ 7X7X4_M
GPU_VDD_RUN_FB_L 7 1 4
0.01U_0402_50V7K

VGA@ PR1433 LX2_GFX LX2_GFX

PR1444 0_0402_5% 10_0402_5% D2/S1
+VGA_CORE
1

VGA@ PC1428

100K_0402_5% PR1432 1 2 2 3
EN_1.5V 1 2 DGPU_PWR_EN @VGA@ @VGA_EMI@

G2
S2

S2

S2

1
VGA@ PR1434 VGA@ PR1435
2

AON6992_DFN5X6D-8-7 4.7_1206_5% ISUMP_GFX1 2

6
1

VGA@ 3.65K_0603_1%
VGA@ PR1445 PC1472
B 0.22U_0402_10V6K B
2

2
1M_0402_1% VGA@ PR1436

LG2_GFX
SNB_GFX2 ISEN2_GFX 1 2
2

10K_0402_1%

1
PC1429 VGA@ PR1437

2
680P_0603_50V7K ISUMN_GFX_R 1 2
@VGA_EMI@ 1_0402_1%
EN pin don't floating PR1058=3.65K, PR1040=2.1K and
If have pull down resistor at HW side, pls delete PR702 PR1046=604 to set loadline -2.1mV/A
while PR1046=594 to set OCP 57.16A
for EDC 45A application.
+B_1.5V @VGA_EMI@ +VGA_CORE
PR1438 @VGA_EMI@ PC1430
4.7_1206_5% 680P_0603_50V7K
VGA_EMI@ PL1404 VGA@ 1 2 SNUB_1.5V 1 2

B+ HCB2012KF-121T50_0805
1 2 +B_1.5V 2
PU1402
IN PG
9 @VGA@ PR1439
VGA@
PC1434
(Common Part)
SH00000YE00
0_0603_5%
10U_0805_25V6K
0.1U_0402_25V6

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
3 1 BST_1.5V 1 2 BST_1.5V_R 1 2 VGA@ PL1405
2200P_0402_50V7K

1
1

IN
1

BS

1
1

1
1

1
PC1437

PC1439
PC1432

@VGA_EMI@ PC1433

PC1435

PC1436

PC1440

PC1443

PC1444

PC1445

PC1447

PC1449

PC1450
VGA@ PC1431

PC1438

PC1441

PC1442

PC1446

PC1448
1UH_11A_20%_7X7X3_M
VGA_EMI@

LDO_3V_1.5V 4
IN LX
6 LX_1.5V
0.1U_0603_25V7K
1 2
+1.5VGSP

2
2

2
2

2
2

2
5 19
330P_0402_50V7K

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

@VGA@ IN LX VGA@

1
1

1
1

VGA@

VGA@
7 20

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
VGA@

VGA@

VGA@

VGA@

VGA@
VGA@ PC1454
VGA@ PC1451

VGA@ PC1452

VGA@ PC1453

VGA@ PC1455
PR1440 PR1441
GND LX
0_0402_5% 8 14 FB_1.5V
Rup

2
2

GND FB 30.1K_0402_1% 2
2

ILMT_1.5V 18 17 LDO_3V_1.5V
change PL601

0.1U_0402_10V7K
1U_0402_6.3V6K

0.1U_0402_10V7K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K
GND VCC

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

@VGA@ SM01000C000 to comm EN_1.5V 11

EN NC
10 VGA@

1
1

1
PC1459
PC1457

PC1461

PC1462

PC1468

PC1469
PC1458

PC1460

PC1463

PC1464

PC1465

PC1466

PC1467

PC1470
part SM01000P200 PC1456 FB = 0.6V
1

PR1442 ILMT_1.5V 13 12 2.2U_0402_6.3V6M VGA@

2

ILMT NC PR1443
0_0402_5%

2
2

2
15 16
+3VALW Rdown
2

BYP NC 20K_0402_1%
21
2

PAD
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1

The current limit is set to 8A, 12A or 16A when this pin VGA@
Common NB can delete +3VALW and PC15

VGA@

VGA@

VGA@

VGA@
A A

VGA@

VGA@

VGA@
VGA@
VGA@

VGA@

VGA@

VGA@

VGA@

VGA@
PC1471
is pull low, floating or pull high 1U_0402_6.3V6K
2

Vout=0.6V* (1+Rup/Rdown)
=0.6*(1+(30.1/20))
Vout=1.503V
@ PJ1401
JUMP_43X118
1 2
+1.5VGSP 1 2 +1.5VGS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/01/04 Deciphered Date 2015/01/04 Title
+VGA_CORE - ISL62771
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 40 of 43
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1 Modify +1.2V OCP setting 35 Modify PR502 from 13K to 6.04K_0402_1%(SD034604180) 2015/11/03 EVT
D D

2 Modify 0.95V feedback resistor 37 Modify PR705 from 14K to 12K_0402_1%(SD034120280) 2015/11/03 EVT

3 Modify CHARGER COMP 33 Modify PC223 from 0.015U to 0.022U_0402_25V7K(SE075223K80) 2015/11/03 EVT

4 Modify CPU_CORE COMP_NB 38 Modify PR806 from 11.5K to 41.2K_0402_1%(SD000009K00) 2015/11/03 EVT

Modify PC827 from 68P to 100P_0402_50V8J(SE071101J80)

5 Modify CPU_CORE COMP 38
Modify PR834 to un-mount
2015/11/03 EVT

6 Modify VGA_CORE ISUMN 40 Modify PR1427 from 604 to 549_0402_1%(SD034549080) 2015/11/03 EVT

7 Modify VGA_CORE Rdroop 40 Modify PR1424 from 2.1K to 1.37K_0402_1%(SD034137180) 2015/11/04 EVT

C C
8 Modify +0.95VALW output capacitor 37 Add PC714 & PC715(22U_0603_6.3V6M) 2015/11/04 EVT

PC812 & PC814 & PC831 & PC834 change from 0603 to 0.1U_0402_25V6K
9 Modify capacitor size 38 (SE00000G880) 2015/11/06 EVT

10 Modify 0 ohm P/N 35 PR511 change from to 0_0402_1% to 0_0402_5%(SD028000080) 2015/11/09 EVT

11 Modify APU CORE IC VDDIO for DDR4 design 38

Change PR821 to 0_0402_5%(SD028000080)
2015/11/10 EVT
Reserve PR823 connect to +1.2V for DDR4

12 PSYS add 0ohm connect to GND for AMD platform 33 PR322 change to 0_0402_5%((SD028000080)) 2015/11/12 EVT

Change PL1402 & PL1403 from 0.24UH_22A_+-20%_7X7X3_M(SH000010N00) to

13 Change VGA CHOKE for thermal team request 40 0.22UH_24A_20%_ 7X7X4_M(SH000011H00) 2015/11/12 EVT
B B

Add PC1472 (0.22U_0402_10V6K, SE095224K00)

14 Modify DGPU_PWR_EN sequence for GPU CORE IC 40
2015/11/12 EVT
Change PR1444 from 0_0402_5%(SD028000080) to 100K_0402_5%(SD028100380)

15 Modify VGA CHOKE location 40 Change location from PL1406 to PL1403 2015/11/18 EVT

1.PJ301 change to PL301 ISN CHOKE(SH00000YG00)

16 Add EMI solution 2.PJ701 change to PL701 EMI bead(SM01000P200)
2015/12/03 DVT
3.PR312 change from 0_0603_5% to 2.2_0603_5%
4.Add PR317 , PC217 , PC205
1.Add PC431(1U_0402_16V6K , SE00000OU00)
17 To avoid VL protection for HW USB CHG 34
2.Add PR415(100K_0402_5% , SD028100380)
2015/12/14 DVT

18 Add RF solution for CPU CORE 38 PR803 & PR829 change from 0 ohm to 2.2 0hm 2015/12/14 DVT
A A

19 Change APU_CORE output capacitor 39 PC1084 change from 470U_X_2VY_R9M to 330U_D3_2.5VY_R6M(SGA00006A00) 2015/12/14 DVT

20 Add RF solution Add PC432 , PC838 , PC839 , PC1088(22P_0402_50V8J,SE068220K80) 2015/12/14 DVT

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 41 of 43
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1 Modify footprint for QFN IC Modify PU301,PU401,PU402,PU501,PU701,PU801,PU1401,PU1402 footprint 2015/12/16 DVT

D D

2 ADD RF solution 38 Add PC840(22P_0402_50V8J,SE068220K80) 2015/12/16 DVT

3 To reduce 0-ohm part count Change PR304,PR305 ,PR336,PR322,PR821,PR1410 to 0-ohm short pad 2015/12/16 DVT

4 Delete EVT reserve 0-ohm part Delete PR823 & PR1408(EVT reserve only) 2015/12/16 DVT

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 42 of 43
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for HW
Item Reason for change PG# Modify List Date Phase

1 Modify HDMI HPD R value 21 Modify RH338 from 47K to 15K 2015/12/03 SIV

D
2 Modify KBL strap pin setting 30 Modify R2000 from 10K to 1K 2015/12/03 SIV D

3 Add KB to EC control pin 26,30 Add netname "EC_GPIO72", add R216 and mount 2015/12/03 SIV

4 Remove S15 Power Button 26 Delete SW7 2015/12/03 SIV

5 Remove I2C Port0 level shifter 8 Delete QC15,QC16 2015/12/03 SIV

6 Reduce 0 ohm 14 Delete RV186 2015/12/03 SIV

7 Add SUSP# PD R 30 R1639 change to mount 2015/12/03 SIV

8 Add GPIO pin for MB_ID 8 Add RC57,RC58 2015/12/04 SIV

9 For EMI requirement 21 CH2143,CH2144,CH2145,CH2146,CH2147,CH2148,CH2149,CH2150 change to mount 2015/12/04 SIV

C Add CC68 and mount C

10 For RF requirement 9,23,30 CH146 change to RFS@, C1263, R1560 change to RF@ from unmount 2015/12/08 SIV

11 For GPU GPIO5 function 14 DV1, RV58 change to DIS@ from unmount 2015/12/10 SIV
L13,L15,L17,L18 change to mount
12 For EMI requirement 27 R223,R224,R225,R226,R231,R232,R233,R234 change to unmount 2015/12/10 SIV

13 For RF requirement 29,30 Add C1264 (unmount),C1265,C1266,C1267,C1268,C1269 (mount) 2015/12/15 SIV

Add R2014, R183
14 For USB charger 27 R2012,R3118, C2145 change to unmount 2015/12/15 SIV
R3115 change to @, R3116,CHS250,CHS251,UHS17 change to YOGA@
15 MB side Hall sensor change to mount 20 RHS280 change to mount 2015/12/15 SIV

16 Change YOGA LED R value 26 Change R177 from 100 to 160 2015/12/15 SIV
RKBL1 change to KBL@,RKBL2 change to @,RKBL3 change to 0 ohm
17 For KBL 26,30 Add RKBL4,R2002 , QKBL122 change to @,R2000 change to 1K ohm and @ 2015/12/15 SIV
B B

18 For GPU GPIO5 function 14,30 Add RV195,R1568,R1569 2015/12/17 SIV

7,10,12,14 RC10,RC148,RD139,RV182,RV183,LV4,RV5,RV6,LV1,LV2,LV3,R125,R127,RA1,RA4
19 Reduce 0 ohm 15,16,20,22 RA3,RA2,RA42,RA43,RWL164,RTP258,R311 change to R-short 2015/12/17 SIV
24,30
Add C199,C200
20 For ESD requirement 26,30 C198,C201 change to mount 2015/12/17 SIV

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (HW)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, December 17, 2015 Sheet 43 of 43
5 4 3 2 1