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PIC16F84A: 2.2 Data Memory Organization

The data memory of the PIC16F84A microcontroller is partitioned into two areas - special function registers (SFR) and general purpose registers (GPR). The SFRs control the operation of the device and portions are banked to allow access to more than the available memory. The GPR area is also banked to provide over 116 bytes of RAM. Banking is controlled by bits in the STATUS register. The memory map shows the organization of the SFR and GPR areas across two banks, and instructions like MOVWF and MOVF can move values between the register file and memory locations.

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79 views1 page

PIC16F84A: 2.2 Data Memory Organization

The data memory of the PIC16F84A microcontroller is partitioned into two areas - special function registers (SFR) and general purpose registers (GPR). The SFRs control the operation of the device and portions are banked to allow access to more than the available memory. The GPR area is also banked to provide over 116 bytes of RAM. Banking is controlled by bits in the STATUS register. The memory map shows the organization of the SFR and GPR areas across two banks, and instructions like MOVWF and MOVF can move values between the register file and memory locations.

Uploaded by

Antonio Nappa
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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PIC16F84A

2.2 Data Memory Organization FIGURE 2-2: REGISTER FILE MAP -


PIC16F84A
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the File Address File Address
second is the General Purpose Registers (GPR) area. 00h Indirect addr.(1) Indirect addr.(1) 80h
The SFRs control the operation of the device.
01h TMR0 OPTION_REG 81h
Portions of data memory are banked. This is for both
02h PCL PCL 82h
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general 03h STATUS STATUS 83h
purpose RAM. The banked areas of the SFR are for the 04h FSR FSR 84h
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection. 05h PORTA TRISA 85h
These control bits are located in the STATUS Register. 06h PORTB TRISB 86h
Figure 2-2 shows the data memory map organization. 07h — — 87h
Instructions MOVWF and MOVF can move values from 08h EEDATA EECON1 88h
the W register to any location in the register file (“F”), 09h EEADR EECON2(1) 89h
and vice-versa.
0Ah PCLATH PCLATH 8Ah
The entire data memory can be accessed either
0Bh INTCON INTCON 8Bh
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR) 0Ch 8Ch
(Section 2.5). Indirect addressing uses the present
value of the RP0 bit for access into the banked areas of
data memory. 68
General Mapped
Data memory is partitioned into two banks which Purpose (accesses)
contain the general purpose registers and the special Registers in Bank 0
(SRAM)
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers, implemented as static RAM. 4Fh CFh
50h D0h
2.2.1 GENERAL PURPOSE REGISTER
FILE
Each General Purpose Register (GPR) is 8-bits wide
and is accessed either directly or indirectly through the
FSR (Section 2.5).
7Fh FFh
The GPR addresses in Bank 1 are mapped to Bank 0 Bank 1
addresses in Bank 0. As an example, addressing loca- Unimplemented data memory location, read as ’0’.
tion 0Ch or 8Ch will access the same GPR.
Note 1: Not a physical register.

DS35007B-page 6  2001 Microchip Technology Inc.

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