RISC-V Days Tokyo 2021 Autumn

A Design of RISC-V
RV32IMAFC Core
for MCU
as an Opensource IP

mmRISC-1
Nov. 19, 2021
Munetomo Maruyama (圓山宗智)

Rev.01 @Processing_Unit

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 1

Self Introduction
Munetomo Maruyama (圓山宗智)

As a Hobbyist for 43 years Activity

Design of Hardwares and Softwares talking Today

As an Engineer for 35 years

Development of Micro Controllers and SoCs

As a Freelance Technical Writer for 20 years

Technical Magazines and Books

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 2

Agenda

RISC-V Impact
Specification
Design
Development Works
Summary

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 3

 RISC-V Impact

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RISC-V Impact
Popular CPU Core : ARM Self-Made Original Core

Pros : Comprehensive Eco System Pros : No License / Royalty Fee

Cons: License Fee / Royalty Fee Fun! Learn a Lot!
Cons: Poor Eco System
Eco System Not Practical

ISA IDE ISA

BSP
ARM C Orig.
C++
Logic Logic
Middle
Ware RTOS

Debugger Assembler…only?

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 5

RISC-V Impact
RISC-V Essential Self-Made RISC-V Core
Pros : Comprehensive Eco System Pros : Comprehensive Eco System
Cons: No Hardware Logics only No License / Royalty Fee
Big Impact !

Eco System Eco System

IDE IDE
ISA ISA
BSP BSP
C
C C++
C++

Middle Middle RTOS

Ware RTOS Ware Debug Spec

Debugger Debugger

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 6

RISC-V Impact
Why I have made by myself?
As Public Stance
●
To have practical CPU core
●
To get large eco-system world
●
To have white-box CPU
●
To contribute to MCU designers
●
To learn more and get technical experience more
●
To educate freshers by giving it as sample design
●
To provide technical articles, technical books, technical seminars

As Private Stance (real motif)

●
Anyway, To enjoy !

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 Specification

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Specification
Target Product and Application

ASSP MCU for Industrial / Consumer Applications

Feedback Control Systems
Motor Control : FOC, Servo
Power Converter : AC-DC, DC-DC, DC-AC

Robot Drone Control Board

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 9

Specification
ISA Determination

RV32IMAFC
Fast Digital Filter Operations

32bits Fixed Point, 1cyc Multiplication (M)

32bit Floating Point, 1cyc FADD/FMUL/FMADD (F)

Small Embedded Memory Size

Compressed Code Size (C)

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 10

Specification
MCU → Low Operating Frequency
No Task Switching by Interrupt
Multi-Cores / Heterogeneous / Domain Specific (A)

FLASH
or ReRAM RAM Peri. Peri. Peri.
RV32IMAFC or MRAM
DEBUGGER

Peripheral Bus

Multi Layer Bus Matrix

RV32IMAFC RV32IMAFC RV32IMAFC

Multi Layer Bus Matrix Multi Layer Bus Matrix Multi Layer Bus Matrix

A/D PWM RAM A/D PWM RAM A/D PWM RAM

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Specification
Item Description
Core Name mmRISC-1 (Much More RISC)
ISA RV32IM[A][F]C
Supported Hart Counts 1 hart to 1,000,000 harts
Privileged Mode Machine Mode only
Pipeline 3 to 5 stages for Integer
5 to 6 stages for Floating Point
32bit Integer Multiplication 1-cycle
32bit Floating Point 1-cycle (FADD.S/FMUL.S/FMADD.S)
Debug Support External Debug Support Ver.0.13.2
JTAG Interface
Hardware Triggers x 4
Interrupts External + Machine Software + Machine Timer +
User IRQ : 64 inputs, independent vectors
16 Priority Levels for each, allow nested
Bus I/F AHB Lite, Instruction / Data / LR-SC Monitor / Debug Access
RTL Verilog-2001, System Verilog
System Proof FPGA + OpenOCD + Eclipse

Debug Support is important for practical use.

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 12
Specification
Implemented Instructions
RV32I RV32 Zifencei RV32C RV32F
LUI rd, imm FENCE.I C.LI rd, imm FADD.S fd, fs1, fs2
AUIPC rd, imm C.LUI rd, imm FSUB.S fd, fs1, fs2
ADD rd, rs1, rs2 C.ADD rd, rs2 FMUL.S fd, fs1, fs2
SUB rd, rs1, rs2 C.SUB rd’, rs2’ FDIV.S fd, fs1, fs2
ADDI rd, rs1, imm
RV32 Zicsr C.ADDI rd, imm FSQRT.S fd, fs1
SLL rd, rs1, rs2 C.ADDI4SPN rd’, uzuimm FMADD.S fd, fs1, fs2,
CSRRW rd csr, rs1 C.ADDI16SP sp, sp, imm fs3
SRL rd, rs1, rs2
CSRRS rd csr, rs1 C.SLLI rd, shamt FMSUB.S fd, fs1, fs2,
SRA rd, rs1, rs2
CSRRC rd csr, rs1 C.SRLI rd’, shamt fs3
SLLI rd, rs1, shamt
CSRRWI rd, csr, imm C.SRAI rd’, shamt FNMADD.S fd, fs1, fs2,
SRLI rd, rs1, shamt
CSRRSI rd, csr, imm C.XOR rd’, rs2’ fs3
SRAI rd, rs1, shamt
CSRRCI rd, csr, imm C.OR rd’, rs2’ FNMSUB.S fd, fs1, fs2,
XOR rd, rs1, rs2
OR rd, rs1, rs2 C.AND rd’, rs2’ fs3
AND rd, rs1, rs2 C.ANDI rd’, imm FMIN.S fd, fs1, fs2
XORI rd, rs1, imm RV32M C.MV rd, rs2 FMAX.S fd, fs1, fs2
ORI rd, rs1, imm C.BEQZ rs1’, imm FSGNJ.S fd, fs1, fs2
ANDI rd, rs1, imm MUL rd, rs1, rs2 C.BNEZ rs1’, imm FSGNJN.S fd, fs1, fs2
SLT rd, rs1, rs2 MULH rd, rs1, rs2 C.J imm FSGNJX.S fd, fs1, fs2
SLTU rd, rs1, rs2 MULHSU rd, rs1, rs2 C.JR rs1 FMV.X.W rd, fs1
SLTI rd, rs1, imm MULHU rd, rs1, rs2 C.JAL imm FMV.W.X fd, rs1
SLTIU rd, rs1, imm DIV rd, rs1, rs2 C.JALR rs1 FCVT.W.S rd, fs1
BEQ rs1, rs2, imm DIVU rd, rs1, rs2 C.LW rd’, rs1’, imm FCVT.WU.S rd, fs1
BNE rs1, rs2, imm REM rd, rs1, rs2 C.LWSP rd, imm FCVT.S.W fd, rs1
BLT rs1, rs2, imm REMU rd, rs1, rs2 C.SW rs1’, rs2’, imm FCVT.S.WU fd, rs1
BGE rs1, rs2, imm C.SWSP rs2, imm FEQ.S rd, fs1, fs2
BLTU rs1, rs2, imm C.EBREAK FLT.S rd, fs1, fs2
BGEU rs1, rs2, imm C.NOP FLE.S rd, fs1, fs2
JAL rd, imm
RV32A ILLEGAL FCLASS.S rd, fs1
JALR rd, imm FLW fd, rs1, imm
LR.W rd, rs1
LB rd, rs1, imm FSW rs1, fs2, imm
SC.W rd, rs1, rs2
LH rd, rs1, imm AMOSWAP.W rd, rs1, rs2
LW rd, rs1, imm AMOADD.W rd, rs1, rs2
LBU rd, rs1, imm AMOXOR.W rd, rs1, rs2 RV32FC
LHU rd, rs1, imm AMOAND.W rd, rs1, rs2
SB rs1, rs2, imm AMOOR.W rd, rs1, rs2 C.FLW fd’, rs1’, imm
SH rs1, rs2, imm AMOMIN.W rd, rs1, rs2 C.FLWSP fd, imm
SW rs1, rs2, imm AMOMAX.W rd, rs1, rs2 C.FSW rs1’, fs2’, imm
FENCE AMOMINU.W rd, rs1, rs2 C.FSWSP fs2, imm
ECALL AMOMAXU.W rd, rs1, rs2
EBREAK

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 13

Specification
Implemented CSRs and other Resources
Machine Mode FPU CSR Debug / Trigger DTM JTAG Reg.
CSR FCSR CSR BYPASS
FRM IDCODE
MVENDORID FFLAGS DCSR
MARCHID DPC DTMCS
FCONV DMI
MIMPID TSELECT
MSTATUS MCONTROL(TDATA1) BYPASS
MISA Interrupt ICOUNT(TDATA1)
MIE TDATA2 DM Reg.
Controller CSR
MIP TINFO
MTVEC DMSTATUS
MINTCURLVL
MSCRATCH DMCONTROL
MINTPRELVL
MEPC HARTINFO
MINTCFGENABLE0
MCAUSE HAWINDOWSEL
MINTCFGENABLE1
MTVAL HAWINDOW
MINTCFGSENSE0 Memory
MCYCLE AUTHDATA
MINTCFGSENSE1
MCYCLEH MINTPENDING0 Mapped HALTSUM0
MINSTRET HALTSUM1
MINTPENDING1 MTIME HALTSUM2
MINSTRETH MINTCFGPRIORITY0
MCOUNTINHIBIT HALTSUM3
MINTCFGPRIORITY1 MTIME_CTRL
CYCLE DATA0
MINTCFGPRIORITY2 MTIME_DIV
TIME DATA1
MINTCFGPRIORITY3 MTIME
INSTRET COMMAND
MINTCFGPRIORITY4 MTIMEH
CYCLEH COMMAND
MINTCFGPRIORITY5 MTIMECMP
TIMEH ABSTRACTCS
MINTCFGPRIORITY6 MTIMECMPH
INSTRETH SBCS
MINTCFGPRIORITY7 MSOFTIRQ
SBADDRESS0
SBDATA0

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Specification
Interrupts and Exceptions
- IRQ_MSOFT / IRQ_MTIME / IRQ_EXT
- IRQ[63:0] : 16 level priorities, Sensing Mode (Level / Edge)
- EBREAK / CBREAK / ECALL / Break Point / Misaligned Access / Bus Error
Cause and Vector
MCAUSE Vector Offset
Group Direct Vectored Description MTVAL
Interrupt Exception Code Mode Mode
1 0x03 base base + 0x000c Machine Software Interrupt (priority is controlled by software) 0x00000000
1 0x07 base base + 0x001c Machine Timer Interrupt (priority is controlled by software) 0x00000000
1 0x0b base base + 0x002c Machine External Interrupt (priority is controlled by software) 0x00000000
Asynchronous

1 0x10 base base + 0x0040 Machine IRQ00 (priority is controlled by hardware) 0x00000000
1 0x11 base base + 0x0044 Machine IRQ01 (priority is controlled by hardware) 0x00000000
1 … … … … …
1 0x4f base base + 0x013c Machine IRQ63 (priority is controlled by hardware) 0x00000000
0 0x00 base base Instruction Address Misaligned Never occurs
0 0x01 base base Instruction Access Fault Fault Instruction Address
0 0x02 base base Illegal Instruction 0x00000000
0 0x03 base base Breakpoint (Trigger, EBREAK, CBREAK) Next PC of executed
Synchronous

0 0x04 base base Load Address Misaligned Bus Error Address

0 0x05 base base Load Access Fault Bus Error Address
0 0x06 base base Store/AMO(Atomic Memory Operation) Address Misaligned Bus Error Address
0 0x07 base base Store/AMO Access Fault Bus Error Address
0 0x0b base base Environment Call from M-mode 0x00000000

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 Design

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Design
Pipeline Stages
CPU Pipeline
F Instruction Fetch

ALU DE D Decode
next D E E Execution

M Data Memory Access

MUL DE
W Write Back
next D E

DIV D d d d d LOAD D E MW
Non-Restoring next DE D E no register conflict
33cyc
LOAD D E MW
register conflict
JUMP D D - E forwarding W→ E
next - FDE
STORE D E M
Bcc D taken D not taken DE
next - FDE next DE
RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 17
Design
FPU Pipeline Pipeline Stage
i Initial : Convert Float to Internal Format
FADD D i a f
D i a f a Add : Add Internal Format
FADD
m Mul : Multiply Internal Format

f Finalize : Convert Internal Format to Float

FMUL D i m f
FMUL D i m f

FMADD D i m a f FMADD D i m a f
FMADD D i m a f FADD - D i a f

tCALC

FDIV/FSQRT D i a/m a/m a/m a/m a/m a/m a/m a/m f Goldschmidt's Algorithm
tCALC=
CPU D E M W FDIV: 11cyc (4-loops)
FSQRT: 19cyc (4-loops)
CPU D E M W
FPU - - - - - D i a f
RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 18
Design
JTAG

Floating Point Operation Unit (FPU32)

Debugger
DTM
Datapath CSR for
Pipeline Interrupt
Unit Clock Domain
Unit
Crossing

Debug Support
CSR for
Debug Debugger
Instruction DM
Fetch Unit CSR for
CPU
AHB-Lite
Bridge
AHB-Lite AHB-Lite AHB-Lite
Bridge Bridge Bridge

HARTn System Bus Access

Instruction Data & LR/SC
Abstract CMD Monitor mmRISC Block Diagram
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 Development
Works

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Development Works
Design Progress
Worked only weekend
Started on Aug. 2017 → Suspended in 2018-2019 → Finished on Sep. 2021

1. Specification and Micro Architecture

2. Test Bench, design from Top Layer
3. JTAG DTM, Check OpenOCD Communication tentatively
4. Multi Layer AHB Matrix
5. Debugger Function except for Triggers, Check Bus Access from JTAG
6. Instruction Fetch Unit
7. Pipeline Unit / Datapath Unit for basic ALU / Load / Store / Jump Instruction
8. CSR Block and Interrupt Controller
9. Trigger Module in Debugger Function
10. Functional C Model of Non-Restoring Division, and Convert to RTL
11. Privileged Instructions
12. Verify whole ISA using “riscv-arch-test”
13. Eclipse, C/C++, OpenOCD Operation and Measure Dhrystone using FPGA
14. Functional C Model of IEEE754, and Convert to RTL
15. Floating Point Instructions and CSR
16. Verify whole ISA using ‘riscv-tests”
RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 21
Development Tools
Platform Ubuntu 64bit FREE
(Parallels Desktop on MacBook Pro)
Simulator Mentor ModelSim
Intel FPGA Starter Edition FREE

IDE Eclipse IDE for Embedded C/C++ Developers FREE

Tool Chain github.com/riscv-collab/riscv-gnu-toolchain FREE

Open OCD github.com/riscv/riscv-openocd FREE

ModelSim Eclipse

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Development Tools

FPGA Board : Terasic DE10-Lite $95

(FPGA : Intel MAX 10 10M50DAF484C7G)
Tool : Quartus Prime Lite Edition FREE

USB-JTAG OLIMEX ARM-USB-OCD(-H) or compatible < $20

Quartus Prime FPGA Board

FTDI FT2232D
as USB-JTAG Interface
Terasic DE10-Lite Board
(Intel MAX 10 10M50DAF484C7G)

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 23

Development Tools
USB-JTAG Olimex ARM-USB-OCD Compatible
< $20
FTDI FT2232D DE10-Lite
USB VCCIOA 3.3V
ADBUS0 TCK
XTAL ADBUS1 TDI
ADBUS2 TDO
ADBUS3 TMS
ADBUS4
ADBUS5
ADBUS6
SRST

ADBUS7
ACBUS0 TRST
ACBUS1
ACBUS2
ACBUS3
VCCIOB 3.3V
(TXD) BDBUS0 RXD
(RXD) BDBUS1 TXD
GND GND

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Verifications
Tiny SoC for FPGA System

JTAG RAM1 RAM0

mmRISC-1 Core Debug (Data) (Instruction)
(HART x n)
System 48KB 128KB
Bus
Instr. Data LR/SC Access
M M Monitor M S S

Monitor
RAM1
Monitor Bus
RAM1 Bus

S S S M M
AHB Multi Layer Bus Matrix
M M M M

Interrupts
Clock
PLL
S S S S

Reset
MTIME INT_GEN UART GPIO

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 25

Verifications
Verification Methods
1. RTL Verification by Vector Simulation

2. Random Wait Cycle in Instruction and Data Access

3. Bus Conflicts among Multi Harts

4. Verification of C Model for non-restoring Division / Remainder

Check many corner cases in signed/unsigned values.

5. Verification of C Model for Floating Point using GNU Scientific Library

Combination of Zero / INF / QNAN / SNAN / Subnormal / Normal / Sign
Rounding Mode : RNE / RTZ / RUP / RDN, x4 cases
FADD/FSUB/FMULFDIV : 4 x (Sign 2 x Expo 256 x Frac 24) ^ 2 = 604M cases
FSQRT : 4 x (Sign 2 x Expo 256 x Frac 24) = 49K cases

6. RTL Verification using GitHub “riscv-arch-test” (ISA IMC, privileged, zifence)

7. RTL Verification using GitHub “riscv-tests” (ISA IMACF, privileged)

8. Several C applications and benchmarks on FPGA system.

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 26

Implementation
FPGA Implementation Result

RISC-V Spec RV32IMAC RV32IMAFC

Peripherals Instruction RAM 128KB
Data RAM 48KB
Multilayer BUS
UART / Timer / GPIO
Device MAX 10 10M50DAF484C7G
Quartus Prime Lite Edition Ver.20.1.1
Optimization Balanced (Normal Flow)
Logic Elements 23062/49760 = 46% 41589/49760 = 84%
Interconnect Usage 30% 38%
Frequency 20MHz 16.67MHz
Worst Setup Slack 3.999ns (met) 0.215ns (met)

RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 27

Sample Programs
Basic Samples for CPU and FPU
Startup Routine, Interrupt, UART, printf(), LED, Switch, ...

FreeRTOS Hello FreeRTOS!

1. Ported FreeRTOS 202104.00 on mmRISC-1 FPGA System. 0: Tx: Transfer1
0: Rx: Blink1
2. Operating Demo Program “Blinky”. 0: Tx: Transfer2
0: Rx: Blink2
Task / Queue / Mutex / Semaphore /User Interrupt 0: Tx: Transfer1
0: Rx: Blink1
Dhrystone …

riscv64-unknown-elf-gcc 10.2.0 DMIPS/MHz Memory

Dhrystone 2.1 -O3 1.55 1cyc RAM

Dhrystone 2.1 -O3 -funroll-loops -fpeel-loops 3.55 1cyc RAM

-fgcse-sm -fgcse-las -flto

Coremark
riscv64-unknown-elf-gcc 10.2.0 Coremark/MHz Memory
Coremark 1.0 -O3 -funroll-loops -fpeel-loops 2.76 1cyc RAM
-fgcse-sm -fgcse-las
RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 28
 Summary

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Summary

What I have done :

To Define specification of RV32IMAFC mmRISC-1

To Design mmRISC-1
To Verify mmRISC-1
To Implement mmRISC-1 in FPGA
To Program some Application Softwares

To push mmRISC-1 on Github

https://github.com/munetomo-maruyama/mmRISC-1
Provided under simple 2-clause BSD License.

Details are described in

Technical Reference Manual in “doc” directory.
RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 30
Road Map and To Do

Road Map Linux

Hi-End MCU
mmRISC-3
General MCU
mmRISC-2
Simple
mmRISC-1

mmRISC-0

To Do Quality Improvement and Bug Fixes Logic Size Reduction

Performance Improvement E Extension
Improve Coremark Reduce Debug Spec
D Extension ...
Bit Manipulation
Custom Instruction Expanding Specifications
Event Handling cJTAG Debugger
Low Latency Interrupt More Privileged Modes
Branch Target Cache AXI Bus Bridge
FLASH Memory Cache Functional Safety
... ...
RISC-V Days Tokyo 2021 Autumn Copyright © 2021 by Munetomo Maruyama 31
Conclusion
More RISC-V Cores
RISC-V Cores
Commercial IP Free IP
56% 44％
11
15

14
49
Total Total 19
Total
62 62 111 49 30

48

47 38

Yes No Yes No

Commercial Free
Outside : Floating Supported Outside : Floating Supported
Inside : Atomic Supported Inside : Atomic Supported

- Commercial IP Growing - Come on! More Free IP!

Source : RISC-V Exchange: Cores & SoCs (https://riscv.org/exchange/cores-socs/), Snap Shot on Oct.15, 2021

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 Thank you.

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