Experiment 6:

NAND-NAND and NOR-NOR Implementations

OBJECTIVES

1. To study universal gates: NAND and NOR

2. To simplify the given functions using SOP (considering 1’s) and POS (considering 0’s)
solutions.
3. To construct NAND-NAND and NOR-NOR Networks.
4. 0To translate standard format to NAND or NOR format.
5. To experimentally derive the truth tables of NAND-NAND and NOR-NOR networks and
compared these with their theoretical truth tables.

BASIC INFORMATION

Digital circuits are more frequently constructed with NAND or NOR gates. NAND or
NOR are easier to fabricate with electronic components and are the basic gates used in all
IC digital logic families. Because of the prominence of NAND and NOR gates in the design of
digital circuits, rule and procedure have been developed for conversion from Boolean
functions implemented with AND, OR and NOT into equivalent NAND and NOR logic
diagrams.

NAND Implementations

The implementations of a Boolean function with NAND gates require that the function be
simplified in the Sum of Products (SOP) form. The following rule and procedures are
observed for obtaining the NAND logic diagram from a Boolean function.
1. Simplify the function and express it in SOP form.
2. Draw a NAND gate for each product term of the function that has at least two literals.
The inputs to each NAND gate are the literals of the term. This constitutes a group of
first-level gates.
3. Draw a single NAND gate in the second level with inputs coming from the outputs of the
first-level gates.
4. A term with a single literal requires an inverter in the first level or may be
complemented and applied as an input to the second-level NAND gate.

NOR Implementations

The NOR function is the dual of the NAND function. For this reason all procedures
and rules for the NOR logic are the duals for the corresponding procedures and rules
developed for NAND logic.

The implementation of a Boolean function with NOR gates requires that the function
be simplified in Product of Sums (POS) form. The rules and procedures for obtaining the

1
NOR logic diagram from a Boolean function is similar to the three-step NAND rule, except
that the simplified expression must be in the Product of Sums and the terms for the first-
level NOR gates are the sum terms. A term with single literal requires a one-input NOR or
Inverter gate, or may be complemented and applied directly to the second-level NOR gate.

Y = A’ = (AA)’ = (A+A)’

NAND2 NOR

A NAND or a NOR can be used to replace by an inverter by tying the inputs together.

Y= AB = ((AB)’)’ = (A’+B’)’

A
Y
B

NAND NAND2
2
A
Y
B

AND2
A

NOR Y

NOR

Y= A + B = ((A + B)’)’ = (A’B’)’

A
Y
B

NOR2 NOR2

A
Y
B
A
OR2

NAND2 Y

B NOR

NAND2

Y = A XOR B = ((AB’)’(A’B)’)’ = (((A’+B)’ + (A+B’)’)’

2
 A

NAND2
NAND2 Y

NAND2
B

NAND2
NAND2
A Y
B

NOR
NOR
Y

NOR NOR

NOR
NOR

MATERIALS:

2 Long Nose Pliers Connecting Wires

2 Wire Stripper Pliers 1 Digital Trainer

Integrated Circuits (ICs)

2 74LS00
2 74LS02

PROCEDURES:

1. Plot the function in the map to simplify it. Consider the 1’s to obtain the SOP expression for
the NAND-NAND network. Do the same with map of the NOR-NOR network but this time
using the 0’s for POS.
2. After obtaining the simplified function from the K-map, construct the theoretical truth
table of each network.
3. Test the logic level of each IC supplied and report any damage to the Laboratory
Technician for immediate replacement.
4. Connect the circuit as shown in Figure 7-2. Adjust the power to 5V.
5. Derive the truth table of the circuit by applying logic combinations of 0 and 1 to the input
variables according to the specified logic level in the truth table. Record the logic signal
values in the corresponding table.
6. Repeat steps 4 and 5 for the circuit of Figure 7-3.

3
DATA AND RESULTS:

Q(A, B, C, D) =  (0,1,2,3,7,8,10) + d(5,6,11,15)

1. AND-OR Network
A. K-Map: SOP (encircle 1’s)

00 01 11 10
00
01
11
10

B. Simplified Function:

C. Theoretical Truth Table

A B D Q A’ B’ D’ B’D’ A’D
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

D. Experimental Truth Table

A B D Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

4
2. OR-AND Network
A. K-Map: POS (encircle 0’s)

00 01 11 10
00
01
11
10

B. Simplified Function:

B
D

Figure 7-2 NAND-NAND Network

D
A

Figure 7-3 NOR-NOR Network

C. Theoretical Truth Table

A B D Q A’ B’ D’ B’+D A’+D’
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

5
D. Experimental Truth Table
A B D Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

QUESTIONS:

1. Explain in your own words, the procedure for implementing Boolean function with:
A. NAND-NAND Network

B. NOR-NOR Network

2. What are the advantages and disadvantages of implementing logic circuit as NAND and
NOR universal gates against standard formats such as POS and SOP?

3. Which implementation is better: NAND or NOR implementation? Why?

4. Determine the NAND

implementation a. F(ABC) = Σ( 0, 3,
5,7)

5. Determine the NOR implementation.

a. F(ABC) = Π ( 1,2,5,7)

***For 4 and 5: Draw the logic circuit at the back of this paper