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DLD Unit-2 Quantum

Quantum is preffered practice book for last moment before exams for all student who are studying in college affiliated to AKTU.

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Ayush Dwivedi
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474 views33 pages

DLD Unit-2 Quantum

Quantum is preffered practice book for last moment before exams for all student who are studying in college affiliated to AKTU.

Uploaded by

Ayush Dwivedi
Copyright
© © All Rights Reserved
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eu Combinational Logic Oe www (2-2A to 2-16A) Part-1... © Combinational Circuits : Analysis Procedure |- Design Procedure Binary Adder-Subtractor Decimal Adder 2-24 2-2A ‘A. Concept Outline : Part-I .. B. Long and Medium Answer Type Questions Part-2 .... . (2-16A to 2-33A) (° Binary Multiplier |- Magnitude Comparator |- Multiplexers I> Demultiplexers I: Decoders le Encoders A, Concept Outline : Part-2 ... B, Long and Medium Answer Type Questions 2-16A 2-17h 21A (EC/CS/IT-Sem-3) ‘Scanned with CemScanner 2-2 A (EC/CS/IT-Sem-3) Combinational Logic PART-1 Combinational Circuits : Analysis Procedure, Design Procedure, Binary Adder-Subtractor, Decimal Adder. CONCEPT OUTLINE: PART-1 * Combinational circuits : It consists of input variables, logic gates, and output variables. The logic gates accept signals from the input variables and generate output signals. This process transforms binary information from the given input data to the required output data. * Half adder :It needs two binary inputs, augend and addend bits and two binary outputs, sum and carry. + Full adder: It performs the arithmetic sum of three input bits. It consists of three inputs and two outputs. © Half subtractor : It is a combinational circuit that subtracts two bits and produces their difference. It also has an output to specify if a 1 has been borrowed. Full subtractor : It performs a subtraction between two bits, taking into account borrow of the lower significant stage. The circuit has three inputs and two outputs. Questions-Answers Long Answer Type and Medium Answer Type Questions Que 2.1. | Describe combinational logic circuit with its block diagram. ic circuits consist of an interconnection of logic gates at any time depends upon the combination of input at instant only, and does not depend on any past cuit, the output does not depend on the past value of ¢ combinational cireuits donot require any memory. Combinational n Outputs Circuit a ig. 21.1, ‘Scanned with CamScanner os Logic Design jonel cireuit. for a change i 2BAECICSIT.5.,, the input the outpu through cirewit , the logic diagram and culminates with a set of boolean function, a truth table or po: explanation of the cireuit operation. w (a) (b) Fig. 22.1. (a) Example of combinational logic circuit and (b) Not a combinational logic circuit. Boolean expression from logic diagram : 3. Once the logic diagram is verified as a combinational circuit, then we can obtain the boolean function. i Label all gate outputs that are a function of input with arbitrary symbols. Determine the boolean functions for each gate output. 3 Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbol. Find the boolean fanctions for these gates. Repeat the step (ii) until the outputs of the circuits are obtained. Y repeated substitution of previously defined function, obtain the output boolean function in terms of input variables. 1, =AB, T,= BC,Y=T,+T,=AB+BC=Bi4 +) ‘Scanned wih CemScanner 2-4. A (EC/CS/IT-Sem-3) 4/2 [en] > ofolofololo oJolilofolo of 1folofolo olififofila 1Jolololo}o i}olifolole rfifolijo}s Hailiiliti c—| Fig. 2.2.2, Combinational Logic Que 2.3. | Explain the design procedure for combinational logic circuits. Answer 1 From the specifications of the circuits, determine the required number of inputs and outputs and assign a symbol to each. 2. _ Derive the truth table that defines the ri inputs and outputs. 3. the input variables, 4. Draw the logic diagram and ve or by simulation). Que 2.4. equired relationship between Obtain the simplified boolean functions for each output as a function of ify the correctness of the design (manually Construct a BCD to excess-8 code converter with a 4-bit adder. What must be done to change the circuit to excess-3 to BCD code converter ? Design a combinational circuit that OR AKTU 2011-12, Marks 10 converts a BCD code to excess-3 code, AKTU 2016-17, Marks 15 Answer Truth table : Input BCD Output excess-3 code Bic|pD willy | z o fo fo 1 ee Osan Oo} 1fojc o}1 | o 0 r}o ja oj. 1 0 1 do. 0 lio} o 0 epee ere ee 1 jo 1 1 o}o0 J 1}1] 0 Oho. | 4 r}afa 1}oj}1]o 0 Jo.) 0 1 o;i da oto fa 1 1lolo ‘Scanned wih CamScanner L ital Logie De: |, are plotted to obtain simplified boolean funetig, ‘The mapsin Fig for the output ‘A two-level logic dingram of each output may be obtained directly fr, the boolean expressions derived from the maps. For y > Fore i gh o0 011110 BN _00_O1__t0 00} 1) 4 1 al a 00}/ 1} | 1 2 01} 14] nf ont a| sfc] ay “hk Sy 15 ad 1 Pha Xa ha 14 aol of Mnf 10[ gf) of Ua} “ro y=CD+CD' For w ADN\_00_01_11_ 10 oof of 1] a] 2 oi} af (0a) q T6 “aL ol} x=BC+BD+BCD' w=A+BC+BD Fig. 2.4.1, Maps for BCD to excoss-3 code converter, lerived from the maps are: D CD+C’D'=CD+(C+Dy B'C+B'D+ BCD =B(C+D)+BCD' BYC + D)+ BC + DY w=A+BC+BD=A+B(C + D) The logic diagram that implements these expressions is shown i Fig. 24.2. D — ‘Scanned wih CamScanner 2-6A (EC/CSIT-Sem-2) Combinational Logie ge the circuit to an excess-3 code to BCD code, the code should be provided as input of combinational circuit and BCD number should be generated at output. Que 2.5. exce! Design a combinational circuit that converts a 3-bit Gray code to a 3-bit binary number. Implement the cireuit with i, Exclusive-OR gate NAND gate only. AKTU 2012-13, 201; Marks 10 Answer Gray code to binary code converter : Gray code Binary code | Gy B| aA iP 2 mer noocoo mw HoorHtoce mon onore Jn-nrHocoe|a loom HOS HooHorre] K-map simplification : GG, For A ForB 200001110 or 0 018, 6,5, + 6,0, 5, + 6,6,6, Baa re B=G,0G, a For C GG, 2 oo Ol 1) 0 ‘Scanned with CemScanner 2-7 A (ECICSAT Se, Digital Logic Design a Logic diagram i. Using XOR gates: G, 8G, Gg=A G, Gy | > a G,@G, d= 2 C=G, Fig. 25.2. ii, Using NAND gates: &— GRR, : (G,G,) = G,6,+G,G, = B Fig: 2.5.3. Que 2.6. | Describe half adder and full adder in brief. Implement! the circuit using logic gates. OR Design a full adder using two half adders. AKTU 2015-16, Marks Answer Half adder : 1. The block diagram of half adder is shown in Fig. 2.6.1 3 Half Adder fe Fig. 2.6.1, Half adder, where, A and B are the inputs and S and C are the outputs sum and carry respectively, ‘Scanned wih CamScanner 2-SA (EC/CSIT-Sem-3) Combinat fonal Layaie 2 ‘The truth table and K-map of the system ate shown in Fig 2.6.9. [impat_] er WE LE Using two-variable K-map, separately for the sun ad & S= ABs AB =AQB CAB The circuit can be implemented using NOK gate. = {)-c F263, Full adder: Fulladder is a circuit that performs the addition of three binary digits, It has three inputs A, Band C with two output S amd C, whore C ie the previous carry. The block diagram is shown in Vig AL 3 B—@ _ Fulladd c— G Fig. 2.6.4, Pull Adder, If there are three input variables the combinations are eight (2" & 8), Now form the truth table of the full adder. a Inputs ‘Outputs AaB aS. s On 0 | o | o 0 0 0 0 1 1 0 0 1 0 1 0 0 a] 0 L 1 | 0 | o 1 0 1 ony 0 1 1 1 | 0 0 L 1 rj L 1 For § ou 10 2 a, 3] i a aa ‘Scanned wih CamScanner Digital Logie 1 3. Que 2.7. | Describe a half subtractor with its logic diagram. Answer 1. BBALECA Sum : S= ABC+ ABC + ABC + ABC Carry C,=AB+AC+ BC A full adder can be implemented using two half adders and one OF »., Sum S= ABC + ABC + ABC = ABC + ABC + ABC CUAB + AB)+ C (AB + AB) = CAB + ABY + C'(AB + ABY =A®ROC Carry C= AB + AC + BC AB+¥CIA+B) = AB+C(A+B(A+ ANB + By = AB+ClAB+ AB+ AR) = AB+ ABC +C(AB + AB) = AB(1+C)+C\iA@B) = AB+C\A@B) Half adder eieneec sta 1 A B c Fig. 2.6.6, Full adder circuit using 2 half adder. ‘The block diagram is shown in Fig. 2.7.1. > D oe Fig. 2.7.1. Half subtractor, It has two inputs, A (minuend) and B (subtrahend) and two outputs! (difference) and B, (borrow) are produced by subtraction of two bits. ‘The truth table can be formed by keeping in mind that difference (outpt is 0 if A = B and 1 if A + B. The K-map and truth table are shown Fig. 2.7.2 ‘Scanned with CamScanner 2-10. A (EC/CSIIT-Sem-3) Combinational Logic Tnputs | Outputs NX 5 1 0 A] Bl DB ofololo Clee of ofifa rfoli ° ee 1} cs BR a IES D=AB+AB=A0B B,=AB Fig. 2.7.2. 4. The logical implementation using basic logic gates and XOR gate : a D iB XOR gate De implementation B Fig. 2.7.3. Que 28. | Design a full subtractor circuit with three inputs x, y, B,, and two outputs ‘Diff and B, ,. The circuit subtracts x-y-B,, where, B,, is the input borrow, B.,, is the output borrow and ‘Dif? is the difference. AKTU 2016-17, Marks 10 Answer 1, _Itisa combinational circuit that performs the subtraction of three binary digits. x b——— pitt 3 Fall subtractor By I Bout Fig. 2.8.1. Fig. 2.8.1 shows the block diagram approach of full subtraetor. It has three inputs x, y and B,, and two outputs ‘Diff and B,,, produced by subtraction of three input bits. 3. For the formation of truth table, eight possible combinations of three input variables with their outputs are required. Inputs Outputs Diff by Hornornorne HooHOoHHS HooonHeHe! ‘Scanned with CemScanner i Digit: al Logic Design au ZILA (ECiegry, ~ Using the concept of K, r or boolean) Pt ‘K-map, reduce the ‘ruth table toa function ¥Bin Beh Dift= xy B+ XYBi,! + xy'B, Fig. 2.8.2. A aa aor can also be implemented using two half subtractoy Diff = ayB,, Hay Bi tx yBY x = B, (xy +x'y') 4 Bi xy’ +2'y) = Bux ®@y) + Bi (x @y) = (e ®yeOB and B.., SEY 42B FYB 225 4B OF ey | Fry +Bi' sy) Gerry, | Hy +B ir'y tay 4 a'yex'y 4 YB, +B, (xy + 2x'y) = ry (B, +1) 4B ey) =2'y + Bx @yy Half subtraetor Nar o “ Fig. 2.8.3, Full subtractor circuit using 2 half subtractor. Que 2.9. | Write a short note on binary adder. A single full-adder is capable of adding three one 1-bit binary numbers or two 1-bit numbers and one previous carry, in order to add bia numbers, with more than one bit, additional full adders must employed. a A4-bit parallel adder can be constructed using four full sdidere as ae ” in Fig. 2.9.1. Those four full adders are connected in ea carry input of the next higher-order adder. An n-bit parallel constructed using ‘n’ number of full adders. ‘Scanned wih CamScanner Combinational Logie 4. Fig. 2.9.1 shows the interconnection of four full adders to provide a 4-bit binary parallel adder 4. The augend bits of A and the addend bits of B are designated by subseript numbers from right to left, with subscript 0 denoting the low order bit 5. The rries are connected in chain through the full adders. The input carry is denoted by C;,, and output is C,.,. The S output generates the required sum bits B, Ay By A, By A ry t Cou | ul Full Full adder f*~|adder [adder Ss, S, Sy Fig. 2.9.1, Block diagram of parallel udder. Ah = Augend bits ByB,B By = Addend bits S8,8,S) = Sumbits Que 2.10. | Describe carry look ahead adder. =] 1, The addition of two binary numbers in parallel implies that all the bits of the augend and addend are available for computation at the same time. ‘The carry propagation time is an important attribute of the adder because it limits the speed with which two numbers are added. 3. An obvious solution is to increase the complexity of the equipment in such a way that the carry delay time is reduced. peed ~— 2 Fig. 2.10.1, ider the circuit of the full adder shown in Fig. 2.10. w binary variables P, . If we define 2B, G,=AB, ‘Scanned wih CemScanner —” Digital Logic Design 2-18 A (ECICSIIT.g oy ee ‘The output sum and carry can respectively be expressed as S,=P,®C,,C,.=G,+PC, Cc Fig. 2.10.2. Logic diagram of carry look ahead generator, 6. G, is called a carry generate, and it produces a carry of 1 when both 4, and B, are 1, regardless ofthe input carry C,.P,is called acarry propagate because it determines whether a carry into stage i will propagate ints stage i+ 1. Cy = input carry C= Gy+P,C, C,=G,+P,C,=G,+P\G,+P,C,) =G,+P,G,+P,P.C, C,= G, + PiC,= G,+P,G, + P,P,G, + PPP.C, 4 Que 2.11. | Describe a circuit of 4-bit binary adder-subtractor with overflow detection. oR Realize a circuit which is capable of performing addition and subtraction with the same circuit, Answer 1. The addition and subtraction operations can be combined into one i with one common binary adder by including an exclusive-OR gate wit each full adder. A4bit adder-subtractor circuit is shown in Fig. M controls the operation. 2 11.1. The mode input ‘Scanned with CamScanner 2-14 A (EC/CS/IT- 3) Combinational Logic Ay Bs A, By A, By Ay Bo, vi Wy ra pg [SA] ra 4 a Me ADDIBUB rao oat I, a i 7 f v<{ Fig. 2.11.1. 4-bit adder-subtractor (with overflow detection). 3, When M =0, the circuit is an adder, and when M = 1, the circuit becomes a subtractor, each exclusive-OR gate receives input M and one of the inputs of B. 4, When M=0, we have B ® 0 = B. The full adders receive the value of B, the input carry is 0, and the circuit performs A plus B. 5. When M = 1, we have B® 1 = B’ and Cy = 1. The B inputs are all complemented and a 1 is added through the input carry. 6. The circuit performs the operation A plus the 2’s complement of B. (The exclusive-OR with output V is for detecting an overflow). 7. When two numbers with n digits each are added and the sum is a number occupying n'+ 1 digits, we say that an overflow occurred. 8 Overflow is a problem in digital computers because the number of bits that hold the number is finite and a result that contains n + 1 bits cannot be accommodated by an n-bit word. Que 2.12. | Discuss BCD adder with its block diagram. Answer BCD adder is circuit that adds two BCD digits in parallel and produces a digit which is also BCD. BCD numbers use 10 symbols (group of 0000 to 1001), ABCD adder circuit must be able to do the following 0 4-bit BCD numbrs using straight binary addition. sum is equal to or less than 9, the sumis a valid BCD number and ction is needed. bit sum is greater than 9 or ifa carry is generated from the sum, is invalid BCD number. Then the digit 6 (01100), should be the sum to produce the valid BCD symbols. ‘Scanned with CemScanner 215A EECICSIT 4 Digital Logie Design “Sem Addend (BCD digit) Augend (BCD digit) | tid tity Binary adder-1 [+— Carry in K eA Output. carry a Soa \ 1 + C=K+gZ,4%52, 0 it binary adder Sp5, 8. 8, Fig. 2.12.1. Block diagram of a BCD adder, nasa BCD Sum Decimal % | %|%/|2, | cls, S4 |S. | S, 9}ololo O}o0}o0]o]fo 0 ST oO)yo} 1} ofololo 1 1 oy Olt} oY) ofololy 0 2 oy ortt a] ololola 1 3 Oe ets Fala) 9} 0O}1}0] o 4 ofr ftoly 9}o;afo}a 5 Oo} 1 }aito 9;}o};ali lo 6 Sy 2 Fata] ololy afi 7 "Ti toflolo °;}1}olo] o 8 T}oflo}y SF} }olo fy 9 V}ofifio 1/0} o0}0] 9 10 diofsaila 1}0}o0}o}a 1 Que 2.13. Discuss excess.3 adder with its block diagram. Answer! 1. Excess-3 code is obtained by ¥ adding, 8, toa BCD code. For example, ! excess-8 code of 3 is 0011, Petia ade Fer ° 2 The excess-3 adder performs the addition of two excess-3 number. TH following steps are followed to perform excess-3 code additiom Fig. 2.13.1 shows bit, excess-3 adder, a ee ‘Scanned wih CamScanner 2-16 A (EC/CS/IT-Sem-3) Combinational Logle By By By By Ay Ay Ay em LI ]] ttt Ay Ag Ay do Ry By By By] 1 0 S Adding 3 if carry ‘Adding 13 ifearry Binary adde | 1 Cour [ Ag Ag Ay Ag ByB, By By} C= 0 I | \| 0 A-bitbinary adder [ye 06.400 EF ‘ 7 : 454 Sy Fig. 2.18.1. 4-bit excess-3 adder, i, Add two excess-3 number. ii, Ifthe above sum produces acarry, add 3 (0011) to the sum of two digits. Ifthe above sum (step 1) does not produce a carry, subtract 3 from the above sum (or) add 13 to the sum of two digits. PART-2 Binary Multiplier, Magnitude Comparator, Multiplexers, Demuttiplexers, Decoders, Encoders. CONCEPT OUTLINE : PART-2 Binary multiplier :It is a combinational circuit. which performs the multiplication of binary numbers in the same way as multiplication of decimal numbers. Magnitude comparator : It is a combinational circuit that compares two numbers A and B and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether A > B, A = Bor A B—| whether A > B, Fig. 2.16.1, Comparator | _» acB a single hit. magnitude comparator as shown in Fig. 2.16.2. is shown in Fig. 2.16.1 A Inputs | Outputs gram of a single bit magnitude comparator iy hyp, EX-NOR and AND gate is used to implement the circuit. If the yy NOR gate and two AND gates are combined, the circuit will functiz,, ‘The circuit diagram and truth table of a single bit magnitude compersiy by 2%, | Zy Heool> Hone is high when A > B, , is high when A = B, Z, is high when A B)= A, = By, A, =B, AB +AB, ‘Scanned wih ComScanner equality relation of each pair of bit® nt function as, 01,2 2-20 A (EC/CS/IT-Sem-3) (A=B) Fig. 2.16.3. 3-bit magnitude comparator using logic gates, Que 2.17. | Design and explain the logic and circuit of 4-bit magnitude comparator. AKTU 2014-15, Marks 06 OR Design a 4-bit magnitude comparator using one bit comparator modules. Answer AKTU 2015-16, Marks 10 1. Let two numbers A and B with four digits each. A=A,A,A,Ay B=B,B,B,B, 2. 2. The two numbers are equal if all pairs of significant digits are equal, B,andA,=B,, Equality relation is generated A,B + xt A,B; + 4%, A,By . + Xp AiBy + xy AjBy. is shown in Fig. 2.17.1. ‘Scanned with CemScanner i 2-21A BCICSnn. 5 S Digital Logie De (A B) (A=B) Fig. 2.17.1. (bit magnitude comparator using logic gates. Que 2.16. | Design a combinational circuit that compare two 2-i number A and B to check if they are equal. Use NAND gates only ¢ NOR gates only to implement your design. AKTU 2013-14, Marks 05) Outputs AaB > & > v & Or eooneicly 2S o'ouw 6&6 os SC2OMNSSooH ‘ ‘Scanned wih CamScanner 2-22 A (EC/CS/T-Sem-3) Combinational Logic 1} o0]o 1 1 0 0 1}]of1] 0 0 1 0 rjo]}. 1 0 0 1 1]/1]o0] 0 1 0 0 1] tao 1 1 0 0 afada 0 1 0 0 rfaja 1 0 1 0 K-map simplification : B,Bo ForA>B B,By ForA=B AyAQ\ 000110 AAS 00,01 0 00 0 0 0 o 00} LL 0 oO oO o os} of af 3] 2 of} fa} } o fo | o Is s| | is qn} (J 1 0 1 11 0 oO 1 0 wz] fol us| a2] as] as] aa 0) aetelieett ees 20) wl of oflo |G st] uy] s| | on] 0 BB, ForA

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