A Low-Power, Ultra Low-Offset, 16.

5-bit,
ΣΔ ADC for Coulomb Counting and
Fuel Gauge Applications
Jose Luis Ceballos, Christian Reindl,
Infineon Technologies Austria AG
Villach, Austria
[email protected]

Abstract - A converter macro is presented. It has been used as

part of a current-to-digital converter and as part of the
voltage measurement unit for battery charge control. It uses a
split decimation filter, which improves the resulting SNR
when system level chopping is performed. Fabricated in a
130nm CMOS process it consumes only 30µA/24µA (with or
w/o reference buffer) from a 1.35V source. Specially tailored
to be connected to low impedance sources, it accepts small
input signals with a linear range (-3dBFS) in the order of
100mVpeak. It has an SNDR > 97dB @ -3dBFS in a 1Hz BW, a
low-frequency CMRR > 100dB due to double sampling, and a
low-frequency PSR > 80dBFS for a 20mVpeak supply
disturbance (operating at maximum input level). The
chopping results in an average offset in the order of 200nV. (a)

I. INTRODUCTION 2
⎛ α ⎞
The use of low-power electronic devices increases daily H ( z ) = ⎜⎜ ⎟⎟
⎝ z − (1 − α ) ⎠
due to the fact that more functions are concurrently running
in new systems. This requires the use of new ways to
accurately control the charge/discharge process of the
supply batteries, while consuming as less additional power
as possible for these tasks.
This paper presents a flexible high-performance ADC (b)
macro specially designed to fit this kind of measurements.
The paper is organized as follows: Section II presents the Figure 1. a) Measurement system: the ADC macro is replicated to
measure current/charge (I/Q) and battery voltages, by means of
basic structure and its possible ways of use. Section III
resistive dividers and a MUX. b) Simplified block diagram of the A/D
presents the circuit considerations, while in Section IV some converter using split decimation filter and system level chopping.
measurement results are described. The paper ends with the
conclusions and acknowledgment.
II. ARCHITECTURAL CONSIDERATIONS filters and decimates the output to a rate fdec. If fchopp<fdec/2,
The basic architecture is presented in Fig. 1a. It contains then replicas of the up-modulated offset will appear in band.
the ADC macro replicated twice: one measures the input If fchopp= fdec/2 then an extra sharp filter is needed to filter
current Ana In or its charge, using a shunt resistor (of order out the up-modulated offset as in [1], where a sinc3 filter
mΩ) to ground. The other ADC uses a multiplexer for plus down-sampling was also used. If fchopp>fdec/2 then the
signals previously attenuated by resistive dividers, to find approach of [1] is not effective anymore (offset remains).
the differential voltages of stacked batteries for fuel gauge With the proposed architecture this condition doesn’t need
control. to hold, so the need of extra sharp filtering is avoided. The
price to pay is to prefilter the 1-bit data stream before de-
Figure 1b shows the simplified diagram of the delta- chopping (in this case with a 2nd order lowpass) in order to
sigma (ΔΣ) ADC macro, with system-level chopping using attenuate the out of band noise that can corrupt the in-band
embedded filtering to reduce folding effects. The input is SNR.
up-converted by the analog multiplier in front of the ΔΣ
In order to allow enough harmonics of the square wave
ADC, using analog switches switching at fchopp. The
to pass (hence, recovered signal with very small attenuation)
decimation filter of the ΔΣ ADC is split into two parts: one and small folding noise effects, the following empirical
precedes the demodulation (“de-chopping”) operation and condition must be fulfilled:
runs at the converter clock frequency (fclock), the other one

978-1-4673-5762-3/13/$31.00 ©2013 IEEE 817

 f
15 (1)
f

where f3dBLPF1 is the cutoff frequency of the filter LPF1 and

fchopp is the system chopping frequency. For normalized
values fclk=1, fchopp=1/2048, f3dBLPF1~1/60 (α=0.1), the
measured SNR penalty was in the order of 0.5dB (~ 5%).
Measuring the voltages of stacked batteries with the
macro is accomplished by means of resistive dividers. The
power consumption penalty due to this is an increase of
27µA for 5V batteries. A dummy branch to ground is
Figure 3. Simplified schematic of the switched capacitor (SC) ΔΣ
included to preserve symmetry and to get first order ADC. Full feed-forward and buffered latch enhance its performance.
cancellation of charge injection effects.
Low offset is needed because the charge is measured
over long time periods using an accurate time reference. The for a single loop modulator is not an issue, as long the 2nd
charge flow can be estimated using (2). stage compensates for the overall loop gain loss at DC.
Specifically, the integrator transfer function is given by:
(2)
; / (3)
A low offset means low drift over long operating times.
Figure 4a shows the simplified schematic of the 1st stage
amplifier. It consists of an active folded cascode first stage,
III. CIRCUITRY
followed by a differential gain stage with a Miller nulling-
The simplified schematic of the ΔΣ ADC is shown in resistor compensation scheme. Simulated DC OTA gain
Fig. 3. It is a full feed-forward structure [2] with crossed values higher than 100dB were chosen even though the
input sampling [3] to improve SNR. The passive adder is Cs/Cp ratio sets the gain in the order of 85dB (Cs~2pF,
implemented by sharing the comparator switches during the Cp~0.1fF)
auto-zero phase. The buffer reduces kick-back effects from
the regenerative latch. The reference is buffered internally with a power-
optimized buffer (Fig. 4b) which shares the same output
Due to the correlated double sampling (CDS) used, the branch for the common mode and the reference.
DAC’s settling requirement is relaxed (the data changes Implementing it with long devices improves its output
during auto-zeroing, so the delay effects are irrelevant as conductance, by increasing its gain and so the power supply
long as they are within half a clock period. Also due to CDS, rejection ratio (PSRR) at low frequencies.
the 1st stage OTA linearity is enhanced. With only this
feature enabled, the measured offset over several samples In the voltage ADC, the use of resistive dividers (15kΩ
and runs was in the order of 30µV. When system chopping equivalent input resistance) does not increase the total noise.
was also enabled, the residual long-term averaged offset was Due to the sampling operation, the thermal noise becomes
below 200nV. kT/C in the sampling capacitances, which were designed to
allow 200mVpeak input levels. High voltage switches
An advantage of this kind of CDS [5], compared to that combined with level shifters prevent any leakage, and set the
of [4], is that only one set of capacitors is used for sampling inputs to ground during the standby mode.
and for offset and flicker noise compensation, resulting in
less chip area. On the other hand, the input common mode
(CM) of the 1st stage amplifier is set at the same level than IV. MEASURED RESULTS
its output common mode, hence it needs to be shifted from
VDD/2 (the commonly used operating point) when working Figure 5 shows the measured SNR/IBIAS variation over
at low voltage levels (1.35V minimum spec), in order to temperature and supply-voltage (VDD) for the ADC +
avoid using boosted switches. Here, the CM was set to 0.6V. reference buffer block (20% power consumption is allocated
for the buffer).
Another drawback is that any parasitic capacitance Cp
between 1st stage amplifier’s input and output is periodically Figure 6 shows the variation of the SNR at -3.5dBFS in a
charged and discharged, that is, it behaves as a damping 25Hz BW as a function of the power consumption: 30µA
feedback resistor, so the integrator is a lossy one looks like a “sweet spot,” were thermal and process
independently of the OTA’s open loop gain. This pole error variations can be absorbed.

818
 Figure 5. SNR and current consumption vs. VDD for different temperatures
with a -3.5dBFS input signal in a 10Hz BW.

(a)

(b)
Figure 4. a) Schematic of the first stage OTA. Active folded-cascode Figure 6. SNR and total current consumption variation as a function of bias
stage with a Miller-compensated second stage allows gains higher than current for a -3.5dBFS input signal (Room Temperature) in a 25Hz BW.
100dB over process and temperature variations. b) Schematic of the low
power reference/common mode buffer.

TABLE I
MEASURED DATA @ ROOM TEMPERATURE
Technology 130nm
A Hanning-windowed FFT plot shows a clean spectrum Area 0.914mm x 0.363mm
for a -3.5dBFS input signal (Fig. 7) using Matlab© post (+0.124mm x 0.128mm for the
processing. Extrapolated values to 1Hz (target) indicate resistive dividers in the Voltage ADC)
performance in the order of 16.5 bits, with an average offset Clock frequency 50 kHz
in the order of 19 bits below full-scale. Power (with / without ref. 30µA/ 24µA (+27µA for VADC)
buffer) x 1.35V
Table I shows the relevant measured data for the current SNR/THD 90dB / 97dB (-3dBFS ~ 100mVp)
ADC, while Figure 8 shows room temperature offset (-3dBFS, 10Hz BW)
measurements with shorted input and system chopping Offset (with/without 200nV/30µV
system level chopping)
enabled. The first prototype layout is shown in Fig. 9.
V. CONCLUSIONS
ACKNOWLEDGMENT
An ADC macro was designed using split decimation
The authors would like to thank Mr. L.A. Schilke for his
filtering. Two different runs and several samples have been
endless patience and dedication with the overnight
used to obtain the measured data. A later version included in
measurements, and Mr. Jojo Paca for his careful and
a bigger system uses a 16-bit final digital output, and gave
excellent layout.
similar performance.

819
 Figure 7: One Msample FFT @ -3.5 dBFS. Chopper disabled.
fclk=50kHz, BW=5Hz, SNR=93.1dB, THD=97.8dB

Figure 9. Layout of the first prototype. Dimensions: 0.9mm x

0.36mm.

Figure 8. Offset measurements with chopper enabled. Top: averaged

offset (each run represents the offset of one Msample acquisition at
50kHz). Bottom: individual offset per run.

REFERENCES
[1] D. McCartney et al., “A Low-Noise Low-Drift Transducer ADC,”
IEEE JSSC, vol. 32, no. 7, pp. 959-967, July 1997.
[2] J. Silva, U. Moon, J. Steensgaard, and G. Temes, "A wideband low-
distortion delta-sigma ADC topology," Electron. Lett., vol. 37, no.
12, pp. 737-738, Jun. 7, 2001
[3] Ichiro Fujimori, “High Resolution CMOS Analog-to-Digital and
Digital-to-Analog Converters using Delta-Sigma Modulation,”
Doctor of Engineering dissertation, Hiroshima University, Jun. 2003.
[4] K. Nagaraj, “SC circuits with reduced sensitivity to finite amplifier
gain,”in Proc. IEEE Int. Symp. Circ. Syst, 1986, pp.618-621.
[5] M. Pertijs, J. Huijsing, “Precision Temperature Sensors in CMOS
Technology,” 2006, Ed. Springer.

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