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5.1 Lab Assignment # 5

This lab assignment involves learning Verilog procedures and module instantiation. Students are asked to: 1) Generate truth tables and write Verilog modules for several logic expressions involving inputs A, B, C and outputs X, Y, Z. 2) Design a Verilog code to convert BCD to excess-3 code by preparing a truth table, identifying Boolean functions, and writing a module to implement it with testbench verification. 3) Write Verilog modules for a half adder and full adder by developing Boolean expressions and logic circuits from given truth tables, with testbench verification. Submission instructions require students to compile Verilog code, testbenches, and waveforms into a single PDF

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Sushain Thakur
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43 views

5.1 Lab Assignment # 5

This lab assignment involves learning Verilog procedures and module instantiation. Students are asked to: 1) Generate truth tables and write Verilog modules for several logic expressions involving inputs A, B, C and outputs X, Y, Z. 2) Design a Verilog code to convert BCD to excess-3 code by preparing a truth table, identifying Boolean functions, and writing a module to implement it with testbench verification. 3) Write Verilog modules for a half adder and full adder by developing Boolean expressions and logic circuits from given truth tables, with testbench verification. Submission instructions require students to compile Verilog code, testbenches, and waveforms into a single PDF

Uploaded by

Sushain Thakur
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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School of Computer Science Engineering and Technology

Course- BTech Type- Core


Course Code- CSET105 Course Name- Digital Design
Year- 2022 Semester- Even
Date- Batch-

5.1 Lab Assignment # 5


In this lab, we shall learn about the procedures in Verilog, generation of modules from a truth table.  
We also further explore the “Module Instantiation”, where a previously designed module will be
used other modules. 
Q1. Consider the following expressions. Here A, B, and C are acting as input.  
X = A.B’.C + A’.B.C’ 
Y = A’.B’ + B.C’ 
Z = X’.Y + Y’.X 
i. Generate the truth table for each expression. 
ii. Write down the modules for X and Y. use the instances of X and Y to implement the module
for Z. 
iii. Verify the same with the corresponding Testbench code. 
 
  
Q2. Design a Verilog code for BCD to excess-3 code. Using behavioral design then test with test bench
code.  
a. Prepare truth table. 
b. Identify Boolean function for each output using K-maps.  
c. Write Verilog code for implement the module. 
d. Check with test bench.  

Q3. A half-adder is used to add two single bit inputs. It produces a single bit output and a possible carry bit.
Below is the truth table for the same.

(i) Develop the Boolean expression and logic circuit for the given truth table.
(ii) Write a Verilog module for Universal NOR gate. Utilize the instances of NOR gate only to write a structural
Verilog code for Half adder.
(iii) Verify it with respective testbench code.
School of Computer Science Engineering and Technology

Q.4 The half adder in the previous question can only add two one-bit numbers when there is no carry bit,
which is not sufficient in many cases. While a full-adder has two one-bit inputs, a carry-in input, a sum output,
and a carry-out output. Below truth table represents a full adder.

(i) Utilize the above truth table to design the Boolean expression and digital circuit for the full adder.
(ii) Write the behavioral Verilog code for the full adder.
(iii) Verify it with respective Testbench code.

Submission Instructions:  
 Prepare the submission file according to the following process: 
1. Copy the Verilog code, the Test Bench Code in a Word File.  
2. Take the ScreenShot of Waveform and paste into the same word file. 
3. Repeat Step 1 and 2 for all the programs.  
4. Copy and Paste all the Verilog code, Testbench Code and Waveform into a
single word file as 1_verilog, 1_TestBench, 1_Waveform, 2_verilog, 2_TestBench,
2_Waveform… etc. 
5. Convert it into pdf file, name it as RollNo_Assignment# (Example: E20CSE001_
Assignment3.pdf). 
6. Submit your file on LMS within the deadline.  
 Write your Name and Roll No. as comment before starting of each program. Keep in
mind this is Mandatory. Failing which you may lose your marks. 
 Make it sure that in each program, you have mentioned enough comments regarding
the explanation of program instructions. 
 Each student will submit their assignment on their corresponding group slot only.  
 Late submission will lead to penalty.  
 Any form of plagiarism/copying from peer or internet sources will lead penalty.  
 Following of all instructions at submission time is mandatory. Missing of any
instructions at submission time will lead penalty. 
 

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