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VHDL Logic Gates & Adders Design

The document describes designing logic gates and a ripple carry adder using VHDL. It discusses implementing logic gates like AND, OR, NOR, etc. using VHDL and simulating, synthesizing and downloading the design to an FPGA board. It then discusses designing a 14-bit ripple carry adder using VHDL by connecting full adders in series and generating the sum and carry outputs. Procedures for writing VHDL code, simulating, synthesizing and implementing the designs on FPGA are provided.

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0% found this document useful (0 votes)

68 views87 pages

VHDL Logic Gates & Adders Design

Uploaded by

NAVEENTEJATEJ

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 87

VLSI Lab III/II

1. LOGIC GATES
Date :
1. AIM: Design Logic gates using VHDL, simulate using ISim Simulator, Synthesize using
Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

VHDL supports logical operations like AND, OR, NOR ,NAND, XOR, XNOR,NOT.

In this program Logic gates Entity has two inputs A & B and six outputs Y0,Y1……Y6.

Logic gates are described using data flow model.

Logic
Gates

4. VHDL Program:

Dataflow Style:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_Arith.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

entity allgates is

Port ( a,b : in STD_LOGIC;

c,d,e,f,g,h,i : out STD_LOGIC);

end allgates;

architecture Behavioral of allgates is

Dept. of ECE, SIET Page 1
VLSI Lab III/II

begin

c<=a and b;

d<=a or b;

e<= not a;

f<=a nand b;

g<=a nor b;

h<=a xor b;

i<=a xnor b;

end Behavioral;

Sub Program: And Gate :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_Arith.ALL;

use IEEE.STD_LOGIC_Unsigned.ALL;

entity and_gateis

Port ( a,b : in STD_LOGIC;

c : out STD_LOGIC);

end and_gate;

architecture Behavioral of and_gate is

begin

c<= a AND b;

end Behavioral;

Sub Program: OR Gate :

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

Dept. of ECE, SIET Page 2

VLSI Lab III/II

useieee.std_logic_unsigned.all;

entity or_gate is

Port ( a,b : in STD_LOGIC;

d : out STD_LOGIC);

end or_gate;

architecture Behavioral of or_gate is

begin

d<= a or b;

end Behavioral;

Sub Program: Not Gate :

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity not_gate is

Port ( a : in STD_LOGIC;

e : out STD_LOGIC);

end not_gate;

architecture Behavioral of not_gate is

begin

e<= not a;

end Behavioral;

Sub Program: Nand Gate :

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

Dept. of ECE, SIET Page 3

VLSI Lab III/II

use ieee.std_logic_unsigned.all;

entity nand_gate is

Port ( a,b : in STD_LOGIC;

f : out STD_LOGIC);

end nand_gate;

architecture Behavioral of nand_gate is

begin

f<= a nand b;

end Behavioral;

Sub Program: Nor Gate :

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity nor_gate is

Port ( a,b : in STD_LOGIC;

g : out STD_LOGIC);

end nor_gate;

architecture Behavioral of nor_gate is

begin

g<= a nor b;

end Behavioral;

Sub Program: XorGate :

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

Dept. of ECE, SIET Page 4

VLSI Lab III/II

use ieee.std_logic_unsigned.all;

entity xor_gate is

Port ( a,b : in STD_LOGIC;

h : out STD_LOGIC);

end xor_gate;

architecture Behavioral of xor_gate is

begin

h<= a xor b;

end Behavioral;

Sub Program: XnorGate :

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity xnor_gate is

Port ( a,b : in STD_LOGIC;

i : out STD_LOGIC);

end xnor_gate;

architecture Behavioral of xnor_gate is

begin

i<= a xnor b;

end Behavioral;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

Dept. of ECE, SIET Page 5

VLSI Lab III/II

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. Function Table:

Y0= Y1= Y2= Y3= Y4= Y5=

Y6=
A B A AND A OR A NAND A NOR A XOR A XNOR
NOT A
B B B B B B

0 0

0 1

1 0

1 1

7. RESULT:

Dept. of ECE, SIET Page 6

VLSI Lab III/II

2. 14-BIT RIPPLE CARRY ADDER

1. AIM: Design Ripple carry adder using VHDL, simulate using ISim Simulator, Synthesize
using Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. Theory:
Ripple Carry Adder adds 2 n-bit number plus carry input and gives n-bit sum and a carry
output. The Main operation of Ripple Carry Adder is it ripple the each carry output to carry
input of next single bit addition. Each single bit addition is performed with full Adder operation
(A, B, Cin) input and (Sum, Cout) output. The 4-bit Ripple Carry Adder VHDL Code can be
Easily Constructed by Port Mapping 4 Full Adder. The following figure represent the 4-bit
ripple carry adder.

In the above figure, A, B 4-bit input, C0 is Carry in and S 4-bit output , C4 is Carry out. The
remaining C1, C2, C3 are intermediate Carry. They are called signals in VHDL Code.

4. VHDL Program:
Dataflow model

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--entity declaration with port definitions

entity rc_adder is
Dept. of ECE, SIET Page 7
VLSI Lab III/II

port( num1 : in std_logic_vector(3 downto 0); --4 bit input 1

num2 :in std_logic_vector(3 downto 0); -- 4 bit input 2

sum : out std_logic_vector(3 downto 0); -- 4 bit sum

carry : out std_logic -- carry out.);

end rc_adder;

--architecture of entity

architecture Behavioral of rc_adder is

--temporary signal declarations(for intermediate carry's).

signal c0,c1,c2,c3 : std_logic := '0';

begin

--first full adder

sum(0) <= num1(0) xor num2(0); --sum calculation

c0 <= num1(0) and num2(0); --carry calculation

--second full adder

sum(1) <= num1(1) xor num2(1) xor c0;

c1 <= (num1(1) and num2(1)) or (num1(1) and c0) or (num2(1) and c0);

--third full adder

sum(2) <= num1(2) xor num2(2) xor c1;

c2 <= (num1(2) and num2(2)) or (num1(2) and c1) or (num2(2) and c1);

--fourth(final) full adder

sum(3) <= num1(3) xor num2(3) xor c2;

c3 <= (num1(3) and num2(3)) or (num1(3) and c2) or (num2(3) and c2);

--final carry assignment

carry <= c3;

end Behavioral;

Dept. of ECE, SIET Page 8

VLSI Lab III/II

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. RESULT:

Dept. of ECE, SIET Page 9

VLSI Lab III/II

2.2. 4 Bit Carry Look Ahead Adder

1. AIM: Design 4 Bit Carry Look Ahead Adder using VHDL, simulate using ISim Simulator,
Synthesize using Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. Theory

Carry Look Ahead Adder is fastest adder compared to Ripple carry Adder. For the Purpose of
carry Propagation, Carry look Ahead Adder construct Partial Full Adder, Propagation and
generation Carry block. It avoid Carry propagation through each adder.

In order to implement Carry Look Ahead Adder, first implement Partial Full Adder and then
Carry logic using Propagation and generation Block.

Dept. of ECE, SIET Page 10

VLSI Lab III/II

Partial Full Adder consist of inputs (A, B, Cin) and Outputs (S, P, G) where P is Propagate
Output and G is Generate output.

VHDL code for carry look ahead adder can be implemented by first constructing Partial full
adder block and port map them to four times and also implementing carry generation block as
shown below.

4. VHDL Program:

Dataflow Model
Library IEEE;

Use IEEE.STD_LOGIC_1164.ALL;

Use IEEE.STD_LOGIC_ARITH.ALL;

Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity CARRYLOOK is

Port ( A,B : in STD_LOGIC_VECTOR (3 downto 0);

CIN : in STD_LOGIC;

S : out STD_LOGIC_VECTOR (3 downto 0));

end CARRYLOOK;

Architecture Behavioral of CARRYLOOK is

SIGNAL C:STD_LOGIC_VECTOR(4 DOWNTO 0);

SIGNAL P:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL G:STD_LOGIC_VECTOR(3 DOWNTO 0);

Begin

G1: FOR I IN 0 TO 3

GENERATE

P(I)<=A(I) XOR B(I);

G(I)<=A(I) AND B(I);

S(I)<=P(I) XOR C(I);

end GENERATE;

Dept. of ECE, SIET Page 11

VLSI Lab III/II

C(0)<=CIN;

G2: FOR I IN 0 TO 3

GENERATE

C(I+1)<= (C(I) AND P(I))OR G(I);

end GENERATE;

end Behavioral;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

RESULT:

Dept. of ECE, SIET Page 12

VLSI Lab III/II

3(a) 16:1 mux through 4:1 mux

1. AIM: Design 16:1 mux through 4:1 mux using VHDL, simulate using ISim Simulator,
Synthesize using Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. Theory:
A digital multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. Multiplexing means transmitting a large number
of information units over a smaller number of channels or lines. The selection of a particular
input line is controlled by a set of selection lines. Normally, there are 2 n input lines and n
selection lines whose bit combinations determine which input is selected. A multiplexer is also
called a data selector, since it selects one of many inputs and steers the binary information to the
output lines. Multiplexer ICs may have an enable input to control the operation of the unit.
When the enable input is in a given binary state (the disable state), the outputs are disabled, and
when it is in the other state (the enable state), the circuit functions as normal multiplexer. The
enable input (sometimes called strobe) can be used to expand two or more multiplexer ICs to
digital multiplexers with a larger number of inputs.The size of the multiplexer is specified by the
number 2n of its input lines and the single output line. In general, a 2 n – to – 1 line multiplexer
is constructed from an n – to 2n decoder by adding to it 2 n input lines, one to each AND gate.
The outputs of the AND gates are applied to a single OR gate to provide the 1 – line output.

4. VHDL Program:
Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity hema_16x1mux is

port(a:instd_logic_vector(15 downto 0);

s: in std_logic_vector(3 downto 0);

Z:out std_logic);

End hema_16x1mux;

Architecture hema_16x1mux1 of hema_16x1mux is

Dept. of ECE, SIET Page 13
VLSI Lab III/II

signal z1,z2,z3,z4:std_logic;

component hema_4x1mux is

port(a,b,c,d,s0,s1:in std_logic;

Q:out std_logic);

End component;

Begin

M1: hema_4x1mux port map(a(0),a(1),a(2),a(3),s(0),s(1),z1);

m2: hema_4x1mux port map(a(4),a(5),a(6),a(7),s(0),s(1),z2);

m3: hema_4x1mux port map(a(8),a(9),a(10),a(11),s(0),s(1),z3);

m4: hema_4x1mux port map(a(12),a(13),a(14),a(15),s(0),s(1),z4);

m5: hema_4x1mux port map(z1,z2,z3,z4,s(2),s(3),z);

end hema_16x1mux1;

Subprogram:

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity hema_4x1mux is

port(a,b,c,d : in std_logic;

S0,s1 : in std_logic;

q : out std_logic);

end hema_4x1mux;

Architecture hema_4x1mux1 of hema_4x1mux is

Begin

Process(a,b,c,d,s0,s1)

Begin

If s0 ='0' and s1 ='0' then q <= a;

Dept. of ECE, SIET Page 14

VLSI Lab III/II

Elsif s0 ='1' and s1 ='0' then q <= b;

elsif s0 ='0' and s1='1' then q <= c;

else q <=d;

end if;

End process;

End hema_4x1mux1;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. RESULT:

Dept. of ECE, SIET Page 15

VLSI Lab III/II

3 (b). 3 to 8 DECODER THROUGH 2 TO 4 DECODER

1. AIM: Design Ripple carry adder using VHDL, simulate using ISim Simulator, Synthesize
using Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. Theory:
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One
of these outputs will be active High based on the combination of inputs present, when the
decoder is enabled. That means decoder detects a particular code

4. VHDL Program:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity dec3to8 is

Port ( w : in STD_LOGIC_VECTOR (2 downto 0);

EN : in STD_LOGIC;

Y : out STD_LOGIC_VECTOR (7 downto 0));

Dept. of ECE, SIET Page 16

VLSI Lab III/II

end dec3to8;

architecture Behavioral of dec3to8 is

component dec2to4 is

Port ( enable : in STD_LOGIC;

sw : in STD_LOGIC_VECTOR (1 downto 0);

led : out STD_LOGIC_VECTOR(3 downto 0));

end component;

signal m0: STD_LOGIC;

signal m1: STD_LOGIC;

begin

U1: dec2to4 Port map(m1,w(1 downto 0),Y(7 downto 4));

U2: dec2to4 Port map(m0,w(1 downto 0),Y(3 downto 0));

m0 <= NOT w(2) AND EN;

m1 <= w(2) AND EN;

end Behavioral;

Subprogram:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity dec2to4 is

Port ( enable : in STD_LOGIC;

sw : in STD_LOGIC_VECTOR (1 downto 0);

led : out STD_LOGIC_VECTOR (3 downto 0));

end dec2to4;

architecture Behavioral of dec2to4 is

begin

led <= "0000" when enable='0' else

Dept. of ECE, SIET Page 17

VLSI Lab III/II

"0001" when sw="00" else

"0010" when sw="01" else

"0100" when sw="10" else

"1000";

end Behavioral;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. RESULT:

3 to 8 DECODER THROUGH 2 TO 4 DECODER has been designed using VHDL, simulated

using ISim Simulator, Synthesized using XST (Xilinx Synthesis Tool) and Implemented using
SPARTAM 3 XC3S400 TQ 144.Verified with expected results.

Dept. of ECE, SIET Page 18

VLSI Lab III/II

4. 8:3 ENCODER
1. AIM: Design 8:3 Encoder using VHDL, simulate using ISim Simulator, Synthesize using
Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

An Encoder is a combinational circuit that performs the reverse operation of Decoder.It has
maximum of 2^n input lines and ‘n’ output lines, hence it encodes the information from 2^n
inputs into an n-bit code. It will produce a binary code equivalent to the input, which is active
High. Therefore, the encoder encodes 2^n input lines with ‘n’ bits

The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs : Y7 to Y0 and 3 outputs : A2,
A1 & A0. Each input line corresponds to each octal digit and three outputs generate
corresponding binary code.The figure below shows the logic symbol of octal to binary encoder:

Logic Diagram

Dept. of ECE, SIET Page 19

VLSI Lab III/II

Truth Table

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

4. VHDL Program:
module encoderbehav(d, a,b,c);

input [7:0] d;

output a,b,c;

reg a,b,c;

always @ (d [7:0]) begin

a= d[4] | d[5] | d[6] | d[7];

b= d[2] | d[3] | d[6] | d[7];

c= d[1] | d[3] | d[5] | d[7];

end

endmodule

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

Dept. of ECE, SIET Page 20

VLSI Lab III/II

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6.RESULT:

8:3 Encoder has been designed using VHDL, simulated using ISim Simulator, Synthesized
using XST (Xilinx Synthesis Tool) and Implemented using SPARTAM 3 XC3S400 TQ
144.Verified with expected results.

Dept. of ECE, SIET Page 21

VLSI Lab III/II

5. 8 Bit Parity Generator and Checker

1. AIM: Design Logic gates using VHDL, simulate using ISim Simulator, Synthesize using
Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY: The 8-bit parity generator circuit

Truth table

4. VHDL Program:
library ieee;

use ieee.std_logic_1164.all;

entity parity is

port( data:inbit_vector(7 downto 0);

Dept. of ECE, SIET Page 22
VLSI Lab III/II

even_p,odd_p: out bit);

end parity;

architecture parity_gen of parity is

signal temp :bit_vector(5 downto 0);

begin

temp(0)<=data(0) xor data(1);

temp(1)<=temp(0) xor data(2);

temp(2)<=temp(1) xor data(3);

temp(3)<=temp(2) xor data(4);

temp(4)<=temp(3) xor data(5);

temp(5)<=temp(4) xor data(6);

even_p<= temp(5) xor data(7);

odd_p<= not(temp(5) xor data(7));

end parity_gen;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results.

Dept. of ECE, SIET Page 23

VLSI Lab III/II

The 8-bit parity checker circuit

Truth table

4. VHDL Program:
library ieee;

use ieee.std_logic_1164.all;

entity parity_chk is

port( data:inbit_vector(7 downto 0);

p: in bit;

e: out bit);

end parity_chk;

architecture parity_arch of parity_chk is

signal temp :bit_vector(6 downto 0);

Dept. of ECE, SIET Page 24
VLSI Lab III/II

begin

temp(0)<=data(0) xor data(1);

temp(1)<=temp(0) xor data(2);

temp(2)<=temp(1) xor data(3);

temp(3)<=temp(2) xor data(4);

temp(4)<=temp(3) xor data(5);

temp(5)<=temp(4) xor data(6);

temp(6) <= temp(5) xor data(7);

e <= p xortemp(6);

end parity_arch;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. RESULT:

Dept. of ECE, SIET Page 25

VLSI Lab III/II

6 .Flipflops
6.1. D FLIP FLOP 74X74
1. AIM: Design D flip flop using VHDL, simulate using ISim Simulator, Synthesize using
Xilinx Synthesis Tool (XST) and Implement using SPARTAN 3 /2 FPGA

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

IC 74X74 is a positive edge triggered DFF with active low preset and clear. In this
program DFF architecture is described using behavior model.

3.1 PIN DIAGRAM

4. VHDL Program:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity dff is

Port ( d,clk,reset : in STD_LOGIC;

q,qb : out STD_LOGIC);

end dff;

architecture Behavioral of dff is

begin

process(d,clk,reset)

begin
Dept. of ECE, SIET Page 26
VLSI Lab III/II

if (clk 'event and clk='1') then

if (reset='1') then q<='0';qb<='1';

else q<= d; qb<= not d;

end if;

end process;

end Behavioral;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device

10. Generate programming file

11. Down load design to the target device on FPGA/CPLD demo board

12. Verify the functionality of design with expected results.

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6. FUNCTION TABLE:

CLK D RESET Q NQ

1 0 0 0 1

0 1 1 0 1

1 1 1 0 1

1 1 0 1 0

0 0 0 1 0

7. RESULT

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6.2 T flip-flop
1. AIM: Design T flip-flop using VHDL, simulate using ISim Simulator, Synthesize using
Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

The T in T flip-flop stands for ‘toggle’. This is because a T flip-flop toggles (changes) its value
whenever the input is high. When the input is low, the output remains the same as the previous
output. A T flip-flop can be made using an SR latch, as shown above. Or it can be made using a
JK flip-flop as shown below.

Truth table for T flip-flop

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The entity will declare the input and output ports for the T flip-flop. We have the clock, the
reset, and the T input as actual inputs. The outputs are just the usual Q and Qb. As has been the
case with all the remaining flip-flops, we will use behavioral architecture. That’s the entity-
architecture pair sorted right there.

4. VHDL Program:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity T_FLIPFLOP_SOURCE is

Port ( T,CLK,RES,TEMP : in STD_LOGIC;

Q,QB : out STD_LOGIC);

end T_FLIPFLOP_SOURCE;

architecture Behavioral of T_FLIPFLOP_SOURCE is

begin

PROCESS(T,CLK,RES)

VARIABLE TEMP:STD_LOGIC:='0';

BEGIN

IF(RES='1')THEN

TEMP:='0';

ELSIF(RISING_EDGE(CLK))THEN

IF(T='1')THEN

TEMP:= NOT TEMP;

END IF;

Q<= NOT TEMP;

QB<= TEMP;

END PROCESS;
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END BEHAVIORAL;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6 RESULT:

T flip flop has been designed using VHDL, simulated using ISim Simulator, Synthesized using
XST (Xilinx Synthesis Tool) and Implemented using SPARTAM 3 XC3S400 TQ 144.Verified
with expected results.

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6.3 SR FLIPFLOP
1. AIM: Design SR FlipFlop using VHDL, simulate using ISim Simulator, Synthesize using
Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

4. VHDL Program:
module srflipflop(s, r, clk, rst, q, qbar);

input s;

input r;

input clk;

input rst;

output q;

output qbar;

reg q,qbar;

always @ (posedge(clk) or posedge(rst)) begin

if(rst==1'b1) begin

q= 1'b0;qbar= 1'b1;

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end

else if(s==1'b0 && r==1'b0)

begin

q=q; qbar=qbar;
end

else if(s==1'b0 && r==1'b1)

begin

q= 1'b0; qbar= 1'b1;

end

else if(s==1'b1 &&r==1'b0)

begin

q= 1'b1; qbar= 1'b0;

end

else

begin

q=1'bx;qbar=1'bx;

end

endmodule

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

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9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6.RESULT:

SR Flip Flop has been designed using VHDL, simulated using ISim Simulator, Synthesized
using XST (Xilinx Synthesis Tool) and Implemented using SPARTAM 3 XC3S400 TQ
144.Verified with expected results.

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6.4 JK FLIPFLOP

1. AIM: Design JK Flip Flop using VHDL, simulate using ISim Simulator, Synthesize using
Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

4. VHDL Program:
Behavioral Modeling:

module jkff(j, k, clk, rst, q, qbar);

input j;
input k;
input clk;
input rst;
output q;
output qbar;
reg q;
reg qbar;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
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q=1'b0;
qbar=1'b1;
end
else if (j==1'b0 && k==1'b0)
begin
q=q;
qbar=qbar;
end
else if (j==1'b0 && k==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if (j==1'b1 && k==1'b0)
begin
q=1'b1;
qbar=1'b0;
end
else
begin
q=~q;
qbar=~qbar;
end
end
endmodule

5. PROCEDURE:

1. Open Xilinx Project Navigator

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2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. RESULT:

JK Flip Flop has been designed using VHDL, simulated using ISim Simulator, Synthesized
using XST (Xilinx Synthesis Tool) and Implemented using SPARTAM 3 XC3S400 TQ
144.Verified with expected results.

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7. 8 BIT SYNCHRONOUS UP-DOWN COUNTER

1. AIM: Design 8 Bit Synchronous Up-Down Counter using VHDL, simulate using ISim
Simulator, Synthesize using Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3
FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

When counter is clocked such that each flipflop in the counter is triggered at the same time, the
counter is called as synchronous counter.

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4. VHDL Program:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updown_count is

Port ( clk, rst,updown : in STD_LOGIC;

count : out STD_LOGIC_VECTOR (3 downto 0));

end updown_count;

architecture Behavioral of updown_count is

signal temp:std_logic_vector(3 downto 0):="0000";

begin

process(clk,rst)

begin

if(rst='1')then temp<="0000";

elsif(rising_edge(clk))then

if(updown='0')then temp<=temp+1;

else temp<=temp-1;

end if;

end process;

count<=temp;

end Behavioral;

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

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VLSI Lab III/II

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. RESULT:

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8.1. 4 Bit Sequence Detector Through Mealy and Moore State

Machines
1. AIM: Design 4 Bit Sequence Detector Through Mealy and Moore State Machines using
VHDL, simulate using ISim Simulator, Synthesize using Xilinx Synthesis Tool (XST) and
Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

4 Bit Sequence Detector Through Mealy

4. VHDL Program:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--Sequence detector for detecting the sequence "1011".

--Non overlapping type.

entity seq_det is

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port( clk : in std_logic; --clock signal

reset : in std_logic; --reset signal

seq : in std_logic; --serial bit sequence

det_vld : out std_logic --A '1' indicates the pattern "1011" is detected in the sequence.

);

end seq_det;

architecture Behavioral of seq_det is

type state_type is (A,B,C,D); --Defines the type for states in the state machine

signal state :state_type := A; --Declare the signal with the corresponding state type.

begin

process(clk)

begin

if( reset = '1' ) then --resets state and output signal when reset is asserted.

det_vld<= '0';

state <= A;

elsif( rising_edge(clk) ) then --calculates the next state based on current state and input bit.

case state is

when A => --when the current state is A.

det_vld<= '0';

if ( seq = '0' ) then

state <= A;

else

state <= B;

end if;

when B => --when the current state is B.

if ( seq = '0' ) then

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VLSI Lab III/II

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. RESULT:

4 Bit Sequence Detector Through Mealy and Moore State Machines has been designed using
VHDL, simulated using ISim Simulator, Synthesized using XST (Xilinx Synthesis Tool) and
Implemented using SPARTAM 3 XC3S400 TQ 144.Verified with expected results.

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8.2. MOORE FSM SEQUENCE DETECTOR

1. AIM: Design Moore FSM Sequence Detector using VHDL, simulate using ISim Simulator,
Synthesize using Xilinx Synthesis Tool (XST) and Implement using SPARTAN-2/ 3 FPGA.

2. COMPONENTS & TOOLS REQUIRED:

2.1 XILINX-12.3i Version,

2.2 ISim Simulator

2.3 FPGA/CPLD kit

3. THEORY:

VHDL code for Moore FSM Sequence Detector

The Moore FSM state diagram for the sequence detector is shown in the
following figure

4. VHDL Program:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity VHDL_MOORE_FSM_Sequence_Detector is

port ( clock: in std_logic; --- clock signal

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reset: in std_logic; -- reset input

sequence_in: in std_logic; -- binary sequence input

detector_out: out std_logic -- output of the VHDL sequence detector);

end VHDL_MOORE_FSM_Sequence_Detector;

architecture Behavioral of VHDL_MOORE_FSM_Sequence_Detector is

type MOORE_FSM is (Zero, One, OneZero, OneZeroZero, OneZeroZeroOne);

signal current_state, next_state: MOORE_FSM;

begin

-- Sequential memory of the VHDL MOORE FSM Sequence Detector

process(clock,reset)

begin

if(reset='1') then

current_state<= Zero;

elsif(rising_edge(clock)) then

current_state<= next_state;

end if;

end process;

-- Next state logic of the VHDL MOORE FSM Sequence Detector

-- Combinational logic

process(current_state,sequence_in)

begin

case(current_state) is

when Zero =>

if(sequence_in='1') then

-- "1"

end case;

end process;

-- Output logic of the VHDL MOORE FSM Sequence Detector

process(current_state)

begin

end process;

end Behavioral;

Dept. of ECE, SIET Page 48

VLSI Lab III/II

5. PROCEDURE:

1. Open Xilinx Project Navigator

2. Open New Project

3. Select Target Device details

4. Enter VHDL Program

5. Compile for Syntax errors

6. Simulate design using ISim Simulator

7. Verify the functionality of design with expected results and draw input and output waveforms

8. Synthesize design using XST (Xilinx Synthesis Tool)

9. Write User Constrain File to fix in/out ports on Target device Generate programming file

10. Down load design to the target device on FPGA/CPLD FPGA/CPLD demo board

11. Verify the functionality of design with expected results

6. RESULT:

Moore FSM Sequence Detector has been designed using VHDL, simulated using ISim
Simulator, Synthesized using XST (Xilinx Synthesis Tool) and Implemented using SPARTAM
3 XC3S400 TQ 144.Verified with expected results.

6) Write difference between Concurrent statements and Sequential Statements?

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1. INVERTER
Date:

Aim: To generate schematic and layout for an inverter using mentor graphics tool.

Tools Required:

1. Operating System: Windows XP

Simulation Diagram for Inverter:

Waveforms for Inverter:

Dept. of ECE, SIET Page 54

VLSI Lab III/II

Layout for inverter:

Result: Hence simulated and verified the schematic and layout of inverter using mentor
graphics tool.

Dept. of ECE, SIET Page 55

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2.1 2-INPUT NAND GATE

Date:

Aim: To generate schematic and layout for an NAND Gate using mentor graphics tool.

Tools Required:

1. Operating System: Windows XP

2. Software: Mentor Graphics Tool

Theory: Nand gate is the logic component in this if any one of the input is ‘0’ or low the
output is high ‘1’ otherwise if two inputs are equal to one then out put is low ‘0’.
It is used to perform logical operations

Truth table:

Input A Input B Output

0 0 1
0 1 1
1 0 1
1 1 0

Procedure for Schematic:

1. Click on “X-manager enterprise-3” on desktop; now click on “X-start”.

2. Enter the IP address under host as 10.0.26.133 (IP Address of the Server system).

3. Select the protocol as SSH from the dropdown.

4. Enter the username: user1 to user20

Password: vlsi123.
Under execution command select Xterm (Linux: type2) and then click on run.
5. A command prompt will open.

6. Now follow below instructions to continue to design schematic

User1@mentor server
$ cshand click enter
$ Source /home/software/cshrc/ams_2009.cshrc and click enter
$ dmgr_ic&and click on enter to enter the 130nm tech.
7. To create a new project click on File and go to new project which invoke the new project
window.

Dept. of ECE, SIET Page 56

VLSI Lab III/II

9. Beside the library browse on the folder and click on the look in icon until you reach home
then click on software/FOUNDRY/GDK/pyris_SPT_HEP/ic_reflibs/tech_libs and select
the generic13 file and click on OK.

10. Again click on OK then manage external/logic libraries window will pop up, now click
on the Add standard Libraries then the libraries will be added up and click on OK.

11. The project will be appeared on the left side of the screen,

12. Now right click on the project name and select new library then a pop up window asking
for library name is opened, provide the library name as vlsilaband click on Ok.

13. To create a schematic, right click on the library below the project name and go to new &
select schematic.

14. A window will pop up asking for the schematic name & cell name; provide the same
name for both schematic name and cell name and click on OK.

15. A pyxis schematic editor window is opened.

16. From the left icon bar press on add instance icon then double click on the generic13 and
then select the symbols.

17. In the symbols select the two pmos and two nmos and click on OK to place the pmos on
the workspace and press ESC to cancel additional one.

18. Now go to “library” → ”generic library” now select “two PORT INs, PORT OUT,
VDD, GND”.

19. Now connect all the components with wire by clicking on ’add wire’ on the left of the
window or pressing W on keyboard.

20. After completion of connections press ‘escape F2’.

21. Select and press Q to change the names and properties of components and click on OK.

23. Select pmos and press Q then change the W=width-0.52u and L=length-0.13u and click
on OK.

24. Now select nmos and press Q then change W=width-0.26u and L=length-0.13u and click
on OK.

25. Press on input port →press ’Q’→ change name as ‘a’→ press ‘ok’

Input port →press ’Q’→ change name as ‘b’→ press ‘ok’

Dept. of ECE, SIET Page 57
VLSI Lab III/II

Output port → press ‘Q’ → change name as ‘c’→ press ‘ok’

26. Click on ‘check’ and ‘save’→ we will get error report

→To close the error report window press scroll on mouse & drag
from right to left
27. Now click on Add in the tool bar and select Generate Symbol then a pop up is opened.

28.Check marks the options ‘replace existing’ & ‘activate symbol’ and click on ‘choose
symbol’ →now select a symbol as AND according to our need and then click ‘ok’. Again
click on Ok, now pyxis symbol window is opened then drag the o/p line with mouse and add
the bubble by clicking on circle on left side of window. Now move the wire towards bubble.
Right click on wire & select option ”stretch” to move.

29. Now ‘check & save’ and verify the errors and close all tabs.

30. To create a schematic for simulation, right click on the library below the project name
and go to new & select schematic.

31. A window will pop up asking for the schematic name & cell name; provide the same
name for both schematic name and cell name and click on OK.

32. A pyxis schematic editor window is opened.Right click on design sheet and go to
“instance” →” choose symbol” → select schematic name and click ‘ok’.

33. Now the desired symbol of experiment will appear.

34. Now go to library → generic library, select two ‘PORT IN’, ‘PORT OUT’, ‘VDD’,
three ‘GNDs’, and press ’back’.

35. Go to sources library → select “DC (V)” and two “PATTERNs (V)” and place them on
output side and input side respectively. Now add wires by pressing ‘w’.

36. Select the input and output ports and edit their names by pressing Q and click ‘ok’.

37. Select the DC source and press Q then change voltage to 5V and click on OK, press “
escape F2” and go for ‘check and save’ and close it.

38. Click on “simulation” → “new configuration” → edit configuration name as

“TRAN_SIM” and click ‘ok’.

39. Again click on Ok, now click on “lib/temp/inc” → include files →Analysis.

40. In Analysis remove the tick mark for OP and put a tick mark on the Tran box.

41. Mention the start time as 0n and stop time as 500n and click on Apply. Now in the left
side of window select the outputs.

42. In outputs change the analysis to TRAN from the dropdown and select the PLOT under
Task.
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VLSI Lab III/II

43. Now minimize it and select all the I/Ps and O/Ps by holding the Ctrl on keyboard.

44. Release the Ctrl and maximize the set up simulation and click on Add and click on
Apply, then close it.

45. On the Right side palette area click on Run ELDO, now check whether the simulation is
completed or not.

46. Click on “view waves”, now the output waveforms will appear on a new window.

47. Now from the top bar select tools and then select measurement tool and select delay
time, rise time, fall time, to mention on graph by selecting i/p or o/p on graph and then press
then add the waves and then click apply.

Procedure for layout:

1. To create a layout select nandcell, right click on the cell and select new layout
2. A new window named New layout will pop up, here name the layout and click Ok
3. Pyxis layout window will be invoked with a new layout sub window in it and keep the
settings and click on OK.
4. Click restore button and click on MGC --> setup and select left right tiling and click ok
5. Creating SDL:
• Make the Schematic window active by selecting it with the LMB. Select the
PMOS and press on the Pick & Place icon from SDL tool bar on the Icon bar.
The tool will place the device on the Workspace of IC layout window. Similarly
select the NMOS and place it on the workspace
• To make SDL toolbar active, go to setup->SDL
6. After adding the layouts of transistor, select any one of the net in schematic window and
click on inst and then on port, now move your cursor towards layout window and place the
ports one by one.
7. Select the layer POLYG from the layer Palette window and select Easyedit -> shape from
IC palette and connect the gates of NMOS and PMOS transistors.
8. Select the option Tools from the top row menu and select IRoute and interconnect PMOS
and NMOS transistor (press 'w' to change the width of the metal track and specify
width as 0.26).
9. Connect the output port to the metal track using Iroute
10. Create VDD Plane and GND plane using Metal-1 layer . Select metal-1 in layer palette
and choose easyedit -> shape from ic palette and draw planes and place the VDD and
GND ports in the respective planes

11. Connect the Source of PMOS transistor to VDD plane and Drain of NMOS transistor to
GND plane using Iroute (keep the width as 0.26).
12. To connect the Input port to poly layer ( poly to metal contact) we have to follow below
steps

Dept. of ECE, SIET Page 59

VLSI Lab III/II

• Extend the poly region (approx 0.5x0.5) and draw a contact to poly by selecting
CO layer on Layer palette and select easy edit and shape draw exactly 0.16x0.16
of CO layer in the extended poly region.
• Now draw metal-1 layer over the CO layer to the input port.

13. To add N-well contacts select the VDD plane in layout area, click on DLA Layout in IC
palette and click on via (right arrow) and select fill selected and select "m1nwell" in IC
device shape via window and click ok

14. To add P-well contacts select the GND plane in layout area, click on DLA Layout in IC
palette and click on via (right arrow) and select fill selected and select "m1psub" in IC
device shape via window and click ok

15. This finishes the layout for Inverter, Now select Add (from top row) and select add text
on ports and click ok. This should add the names on the I/O ports.

16. Select back in that select IC rules and check and in top of window we shown a ok tag
and click on it.
Schematic Diagram for NAND Gate:

Symbol for NAND Gate:

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Simulation Diagram for NAND Gate:

Waveforms for NAND Gate:

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Layout for NAND Gate:

Result: Hence simulated and verified the schematic and layout of NAND Gate using mentor
graphics tool.

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2.2 2-INPUTNOR GATE

Date:

Aim: To generate schematic and layout for NOR Gate using mentor graphics tool.

Tools Required:

1. Operating System: Windows XP

2. Software: Mentor Graphics Tool

Theory: NOR gate is the logic component in this if any one of the input is one the output
is low ‘0’ otherwise if two input are equal to ‘0’ then the output is high ‘1’. It is
used to perform logical operations

Truth Table:

Input A Input B Output

0 0 1
0 1 0
1 0 0
1 1 0

Procedure for Schematic:

1. Click on “X-manager enterprise-3” on desktop, now click on “X-start”.

2. Enter the IP address under host as 10.0.26.133 (IP Address of the Server system).

3. Select the protocol as SSH from the dropdown.

4. Enter the username: user1 to user20

Password: vlsi123.
Under execution command select Xterm (Linux: type2) and then click on run.
5. A command prompt will open.

6. Now follow below instructions to continue to design schematic

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10. Again click on OK then manage external/logic libraries window will pop up, now click
on the Add standard Libraries then the libraries will be added up and click on OK.

11. The project will be appeared on the left side of the screen,

13. Now right click on the project name and select new library then a pop up window asking
for library name is opened, provide the library name as vlsilaband click on Ok.

14. To create a schematic, right click on the library below the project name and go to new &
select schematic.

15. A window will pop up asking for the schematic name & cell name, provide the same
name for both schematic name and cell name and click on OK.

16. A pyxis schematic editor window is opened.

17. From the left icon bar press on add instance icon then double click on the generic13 and
then select the symbols.

18. In the symbols select the two pmos and two nmos and click on OK to place the pmos on
the workspace and press ESC to cancel additional one.

19. Now go to “library” → ”generic library” now select “two PORT INs, PORT OUT,
VDD, GND”.

20. Now connect all the components with wire by clicking on ’add wire’ on the left of the
window or pressing W on keyboard.

21. After completion of connections press ‘escape F2’.

22. Select and press Q to change the names and properties of components and click on OK.

23. Select pmos and press Q then change the W=width-0.52u and L=length-0.13u and click
on OK.

24. Now select nmos and press Q then change W=width-0.26u and L=length-0.13u and click
on OK.

25. Press on input port →press ’Q’→ change name as ‘a’→ press ‘ok’

Input port →press ’Q’→ change name as ‘b’→ press ‘ok’

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VLSI Lab III/II

Output port → press ‘Q’ → change name as ‘y’→ press ‘ok’

26. Click on ‘check’ and ‘save’→ we will get error report

→To close the error report window press scroll on mouse & drag
from right to left
27. Now click on Add in the tool bar and select Generate Symbol then a pop up is opened.

28. Tick the options ‘replace existing’ & ‘activate symbol’ and click on ‘choose symbol’
→now select a symbol as OR according to our need and then click ‘ok’. Again click on Ok,
now pyxis symbol window is opened then drag the o/p line with mouse and add the bubble
by clicking on circle on left side of window. Now move the wire towards bubble. Right click
on wire & select option ”stretch” to move.

29. Now ‘check & save’ and verify the errors and close all tabs.

30. To create a schematic for simulation, right click on the library below the project name
and go to new & select schematic.

31. A window will pop up asking for the schematic name & cell name, provide the same
name for both schematic name and cell name and click on OK.

32. A pyxis schematic editor window is opened.Right click on design sheet and go to
“instance” →” choose symbol” → select schematic name and click ‘ok’.

33. Now the desired symbol of experiment will appear.

34. Now go to library → generic library, select two ‘PORT INs’, ‘PORT OUT’, ‘VDD’,
three ‘GNDs’, and press ’back’.

35. Go to sources library → select “DC (V)” and two “PATTERN (V)” and place them on
output side and input side respectively. Now add wires by pressing ‘w’.

36. Select the input and output ports and edit their names by pressing Q and click ‘ok’.

37. Select the DC source and press Q then change voltage to 5V and click on OK, press “
escape F2” and go for ‘check and save’ and close it.

38. Click on “simulation” → “new configuration” → edit configuration name as

“TRAN_SIM” and click ‘ok’.

39. Again click on Ok, now click on “lib/temp/inc” → include files →Analysis.

40. In Analysis remove the tick mark for OP and put a tick mark on the Tran box.

41. Mention the start time as 0n and stop time as 500n and click on Apply. Now in the left
side of window select the outputs.

42 .In outputs change the analysis to TRAN from the dropdown and select the PLOT under
Task.
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43. Now minimize it and select all the I/Ps and O/Ps by holding the Ctrl on keyboard.

44. Release the Ctrl and maximize the set up simulation and click on Add and click on
Apply, then close it.

45. On the Right side palette area click on Run ELDO, now check whether the simulation is
completed or not.

46. Click on “view waves”, now the output waveforms will appear on a new window.

Procedure for Layout:

1. To create a layout select nor cell, right click on the cell and select new layout
2. A new window named New layout will pop up, here name the layout and click Ok
3. Pyxis layout window will be invoked with a new layout sub window in it and keep the
settings and click on OK.
4. Click restore button and click on MGC --> setup and select left right tiling and click ok
5. Creating SDL:
• Make the Schematic window active by selecting it with the LMB. Select the
PMOS and press on the Pick & Place icon from SDL tool bar on the Icon bar.
The tool will place the device on the Workspace of IC layout window. Similarly
select the NMOS and place it on the workspace
• To make SDL toolbar active, go to setup->SDL
6. After adding the layouts of transistor, select any one of the net in schematic window and
click on inst and then on port, now move your cursor towards layout window and place the
ports one by one.
7. Select the layer POLYG from the layer Palette window and select Easyedit -> shape from
IC palette and connect the gates of NMOS and PMOS transistors.

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15. This finishes the layout for Inverter, Now select Add (from top row) and select add text
on ports and click ok. This should add the names on the I/O ports.

16. Select back in that select IC rules and check and in top of window we shown a ok tag
and click on it.
Schematic Diagram for NOR Gate:

Symbol for NOR Gate:

Simulation Diagram for NOR Gate:

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Waveforms for NOR Gate:

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Layout for NOR Gate:

Result: Hence simulated and verified the schematic and layout of NOR Gate using mentor
graphics tool.

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3. FULL ADDER
Date:

Aim: To generate schematic for FULL ADDER using mentor graphics tool.

Tools Required:

1. Operating System: Windows XP

2. Software: Mentor Graphics Tool

Theory: A logic circuit for the addition of three one bit binary numbers at a time is known
as a full adder. The function of the circuit is to add three binary digits, producing
both sum and carry. Hence the basic difference full adder and half adder is, full
adder accepts an additional input that allows for handling input carriers. The
carry is produced with an NAND Gate

Truth Table:

Input A Input B Input C sum Carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Procedure for Schematic:

1. Click on “X-manager enterprise-3” on desktop, now click on “X-start”.

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8. Beside the project path browse on the folder and click on the look in icon until you reach
the home and click on your user number & give the project name. Now libraries have to
be added to the project.
9. Beside the library browse on the folder and click on the look in icon until you reach
home then click on software/FOUNDRY/GDK/pyris_SPT_HEP/ic_reflibs/tech_libs
and select the generic13 file and click on OK.
10. Again click on OK then manage external/logic libraries window will pop up, now click
on the Add standard Libraries then the libraries will be added up and click on OK.
11. The project will be appeared on the left side of the screen,
12. Now right click on the project name and select new library then a pop up window asking
for library name is opened, provide the library name as vlsilaband click on Ok.
13. To create a schematic, right click on the library below the project name and go to new &
select schematic.
14. A window will pop up asking for the schematic name & cell name, provide the same
name for both schematic name and cell name and click on OK.
15. A pyxis schematic editor window is opened.
16. Right click on design sheet and go to “instance” →” choose symbol” → select nand
schematic and click ‘ok’. Choose nine schematics.
17. Now go to “library” → ”generic library” now select “three PORT IN, two PORT
OUTs”.
18. Now connect all the components with wire by clicking on ’add wire’ on the left of the
window or pressing W on keyboard.
19. After completion of connections press ‘escape F2’.
20. Select and press Q to change the names and properties of components and click on OK.
21. Press on input port →press ’Q’→ change name as ‘a’→ press ‘ok’
Input port → press ‘Q’ → change name as ‘b’→ press ‘ok’
Input port → press ‘Q’ → change name as ‘c’→ press ‘ok’
Output port → press ‘Q’ → change name as ‘Sum’→ press ‘ok’
Output port → press ‘Q’ → change name as ‘carry’→ press ‘ok’
22. Click on ‘check’ and ‘save’→ we will get error report
→To close the error report window press scroll on mouse & drag
from right to left
23. Now click on Add in the tool bar and select Generate Symbol then a pop up is opened.
24. Tick the options ‘replace existing’ & ‘activate symbol’ and click on ‘choose symbol’
→now select a symbol as Full Adder according to our need and then click ‘ok’. Again
click on Ok,
25. Now ‘check & save’ and verify the errors and close all tabs.
26. To create a schematic for simulation, right click on the library below the project name
and go to new & select schematic.
27. A window will pop up asking for the schematic name & cell name, provide the same
name for both schematic name and cell name and click on OK.
28. A pyxis schematic editor window is opened.Right click on design sheet and go to
“instance” →” choose symbol” → select schematic name and click ‘ok’.

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29. Now the desired symbol of experiment will appear.

30. Now go to library → generic library, select three ‘PORT INs’, two ‘PORT OUTs’,
‘VDD’, four ‘GNDs’, and press ’back’.
31. Go to sources library → select “DC (V)” and three “PATTERNs (V)” and place them on
output side and input side respectively. Now add wires by pressing ‘w’.
32. Select the input and output ports and edit their names by pressing Q and click ‘ok’.
33. Select the DC source and press Q then change voltage to 5V and click on OK, press “
escape F2” and go for ‘check and save’ and close it.
34. Click on “simulation” → “new configuration” → edit configuration name as
“TRAN_SIM” and click ‘ok’.
35. Again click on Ok, now click on “lib/temp/inc” → include files →Analysis.
36. In Analysis remove the tick mark for OP and put a tick mark on the Tran box.
37. Mention the start time as 0n and stop time as 500n and click on Apply. Now in the left
side of window select the outputs.
38. .In outputs change the analysis to TRAN from the dropdown and select the PLOT under
Task.
39. Now minimize it and select all the I/Ps and O/Ps by holding the Ctrl on keyboard.
40. Release the Ctrl and maximize the set up simulation and click on Add and click on
Apply, then close it.
41. On the Right side palette area click on Run ELDO, now check whether the simulation is
completed or not.
42. .Click on “view waves”, now the output waveforms will appear on a new window.
43. Now from the top bar select tools and then select measurement tool and select delay
time, rise time, fall time, to mention on graph by selecting i/p or o/p on graph and then
press then add the waves and then click apply.

Schematic Diagram for Full Adder:

Symbol for Full Adder :

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Simulation Diagram for Full Adder:

Waveforms for Full Adder:

Result: Hence simulated and verified the schematic of Full Adder using mentor graphics tool.

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4. FULL SUBTRACTOR
Date:

Aim: To generate schematic for a Full Subtractor using mentor graphics tool.

Tools Required:

1. Operating System: Windows XP

2. Software: Mentor graphics tool

Theory: A logic circuit for the subtraction of three one bit binary numbers at a time is
known as a full subtractor. The function of the circuit is to subtract three binary
digits, producing both difference and borrow.

Truth Table:

Procedure for Schematic:

1. Click on “X-manager enterprise-3” on desktop, now click on “X-start”.

$ dmgr_ic&and click on enter to enter the 130nm tech.

7. To create a new project click on File and go to new project which invoke the new project
window.
8. Beside the project path browse on the folder and click on the look in icon until you reach
the home and click on your user number & give the project name. Now libraries have to
be added to the project.
9. Beside the library browse on the folder and click on the look in icon until you reach
home then click on software/FOUNDRY/GDK/pyris_SPT_HEP/ic_reflibs/tech_libs
and select the generic13 file and click on OK.
10. Again click on OK then manage external/logic libraries window will pop up, now click
on the Add standard Libraries then the libraries will be added up and click on OK.
11. The project will be appeared on the left side of the screen,
12. Now right click on the project name and select new library then a pop up window asking
for library name is opened, provide the library name as vlsilaband click on Ok.
13. To create a schematic, right click on the library below the project name and go to new &
select schematic.
14. A window will pop up asking for the schematic name & cell name, provide the same
name for both schematic name and cell name and click on OK.
15. A pyxis schematic editor window is opened.
16. Right click on design sheet and go to “instance” →” choose symbol” → select nand
schematic and click ‘ok’. Consider nine nand schematics.
17. Now go to “library” → ”generic library” now select “three PORT INs, two PORT
OUTs”.
18. Now connect all the components with wire by clicking on ’add wire’ on the left of the
window or pressing W on keyboard.
19. After completion of connections press ‘escape F2’.
20. Select and press Q to change the names and properties of components and click on OK.
21. Press on input port →press ’Q’→ change name as ‘a’→ press ‘ok’
Input port → press ‘Q’ → change name as ‘b’→ press ‘ok’
Input port → press ‘Q’ → change name as ‘c’→ press ‘ok’
Output port → press ‘Q’ → change name as ‘Difference’→ press ‘ok’
Output port → press ‘Q’ → change name as ‘Borrow’→ press ‘ok’
22. Click on ‘check’ and ‘save’→ we will get error report
→To close the error report window press scroll on mouse & drag
from right to left.
23. Now click on Add in the tool bar and select Generate Symbol then a pop up is opened.
24. Tick the options ‘replace existing’ & ‘activate symbol’ and click on ‘choose symbol’
→now select a symbol as Subtractor according to our need and then click ‘ok’. Again
click on Ok.
25. Now ‘check & save’ and verify the errors and close all tabs.
26. To create a schematic for simulation, right click on the library below the project name
and go to new & select schematic.

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27. A window will pop up asking for the schematic name & cell name, provide the same
name for both schematic name and cell name and click on OK.
28. A pyxis schematic editor window is opened.Right click on design sheet and go to
“instance” →” choose symbol” → select schematic name and click ‘ok’.
29. Now the desired symbol of experiment will appear.
30. Now go to library → generic library, select three ‘PORT INs’, two ‘PORT OUTs’,
‘VDD’, four ‘GND’, and press ’back’.
31. Go to sources library → select “DC (V)” and three “PATTERN (V)” and place them on
output side and input side respectively. Now add wires by pressing ‘w’.
32. Select the input and output ports and edit their names by pressing Q and click ‘ok’.
33. Select the DC source and press Q then change voltage to 5V and click on OK, press “
escape F2” and go for ‘check and save’ and close it.
34. Click on “simulation” → “new configuration” → edit configuration name as
“TRAN_SIM” and click ‘ok’.
35. Again click on Ok, now click on “lib/temp/inc” → include files →Analysis.
36. In Analysis remove the tick mark for OP and put a tick mark on the Tran box.
37. Mention the start time as 0n and stop time as 500n and click on Apply. Now in the left
side of window select the outputs.
38. .In outputs change the analysis to TRAN from the dropdown and select the PLOT under
Task.
39. Now minimize it and select all the I/Ps and O/Ps by holding the Ctrl on keyboard.
40. Release the Ctrl and maximize the set up simulation and click on Add and click on
Apply, then close it.
41. On the Right side palette area click on Run ELDO, now check whether the simulation is
completed or not.
42. .Click on “view waves”, now the output waveforms will appear on a new window.
43. Now from the top bar select tools and then select measurement tool and select delay
time, rise time, fall time, to mention on graph by selecting i/p or o/p on graph and then
press then add the waves and then click apply.

Schematic Diagram for Full Subtractor:

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VLSI Lab III/II

Symbol for Full Subtractor:

Simulation Diagram for Full Subtractor:

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Waveforms for Full Subtractor:

Result: Hence simulated and verified the schematic of Full Subtractor using mentor graphics
tool.

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5. DECODER
Date:

Aim: To generate schematic Decoder using mentor graphics tool.

Tools Required:

1. Operating System: Windows XP

2. Software: Mentor Graphics Tool

Theory: A decoder is a combinational logic circuit which is used to change the code into a
set of signals. It is the reverse process of an encoder. A decoder circuit takes
multiple inputs and gives multiple outputs. A decoder circuit takes binary data of
‘n’ inputs into ‘2^n’ unique output. Decoding is essential in applications like data
multiplexing, memory address decoding, and 7 segment display. The best
example of decoder circuit would be an AND-gate because when all its inputs are
“High.”, the output of this gate is “High” which is called “active High output”.
As an alternative to AND gate, the NAND gate is connected the output will be
“Low” (0) only when all its inputs are “High”. Such o/p is called “active low
output”.
Truth Table:2 to 4Decoder has two inputs namely A0, A1 and four outputs denoted by D0, D1,
D2, and D3. As you can see in the following truth table – for every input
combination, one o/p line is turned on.

Procedure for Schematic:

1. Click on “X-manager enterprise-3” on desktop; now click on “X-start”.
2. Enter the IP address under host as 10.0.26.133 (IP Address of the Server system).
3. Select the protocol as SSH from the dropdown.
4. Enter the username: user1 to user20
Password: vlsi123.
Under execution command select Xterm (Linux: type2) and then click on run.
5. A command prompt will open.
6. Now follow below instructions to continue to design schematic
User1@mentor server
$ cshand click enter

Dept. of ECE, SIET Page 79

VLSI Lab III/II

$ source /home/software/cshrc/ams_2009.cshrc and click enter

$ dmgr_ic&and click on enter to enter the 130nm tech.
7. To create a new project click on File and go to new project which invoke the new project
window.
8. Beside the project path browse on the folder and click on the look in icon until you reach
the home and click on your user number & give the project name. Now libraries have to
be added to the project.
9. Beside the library browse on the folder and click on the look in icon until you reach
home then click on software/FOUNDRY/GDK/pyris_SPT_HEP/ic_reflibs/tech_libs
and select the generic13 file and click on OK.
10. Again click on OK then manage external/logic libraries window will pop up, now click
on the Add standard Libraries then the libraries will be added up and click on OK.
11. The project will be appeared on the left side of the screen,
12. Now right click on the project name and select new library then a pop up window asking
for library name is opened, provide the library name as vlsilaband click on Ok.
13. To create a schematic, right click on the library below the project name and go to new &
select schematic.
14. A window will pop up asking for the schematic name & cell name; provide the same
name for both schematic name and cell name and click on OK.
15. A pyxis schematic editor window is opened.
16. Now go to “library” → Macro library→ select 2 input AND gate and click ‘ok’.
Consider four AND gates..
17. Now go to “library” → ”generic library” now select three PORT INs, PORT OUT,
VDD.
18. Now connect all the components with wire by clicking on ’add wire’ on the left of the
window or pressing W on keyboard.
19. After completion of connections press ‘escape F2’.
20. Select and press Q to change the names and properties of components and click on OK.
21. Press on input port →press ’Q’→ change name as ‘a0’→ press ‘ok’
Input port →press ’Q’→ change name as ‘a1’→ press ‘ok’
Output port →press ’Q’→ change name as ‘d0’→ press ‘ok’
Output port → press ‘Q’ → change name as ‘d1’→ press ‘ok’
Output port →press ’Q’→ change name as ‘d2’→ press ‘ok’
Output port → press ‘Q’ → change name as ‘d3’→ press ‘ok’

22. Click on ‘check’ and ‘save’→ we will get error report

→To close the error report window press scroll on mouse & drag
from right to left
23. Now click on Add in the tool bar and select Generate Symbol then a pop up is opened.
24. Tick the options ‘replace existing’ & ‘activate symbol’ and click on ‘choose symbol’
→now select a symbol as box according to our need and then click ‘ok’. Again click on
Ok, now pyxis symbol window is opened.
25. Now ‘check & save’ and verify the errors and close all tabs.

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VLSI Lab III/II

26. To create a schematic for simulation, right click on the library below the project name
and go to new & select schematic.
27. A window will pop up asking for the schematic name & cell name; provide the same
name for both schematic name and cell name and click on OK.
28. A pyxis schematic editor window is opened.Right click on design sheet and go to
“instance” →” choose symbol” → select schematic name and click ‘ok’.
29. Now the desired symbol of experiment will appear.
30. Now go to library → generic library, select three ‘PORT INs’, ‘PORT OUT’, ‘VDD’,
two ‘VSSs’, four ‘GNDs’, and press ’back’.
31. Go to sources library → select four “DCs (V)” and two “PATTERNs (V)” and place
them on output side and input side respectively. Now add wires by pressing ‘w’.
32. Select the input and output ports and edit their names by pressing Q and click ‘ok’.
33. Select the DC source and press Q then change voltage to 5V and click on OK, press “
escape F2” and go for ‘check and save’ and close it.
34. Click on “simulation” → “new configuration” → edit configuration name as
“TRAN_SIM” and click ‘ok’.
35. Again click on Ok, now click on “lib/temp/inc” → include files →Analysis.
36. In Analysis remove the tick mark for OP and put a tick mark on the Tran box.
37. Mention the start time as 0n and stop time as 500n and click on Apply. Now in the left
side of window select the outputs.
38. .In outputs change the analysis to TRAN from the dropdown and select the PLOT under
Task.
39. Now minimize it and select all the I/Ps and O/Ps by holding the Ctrl on keyboard.
40. Release the Ctrl and maximize the set up simulation and click on Add and click on
Apply, then close it.
41. On the Right side palette area click on Run ELDO, now check whether the simulation is
completed or not.
42. .Click on “view waves”, now the output waveforms will appear on a new window.
43. Now from the top bar select tools and then select measurement tool and select delay
time, rise time, fall time, to mention on graph by selecting i/p or o/p on graph and then
press then add the waves and then click apply

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Schematic Diagram for Decoder:

Symbol for Decoder:

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Simulation Diagram for Decoder:

Waveforms for Decoder:

Result: Hence simulated and verified the schematic of Decoder using mentor graphics tool.
Dept. of ECE, SIET Page 83
VLSI Lab III/II

7. D-FLIPFLOP
Date:

Aim: To generate schematic and layout for a D-Latch using mentor graphics tool.

Tools Required:

1. Operating System: Windows XP

2. Software: Mentor Graphics Tool

Theory: Latch is an electronic device that can be used to store one bit of information. The
D latch is used to capture, or 'latch' the logic level which is present on the Data
line when the clock input is high. If the data on the D line changes state while the
clock pulse is high, then the output, Q, follows the input, D. When the CLK input
falls to logic 0, the last state of the D input is trapped and held in the latch.

Truth Table:

CLK D Q QBAR
0 0 Q QBAR
0 1 Q QBAR
1 0 0 1
1 1 1 0
Procedure for Schematic:

1. Click on “X-manager enterprise-3” on desktop; now click on “X-start”.

10. Again click on OK then manage external/logic libraries window will pop up, now click
on the Add standard Libraries then the libraries will be added up and click on OK.
11. The project will be appeared on the left side of the screen,
12. Now right click on the project name and select new library then a pop up window asking
for library name is opened, provide the library name as vlsilaband click on Ok.
13. To create a schematic, right click on the library below the project name and go to new &
select schematic.
14. A window will pop up asking for the schematic name & cell name; provide the same
name for both schematic name and cell name and click on OK.
15. A pyxis schematic editor window is opened.
16. Right click on design sheet and go to “instance” →” choose symbol” → select nand
schematic and click ‘ok’.
17. Similarly consider 3 more nand schematics and one inverter schematic.
18. Now go to “library” → ”generic library” now select two PORT INs and two PORT
OUTs”.
19. Now connect all the components with wire by clicking on ’add wire’ on the left of the
window or pressing W on keyboard.
20. After completion of connections press ‘escape F2’.
21. Select and press Q to change the names of components and click on OK.
22. Press on input port →press ’Q’→ change name as ‘d’→ press ‘ok’
Input port →press ’Q’→ change name as ‘clk’→ press ‘ok’
Output port → press ‘Q’ → change name as ‘q’→ press ‘ok’
Output port → press ‘Q’ → change name as ‘qbar’→ press ‘ok’
23. Click on ‘check’ and ‘save’→ we will get error report
→To close the error report window press scroll on mouse & drag
from right to left
24. Now click on Add in the tool bar and select Generate Symbol then a pop up is opened.
25. Tick the options ‘replace existing’ & ‘activate symbol’ and click on ‘choose symbol’
→now select a symbol as box according to our need and then click ‘ok’.
Again click on Ok, now pyxis symbol window is opened.
26. Now ‘check & save’ and verify the errors and close all tabs.
27. To create a schematic for simulation, right click on the library below the project name
and go to new & select schematic.
28. A window will pop up asking for the schematic name & cell name; provide the same
name for both schematic name and cell name and click on OK.
29. A pyxis schematic editor window is opened.Right click on design sheet and go to
“instance” →” choose symbol” → select schematic name and click ‘ok’.
30. Now the desired symbol of experiment will appear.
31. Now go to library → generic library, select two ‘PORT IN’, two ‘PORT OUT’, ‘VDD’,
three ‘GND’, and press ’back’.
32. Go to sources library → select “DC (V)” and two “PATTERN (V)” and place them on
output side and input side respectively. Now add wires by pressing ‘w’.
33. Select the input and output ports and edit their names by pressing Q and click ‘ok’.

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34. Select the DC source and press Q then change voltage to 5V and click on OK, press “
escape F2” and go for ‘check and save’ and close it.
35. Click on “simulation” → “new configuration” → edit configuration name as
“TRAN_SIM” and click ‘ok’.
36. Again click on Ok, now click on “lib/temp/inc” → include files →Analysis.
37. In Analysis remove the tick mark for OP and put a tick mark on the Tran box.
38. Mention the start time as 0n and stop time as 500n and click on Apply. Now in the left
side of window select the outputs.
39. In outputs change the analysis to TRAN from the dropdown and select the PLOT under
Task.
40. Now minimize it and select all the I/Ps and O/Ps by holding the Ctrl on keyboard.
41. Release the Ctrl and maximize the set up simulation and click on Add and click on
Apply, then close it.
42. On the Right side palette area click on Run ELDO, now check whether the simulation is
completed or not.
43. .Click on “view waves”, now the output waveforms will appear on a new window.
44. Now from the menu bar select tools and then select measurement tool and select delay
time, rise time, fall time, to mention on graph by selecting I/P or O/P on graph and then
press then add the waves and then click apply.

Schematic Diagram for D-flipflop:

Dept. of ECE, SIET Page 86

VLSI Lab III/II

Symbol for D-flipflop:

Simulation Diagram for D-flipflop:

Waveforms for D-flipflop:

Result: Hence simulated and verified the schematic of D-flipflop using mentor graphics tool.

Dept. of ECE, SIET Page 87

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