5 4 3 2 1

X'TAL
VCORE(ISL6262A) +1.2V/+1.25V/1.5V/2.5V
14.318MHZ
ZD1(CHAPALA) SYSTEM BLOCK DIAGRAM
CLOCK GENERATOR P33 P37

SELGO: SLG8SP512K05 CPU

Merom 479
5V/3.3V (ISL6236) BATTERYCHARGER
D
P2 uFCPGA P3,P4 Thermal Sensor
P3
(ISL6251) D
P33 P32

TVOUT FSB 667/800 Mhz

DISCHARGE +1.8V / +1.05V
CRT P19
P37 P35,36
DDRII
Dual Channel DDR2 SO-DIMM 0
TFT LCD Panel VGA NB 533/667 MHz
WXGA LVDS
SO-DIMM 1
Crestline
WSXGA+ P16
WUXGA PM965
P18 PCI-Express 16X Lan
P5,P6,P7,P8,P9,P10,P11 DVI MXM-NB8P-GS USB6 USB5
LVDS ( nVidia )
HDD (SATA) X4 DMI interface VGA/TV out VRAM 256M
VRAM 512M Mini Card /
C
P24 WLAN / 3G(TV) New Card Robson C
P17
SATA0 P22 P23 P29

SATA1 PCI-Express PCIE-2 PCIE-4 PCIE-1 PCIE-5

ODD (PATA) SB
PATA
P24
ICH8M PCI Bus PCIE-6
X'TAL
USB 2.0
Bluetooth Azalia
25M
USB4 P21 P12,P13,P14,P15 X'TAL24.576MHZ

X'TAL
USB Port x 4 32.768KHZ BROADCOM
USB0~3 P25
1394
10/100/1G LAN
+Cardreader
CCD Int MIC Controller 5787M
USB7 P21 P27
P20
B
R5C832/833 B
LPC
Azalia Audio X'TAL P28
32.768K Transformer
Audio Amplifier Controller P20
P27 ALC268&888 P26 EC (WPC8769LDG)
RJ45
P31 P21
IEEE 1394 Port Media Card Reader Fan Header
P28 P28 P21,P30
MIC Jack Line in
P27 P27
SPI ROM
P31 VR
P26
Connector

Speaker Phone Jack MDC 1.5 Touch Pad

P27 P27 P26
P30 CIR
A A

P21

K/B COON.
P30
PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
Block Diagram B
Date: Friday, December 08, 2006 Sheet 1 of 38
5 4 3 2 1
 5 4 3 2 1

Clock Generator
Change list:
B-test
1.Change U31 P/N to ALPRS365K13 (ICS)
+3V +3V
+3V R205 +3V_VDD_A
BKP1608HS181-T

C347 C349 C340 C352 C362 C342 C345 C339 R435 R443
*10K_4 *10K_4
10U .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 10U

PCI_CLK_SIO PCLK_ICH
D D

R439 R207
10K_4 10K_4

+1.25V R220 +1.25V_VDD

BKP1608HS181-T
+3V_VDD_A U31
C355 C350 C375 C372 C353 C360 C359 C358

10U .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 10U 2 12 +1.25V_VDD

0_4 R206 VDD_A_48 VDD_PCI VDD_I/O
9 VDD_48 VDD_PLL3_I/O 20
16 VDD_PLL3 VDD_SRC_I/O_1 26
39 VDD_SRC VDD_SRC_I/O_2 36
55 VDD_CPU VDD_SRC_I/O_3 45
0_4 R431 VDD_A_REF 61 49
VDD_REF VDD_CPU_I/O

CPU_STOP# 37 PM_STPCPU# <14>

38 PM_STPPCI# <14> +3V R433 10K_4 PCLK_DEBUG
PCI_STOP#
CKPWRGD/PD# 56 CK_PWRGD <14>
CG_XOUT 59 54 CLK_CPU_BCLK_R RP42 1 2 0X2 MCH_BSEL0 R446 2.2K_4 CLKUSB_48
XTAL_OUT CPU_0 CLK_CPU_BCLK <3>
CG_XIN 60 53 CLK_CPU_BCLK#_R 3 4
XTAL_IN CPU_0# CLK_CPU_BCLK# <3>
<14> SATACLKREQ# R430 475_4 SATACLKREQ#_R 1 51 CLK_MCH_BCLK_R RP44 1 2 0X2
PCI_0/CLKREQ_A# CPU_1_MCH CLK_MCH_BCLK <5>
R432 33_4 PCI_CLK_7412_R 3 50 CLK_MCH_BCLK#_R 3 4 MCH_BSEL2 R424 10K_4 FSC
<28> PCLK_PCM PCI_1/CLKREQ_B# CPU_1_MCH# CLK_MCH_BCLK# <5>
R434 33_4 PCLK_MINI_R 4 47 PCIE_CLK_RBS_R RP46 1 2 0X2
<22,30> PCLK_DEBUG PCI_2 SRC_8/CPU_ITP PCIE_CLK_RBS <29>
R436 33_4 PCLK_591_R 5 46 PCIE_CLK_RBS#_R 3 4
<31> PCLK_591 PCI_3 SRC_8#/CPU_ITP# PCIE_CLK_RBS# <29>
PCI_CLK_SIO R440 33_4 PCI_CLK_SIO_R 6
R444 33_4 PCLK_ICH_R ^PCI_4/LCDCLK_SEL
<13> PCLK_ICH 7 PCIF_5/ITP_EN
C C
NC 48

R447 33_4 FSA 10

<14> CLKUSB_48 MCH_BSEL1 USB_48MHz/FS_A
57 FS_B/TEST_MODE
17 CLK_DREFSSCLK_R RP45 3 4 IV@0X2
LCDCLK/27M CLK_DREFSSCLK <7>
Clock Gen I2C
18 CLK_DREFSSCLK#_R 1 2
LCDCLK#/27M_SS CLK_DREFSSCLK# <7>
R423 33_4 FSC 62
<14> 14M_ICH REF/FS_C/TEST_SEL

RP43 4 3 IV@0X2 DREFCLK_R 13 21 CLK_PCIE_SATA_R RP47 3 4 0X2

<7> CLK_DREFCLK SRC_0/DOT_96 SRC_2 CLK_PCIE_SATA <12>
2 1 DREFCLK#_R 14 22 CLK_PCIE_SATA#_R 1 2
<7> CLK_DREFCLK# SRC_0#/DOT_96# SRC_2# CLK_PCIE_SATA# <12>
24 CLK_PCIE_LAN_R RP49 3 4 0X2
SRC_3/CLKREQ_C# CLK_PCIE_LAN <20>
CGCLK_SMB 64 25 CLK_PCIE_LAN#_R 1 2
SCL SRC_3#/CLKREQ_D# CLK_PCIE_LAN# <20>
CGDAT_SMB 63 27 CLK_PCIE_MINI1_R RP51 3 4 0X2
SDA SRC_4 CLK_PCIE_MINI1 <22>
28 CLK_PCIE_MINI1#_R 1 2 +3V
SRC_4# CLK_PCIE_MINI1# <22>
41 CLK_PCIE_ICH_R RP50 1 2 0X2
SRC_6 CLK_PCIE_ICH <13>
40 CLK_PCIE_ICH#_R 3 4
SRC_6# CLK_PCIE_ICH# <13>
44 PECLK_VGA_R RP48 1 2 EV@0X2
SRC_7/CLKREQ_F# CLK_MXM <17>
8 43 PECLK_VGA#_R 3 4
VSS_PCI SRC_7#/CLKREQ_E# CLK_MXM# <17>
11 30 CLK_PCIE_NEW_C_R RP53 3 4 0X2 Q27 R428 R429
VSS_48 SRC_9 CLK_PCIE_NEW_C <23>
15 31 CLK_PCIE_NEW_C#_R 1 2 RHU002N06
VSS_I/O SRC_9# CLK_PCIE_NEW_C# <23>

2
19 34 CLK_PCIE_3GPLL_R RP52 3 4 0X2 10K_4 10K_4
VSS_PLL3 SRC_10 CLK_PCIE_3GPLL <7>
23 35 CLK_PCIE_3GPLL#_R 1 2
VSS_SRC_1 SRC_10# CLK_PCIE_3GPLL# <7>
29 33 CLK_PCIE_TV_R RP36 3 4 0X2 3 1 CGDAT_SMB
VSS_SRC_2 SRC_11/CLKREQ_H# CLK_PCIE_TV <22> <14,16,22,23> PDAT_SMB
42 32 CLK_PCIE_TV#_R 1 2
VSS_SRC_3 SRC_11#/CLKREQ_G# CLK_PCIE_TV# <22>
C563 33P_4 CG_XIN 52 VSS_CPU
58 VSS_REF
<check list> +3V
XTAL length < 500mils Y4
14.318MHz Q28
ICS9LPRS365BGLFT RHU002N06

2
C565 33P_4 CG_XOUT Main: ICS9LPRS365BGLFT:ALPRS365K13
B B
SLG8SP512T: AL8SP512K05 3 1 CGCLK_SMB
<14,16,22,23> PCLK_SMB

CPU Clock select <3> CPU_BSEL0

R455 0_4 MCH_BSEL0
MCH_BSEL0 <7>

BSEL Frequency Select Table

+1.05V R456 *56_4
FSC FSB FSA Frequency
R450 *1K_4
0 0 0 266Mhz

R451 0_4 MCH_BSEL1 0 0 1 133Mhz

<3> CPU_BSEL1 MCH_BSEL1 <7>

0 1 1 166Mhz
R449 *0_4

A A
0 1 0 200Mhz
+1.05V R454 *1K_4

1 1 0 400Mhz
R425 0_4 MCH_BSEL2
<3> CPU_BSEL2 MCH_BSEL2 <7>
1 1 1 Reserved
PROJECT : ZD1
R427 *0_4 1 0 1 100Mhz
Quanta Computer Inc.
+1.05V R426 *1K_4 1 0 0 333Mhz Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
CLOCK GENERATOR CK505 W/REGULATOR
Monday, December 11, 2006
1
Sheet 2 of 38
B
 5 4 3 2 1

U22A
<5> H_A#[16:3]
H_A#3 J4 H1
A[3]# ADS# H_ADS# <5>
CPU(HOST) CPU Thermal monitor

ADDR GROUP 0
H_A#4 L5 E2
A[4]# BNR# H_BNR# <5>
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# <5>
H_A#6 K5
H_A#7 A[6]# +3V +3V
M3 A[7]# DEFER# H5 H_DEFER# <5>
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# <5>
H_A#9 J1 E1 Q25
A[9]# DBSY# H_DBSY# <5>

2
H_A#10 N3 RHU002N06
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ#0 <5>
H_A#12 P2 <31,32> MBCLK 3 1

CONTROL
H_A#13 A[12]#
L2 A[13]# IERR# D20 H_IERR# R79 56.2/F_4 +1.05V
H_A#14 P4 B3
A[14]# INIT# H_INIT# <12>
H_A#15 P1
H_A#16 A[15]# +3V R360 R361 R357
R1 A[16]# LOCK# H4 H_LOCK# <5>
D D
<5> H_ADSTB0# M1 ADSTB[0]#
C1 Q26 10K_4 10K_4 200
<5> H_REQ#[4:0] RESET# H_CPURST# <5>

2
H_REQ#0 K3 F3 RHU002N06 LM86VCC
REQ[0]# RS[0]# H_RS#0 <5>
H_REQ#1 H2 F4
REQ[1]# RS[1]# H_RS#1 <5>
H_REQ#2 K2 G3 <31,32> MBDATA 3 1 C517
REQ[2]# RS[2]# H_RS#2 <5>
H_REQ#3 J3 G2
REQ[3]# TRDY# H_TRDY# <5>
H_REQ#4 L1 .1U_4
REQ[4]#
<5> H_A#[35:17] HIT# G6 H_HIT# <5>
H_A#17 Y2 E4 U24
A[17]# HITM# H_HITM# <5>
H_A#18 U5 H_THERMDA
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4 T8 8 SCLK VCC 1

ADDR GROUP 1
H_A#20 W6 AD3 XDP_BPM#1
A[20]# BPM[1]# T2
H_A#21 XDP_BPM#2 C518

XDP/ITP SIGNALS
U4 A[21]# BPM[2]# AD1 T3 7 SDA DXP 2
H_A#22 Y5 AC4 XDP_BPM#3
A[22]# BPM[3]# T6
H_A#23 U1 AC2 XDP_BPM#4 6 3 2200P_4
A[23]# PRDY# T4 ALERT# DXN
H_A#24 R4 AC1 XDP_BPM#5
A[24]# PREQ# T5
H_A#25 T5 AC5 XDP_TCK <14,17> THERM_ALERT# R362 *0_4 4 5 H_THERMDC
H_A#26 A[25]# TCK XDP_TDI OVERT# GND
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO
H_A#28 A[27]# TDO XDP_TMS MAX6657
W5 A[28]# TMS AB5
H_A#29 Y4 A[29]# TRST# AB6 XDP_TRST# ADDRESS: 98H
H_A#30 U2 C20 XDP_DBRESET# R358 0_4
A[30]# DBR# SYS_RST# <14>
H_A#31 V4 +3V R363 *10K_4 CPUFAN#_ON <check list>
H_A#32 A[31]#
W3 A[32]# Layout Note:Routing 10:10 mils and away
H_A#33 AA4 THERMAL R355 56.2/F_4 +1.05V
H_A#34 AB2
A[33]# from noise source with ground gard
H_A#35 A[34]# <30> CPUFAN#_ON
AA3 A[35]# PROCHOT# D21 H_PROCHOT_R# R82 *2.2K_4
H_PROCHOT# <34>
<5> H_ADSTB1# V1 ADSTB[1]# THERMDA A24 H_THERMDA
THERMDC B25 H_THERMDC
<12> H_A20M# A6 A20M# <check list>
ICH

A5 C7 PM_THRMTRIP# Default PU 56ohm if no use.

<12> H_FERR# FERR# THERMTRIP#
<12> H_IGNNE# C4
C IGNNE# Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K C
R350 0_4 H_STPCLK_R# D5
<12> H_STPCLK# STPCLK#
<12> H_INTR C6 LINT0 H CLK
<12> H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK <2>
<12> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <2>
M4 RSVD[01]
N5 RSVD[02]
T2 RSVD[03]
V3 RSVD[04]
RESERVED

B2 RSVD[05]
C3 RSVD[06]
D2 RSVD[07]
D22 RSVD[08]
PU/PD (ITP700)
D3 RSVD[09]
F6 RSVD[10]
Thermal Trip +1.05V
Merom Ball-out Rev 1a

3
<5> H_D#[15:0] H_D#[47:32] <5> +1.05V
U22B
H_D#0 E22 Y22 H_D#32
H_D#1 D[0]# D[32]# H_D#33 Q3 R55 D4
F24 D[1]# D[33]# AB24 <7,14,34> DELAY_VR_PWRGOOD 2
H_D#2 E26 V24 H_D#34
H_D#3 D[2]# D[34]# H_D#35 FDV301N *10K_4 *BAS316
G22 D[3]# D[35]# V26
DATA GRP 0

H_D#4 F23 V23 H_D#36 XDP_TMS R44 39/F_4

H_D#5 D[4]# D[36]# H_D#37
G25 T22

1
H_D#6 D[5]# D[37]# H_D#38 +1.05V C39 *1U
E25 D[6]# D[38]# U25
H_D#7 E23 U23 H_D#39
B H_D#8 D[7]# D[39]# H_D#40 XDP_TDI R42 150/F_4 B
K24 Y25
DATA GRP 2

H_D#9 D[8]# D[40]# H_D#41

G24 D[9]# D[41]# W22
H_D#10 J24 Y23 H_D#42
H_D#11 D[10]# D[42]# H_D#43 R56
J23 D[11]# D[43]# W24
H_D#12 H22 W25 H_D#44 XDP_BPM#5 R47 *54.9/F_4
H_D#13 D[12]# D[44]# H_D#45 56.2/F_4 Q4
F26 D[13]# D[45]# AA23

2
H_D#14 K22 AA24 H_D#46 MMBT3904
H_D#15 D[14]# D[46]# H_D#47
H23 D[15]# D[47]# AB25
J26 Y26 PM_THRMTRIP# 1 3 XDP_TDO R45 54.9/F_4
<5> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <5> SYS_SHDN# <33>
<5> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <5>
<5> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <5>
<5> H_D#[31:16] H_D#[63:48] <5>
H_D#16 N22 AE24 H_D#48
D[16]# D[48]# PM_THRMTRIP# <7,12>
H_D#17 K25 AD24 H_D#49
H_D#18 D[17]# D[49]# H_D#50
P26 D[18]# D[50]# AA21
H_D#19 R23 AB22 H_D#51
H_D#20 D[19]# D[51]# H_D#52 XDP_TCK R54 27/F_4
L23 D[20]# D[52]# AB21
DATA GRP 1

H_D#21 M24 AC26 H_D#53 <CRB & Design guide>

H_D#22 D[21]# D[53]# H_D#54
L22 D[22]# D[54]# AD20 Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing
H_D#23 M23 AE22 H_D#55
H_D#24 P25
D[23]# D[55]#
AF23 H_D#56 (ZS1 default NC) XDP_TRST# R46 680/F_4
+1.05V H_D#25 D[24]# D[56]# H_D#57
P23 D[25]# D[57]# AC25
H_D#26 P22 AE21 H_D#58
DATA GRP 3

H_D#27 D[26]# D[58]# H_D#59

<Check list & CRB> T24 D[27]# D[59]# AD21 <Check list & CRB>
Layout note: Z=55 ohm H_D#28 R24 AC22 H_D#60 Layout note: L<0.5"
H_D#29 D[28]# D[60]# H_D#61
L25 AD23
H_GTLREF<0.5" H_D#30 T25
D[29]# D[61]#
AF22 H_D#62 COMP0/2 Z=27.4ohm
H_D#31 D[30]# D[62]# H_D#63 COMP1/3 Z=54.9
N25 D[31]# D[63]# AC23
R365 L26 AE25
<5> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <5>
1K/F_4 M26 AF24
<5> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <5>
<5> H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 <5> <CRB & Design guide>
A A
Layout Note:Connect from
H_GTLREF AD26 R26 COMP0 R367 27.4/F
R101 *1K_4 CPU_TEST1 C23 GTLREF
MISC
COMP[0]
U26 COMP1 R366 54.9/F_4 SB and daisy chain to CPU
R369 *1K_4 CPU_TEST2 D25 TEST1 COMP[1] COMP2 R48 27.4/F CORE VR.Not use T
TEST2 COMP[2] AA1
CPU_TEST3 C24 Y1 COMP3 R43 54.9/F_4 connect.(SB/VR/CPU/NB)
T10 TEST3 COMP[3]
CPU_TEST4 AF26
T74 TEST4
CPU_TEST5 AF1 E5
T7 TEST5 DPRSTP# ICH_DPRSTP# <7,12,34>
CPU_TEST6 A26 B5
R364
T73 TEST6 DPSLP#
DPWR# D24
H_DPSLP# <12>
H_DPWR# <5>
PROJECT : ZD1
2K/F B22 D6
<2> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD <12>
B23 D7
<2> CPU_BSEL1
<2> CPU_BSEL2 C21
BSEL[1]
BSEL[2]
SLP#
PSI# AE6
H_CPUSLP# <5>
PSI# <34>
Quanta Computer Inc.
Size Document Number Rev
Merom Ball-out Rev 1a CPU(1 of 2)/FAN/Thermal B
Date: Monday, December 11, 2006 Sheet 3 of 38
5 4 3 2 1
 5 4 3 2 1

CPU(Power)
VCC_CORE

U22D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
U22C A16 R5
VSS[005] VSS[086]
A7 VCC[001] VCC[068] AB20 <REV.NO. 0.5/REF.NO.19343> A19 VSS[006] VSS[087] R22
C43 C46 C49 C55 C59 C69 C84 C94 C102 C56 A9 AB7 A23 R25
D VCC[002] VCC[069] VSS[007] VSS[088] D
A10 AC7 AF2 T1
10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 A12
VCC[003] VCC[070]
AC9
Ivcc Max 52A B6
VSS[008] VSS[089]
T4
VCC[004] VCC[071] VSS[009] VSS[090]
A13 VCC[005] VCC[072] AC12 B8 VSS[010] VSS[091] T23
A15 VCC[006] VCC[073] AC13 Ivccp Max 6A(VCCP supply before Vcc stable) B11 VSS[011] VSS[092] T26
A17 VCC[007] VCC[074] AC15 Max 2A(VCCP supply after Vcc stable) B13 VSS[012] VSS[093] U3
A18 VCC[008] VCC[075] AC17 B16 VSS[013] VSS[094] U6
A20 VCC[009] VCC[076] AC18 B19 VSS[014] VSS[095] U21
B7 AD7 Ivcca Max 130mA B21 U24
VCC[010] VCC[077] VSS[015] VSS[096]
B9 VCC[011] VCC[078] AD9 B24 VSS[016] VSS[097] V2
B10 VCC[012] VCC[079] AD10 C5 VSS[017] VSS[098] V5
B12 VCC[013] VCC[080] AD12 C8 VSS[018] VSS[099] V22
C60 C42 C47 C53 C58 C63 C80 C90 C99 C51 B14 AD14 C11 V25
VCC[014] VCC[081] +1.05V VSS[019] VSS[100]
B15 VCC[015] VCC[082] AD15 C14 VSS[020] VSS[101] W1
10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 B17 AD17 C16 W4
VCC[016] VCC[083] VSS[021] VSS[102]
B18 VCC[017] VCC[084] AD18 C19 VSS[022] VSS[103] W23
B20 VCC[018] VCC[085] AE9 C2 VSS[023] VSS[104] W26
C9 VCC[019] VCC[086] AE10 C22 VSS[024] VSS[105] Y3
C10 VCC[020] VCC[087] AE12 C25 VSS[025] VSS[106] Y6
C12 AE13 C76 C45 C75 C81 C89 C82 D1 Y21
VCC[021] VCC[088] VSS[026] VSS[107]
C13 VCC[022] VCC[089] AE15 D4 VSS[027] VSS[108] Y24
C15 AE17 .1U .1U .1U .1U .1U .1U D8 AA2
VCC[023] VCC[090] VSS[028] VSS[109]
DESIGN GUIDE C17 VCC[024] VCC[091] AE18 D11 VSS[029] VSS[110] AA5
CHANGE FROM 22UF *20 TO 10UF *32 C18 VCC[025] VCC[092] AE20 D13 VSS[030] VSS[111] AA8
C93 C97 C91 C44 C83 C70 D9 AF9 D16 AA11
VCC[026] VCC[093] VSS[031] VSS[112]
D10 VCC[027] VCC[094] AF10 D19 VSS[032] VSS[113] AA14
10U_8 10U_8 10U_8 10U_8 10U_8 10U_8 D12 AF12 D23 AA16
VCC[028] VCC[095] VSS[033] VSS[114]
D14 VCC[029] VCC[096] AF14 D26 VSS[034] VSS[115] AA19
D15 VCC[030] VCC[097] AF15 E3 VSS[035] VSS[116] AA22
D17 VCC[031] VCC[098] AF17 E6 VSS[036] VSS[117] AA25
D18 AF18 <CRB> +1.05V E8 AB1
VCC[032] VCC[099] VSS[037] VSS[118]
E7 VCC[033] VCC[100] AF20 R for test only E11 VSS[038] VSS[119] AB4
E9 VCC[034] E14 VSS[039] VSS[120] AB8
C CPU_G21 R75 0_4 C
E10 VCC[035] VCCP[01] G21 E16 VSS[040] VSS[121] AB11
E12 V6 CPU_V6 R63 0_4 E19 AB13
VCC[036] VCCP[02] VSS[041] VSS[122]
E13 VCC[037] VCCP[03] J6 E21 VSS[042] VSS[123] AB16
C86 C77 C61 C57 C52 C48 E15 K6 + C54 E24 AB19
10U_8 VCC[038] VCCP[04] VSS[043] VSS[124]
E17 VCC[039] VCCP[05] M6 <Check list> F5 VSS[044] VSS[125] AB23
10U_8 10U_8 10U_8 10U_8 10U_8 <Part Number> E18 J21 330U_7 ESR=12m ohm F8 AB26
<Description> VCC[040] VCCP[06] VSS[045] VSS[126]
E20 VCC[041] VCCP[07] K21 F11 VSS[046] VSS[127] AC3
F7 VCC[042] VCCP[08] M21 F13 VSS[047] VSS[128] AC6
F9 VCC[043] VCCP[09] N21 F16 VSS[048] VSS[129] AC8
F10 VCC[044] VCCP[10] N6 F19 VSS[049] VSS[130] AC11
F12 VCC[045] VCCP[11] R21 F2 VSS[050] VSS[131] AC14
F14 VCC[046] VCCP[12] R6 F22 VSS[051] VSS[132] AC16
F15 VCC[047] VCCP[13] T21 F25 VSS[052] VSS[133] AC19
+ C40 + C41 + C100 F17 T6 G4 AC21
VCC[048] VCCP[14] +1.5V VSS[053] VSS[134]
F18 VCC[049] VCCP[15] V21 <CRB> G1 VSS[054] VSS[135] AC24
F20 VCC[050] VCCP[16] W21 .01U near to B26 ball G23 VSS[055] VSS[136] AD2
330U_7 *330U_7 330U_7 AA7 G26 AD5
VCC[051] +VCCA_PROC R368 0 VSS[056] VSS[137]
AA9 VCC[052] VCCA[01] B26 H3 VSS[057] VSS[138] AD8
AA10 VCC[053] VCCA[02] C26 H6 VSS[058] VSS[139] AD11
AA12 VCC[054] H21 VSS[059] VSS[140] AD13
AA13 AD6 VCC_CORE C520 C130 H24 AD16
VCC[055] VID[0] H_VID0 <34> VSS[060] VSS[141]
AA15 VCC[056] VID[1] AF5 H_VID1 <34> J2 VSS[061] VSS[142] AD19
<Check list> AA17 AE5 .01U_4 10U_8 J5 AD22
VCC[057] VID[2] H_VID2 <34> VSS[062] VSS[143]
Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20) AA18 VCC[058] VID[3] AF4 H_VID3 <34> J22 VSS[063] VSS[144] AD25
AA20 AE3 R62 J25 AE1
Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32) VCC[059] VID[4] H_VID4 <34> VSS[064] VSS[145]
AB9 VCC[060] VID[5] AF3 H_VID5 <34> K1 VSS[065] VSS[146] AE4
AC10 AE2 100/F K4 AE8
VCC[061] VID[6] H_VID6 <34> VSS[066] VSS[147]
AB10 VCC[062] K23 VSS[067] VSS[148] AE11
AB12 VCC[063] K26 VSS[068] VSS[149] AE14
AB14 VCC[064] VCCSENSE AF7 VCCSENSE <34> L3 VSS[069] VSS[150] AE16
AB15 VCC[065] L6 VSS[070] VSS[151] AE19
AB17 VCC[066] L21 VSS[071] VSS[152] AE23
B B
AB18 VCC[067] VSSSENSE AE7 VSSSENSE <34> L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
Merom Ball-out Rev 1a M5 AF6
VSS[074] VSS[155]
. <Demo board> M22 VSS[075] VSS[156] AF8
R58 Routing 27.4ohm with 50mils spacing M25 AF11
VSS[076] VSS[157]
N1 AF13
100/F PU/PD near to CPU 1" N4
VSS[077] VSS[158]
AF16
VSS[078] VSS[159]
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25

Merom Ball-out Rev 1a

.

A A

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
CPU(2 of 2)
Monday, December 11, 2006
1
Sheet 4 of 38
B
 5 4 3 2 1

NB(HOST)

D D

H_A#[35:3] <3>
U30A
<3> H_D#[63:0]
J13 H_A#3
H_D#0 H_A#_3 H_A#4
E2 H_D#_0 H_A#_4 B11
H_D#1 G2 C11 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
G7 H_D#_2 H_A#_6 M11
H_D#3 M6 C15 H_A#7
+1.05V H_D#4 H_D#_3 H_A#_7 H_A#8
H7 H_D#_4 H_A#_8 F16
H_D#5 H3 L13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
G4 H_D#_6 H_A#_10 G17
H_D#7 F3 C14 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
N8 H_D#_8 H_A#_12 K16
R376 H_D#9 H2 B13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M10 H_D#_10 H_A#_14 L16
221_4 H_D#11 N12 J17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
N9 H_D#_12 H_A#_16 B14
H_SWING H_D#13 H5 K19 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
P13 H_D#_14 H_A#_18 P15
H_D#15 K9 R17 H_A#19
R378 C530 H_D#16 H_D#_15 H_A#_19 H_A#20
<check list> M2 H_D#_16 H_A#_20 B16
0.1U close to B3 H_D#17 W10 H20 H_A#21
100_4 .1U_4 H_D#18 H_D#_17 H_A#_21 H_A#22
Y8 H_D#_18 H_A#_22 L19
H_D#19 V4 D17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
M3 H_D#_20 H_A#_24 M17
H_D#21 J1 N16 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
N5 H_D#_22 H_A#_26 J19
H_D#23 N3 B18 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
W6 H_D#_24 H_A#_28 E19
C H_D#25 H_A#29 C
W9 H_D#_25 H_A#_29 B17
H_D#26 N2 B15 H_A#30
H_D#27 H_D#_26 H_A#_30 H_A#31
Y7 H_D#_27 H_A#_31 E17
H_D#28 Y9 C18 H_A#32 H_A#[35:32] are not supported in
H_D#29 H_D#_28 H_A#_32 H_A#33
P4 H_D#_29 H_A#_33 A19 Calero Interposer
H_D#30 W3 B19 H_A#34
H_D#31 N1
H_D#_30 H_A#_34
N19 H_A#35 Crestline support 36 bit address
H_D#32 H_D#_31 H_A#_35
AD12 H_D#_32
H_D#33 AE3 G12
H_D#_33 H_ADS# H_ADS# <3>
H_D#34 AD9 H17
H_D#_34 H_ADSTB#_0 H_ADSTB0# <3>
H_D#35

HOST
AC9 H_D#_35 H_ADSTB#_1 G20 H_ADSTB1# <3>
H_D#36 AC7 C8
H_D#_36 H_BNR# H_BNR# <3>
H_D#37 AC14 E8
H_D#_37 H_BPRI# H_BPRI# <3>
H_D#38 AD11 F12
H_D#_38 H_BREQ# H_BREQ#0 <3>
H_D#39 AC11 D6
H_D#_39 H_DEFER# H_DEFER# <3>
H_D#40 AB2 C10
H_D#_40 H_DBSY# H_DBSY# <3>
H_RCOMP H_D#41 AD7 AM5
H_D#_41 HPLL_CLK CLK_MCH_BCLK <2>
H_D#42 AB1 AM7
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <2>
H_D#43 Y3 H8
H_D#_43 H_DPWR# H_DPWR# <3>
R370 <check list> H_D#44 AC6 K7
H_D#_44 H_DRDY# H_DRDY# <3>
10:20 mils(Width:Spacing) H_D#45 AE2 E4
H_D#_45 H_HIT# H_HIT# <3>
24.9_4 H_D#46 AC5 C6
H_D#_46 H_HITM# H_HITM# <3>
H_D#47 AG3 G10
H_D#_47 H_LOCK# H_LOCK# <3>
H_D#48 AJ9 B7
H_D#_48 H_TRDY# H_TRDY# <3>
H_D#49 AH8
H_D#50 H_D#_49
AJ14 H_D#_50
H_D#51 AE9
H_D#52 H_D#_51
AE11 H_D#_52 H_DINV#[3:0] <3>
H_D#53 AH12 K5 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AJ5 H_D#_54 H_DINV#_1 L2
H_D#55 AH5 AD13 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
AJ6 H_D#_56 H_DINV#_3 AE13
B H_D#57 B
AE7 H_D#_57 H_DSTBN#[3:0] <3>
H_D#58 AJ7 M7 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AJ2 H_D#_59 H_DSTBN#_1 K3
H_D#60 AE5 AD2 H_DSTBN#2
H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AJ3 H_D#_61 H_DSTBN#_3 AH11
H_D#62 AH2 H_D#_62 H_DSTBP#[3:0] <3>
H_D#63 AH13 L7 H_DSTBP#0
R111 H_D#_63 H_DSTBP#_0
K2 H_DSTBP#1
H_SCOMP H_DSTBP#_1 H_DSTBP#2
+1.05V H_DSTBP#_2 AC2
H_SWING B3 AJ10 H_DSTBP#3
54.9_4 H_RCOMP H_SWING H_DSTBP#_3
C2 H_RCOMP H_REQ#[4:0] <3>
M14 H_REQ#0
R110 H_SCOMP H_REQ#_0 H_REQ#1
W1 H_SCOMP H_REQ#_1 E13
H_SCOMP# H_SCOMP# W2 A11 H_REQ#2
H_SCOMP# H_REQ#_2 H_REQ#3
H_REQ#_3 H13
54.9_4 B6 B12 H_REQ#4
<3> H_CPURST# H_CPURST# H_REQ#_4
<3> H_CPUSLP# E5 H_CPUSLP# H_RS#[2:0] <3>
E12 H_RS#0
H_RS#_0 H_RS#1
H_RS#_1 D7
D8 H_RS#2
H_AVREF H_RS#_2
B9 H_AVREF
H_DVREF A9 H_DVREF
CRESTLINE_1p0
+1.05V

R383

1K_4
A A
H_AVREF R384 0_4 H_DVREF

R382 C153 <check list>

0.1U close to B9
2K_4 .1U_4

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
GMCH HOST(1/7) B

Date: Monday, December 11, 2006 Sheet 5 of 38

5 4 3 2 1
 5 4 3 2 1

<check list> <check list>

For EV@ For IV@
Connect to 150ohm
Connect to GND CRT R/G/B
CRT R/G/B TV A/B/C
<check list> TV A/B/C Connect to 39ohm
D D
Vcc1_5 for Calero HSYNC/VSYNC HSYNC/VSYNC
U30C +1.05_PEG
Vcc1_25/Vcc1_05 for Crestline
<18> L_BKLT_CTRL
J40 R167 EV@0_4 HSYNC1
<23> INT_LVDS_BLON L_BKLT_CTRL
H39 L_BKLT_EN PEG_COMPI N43 EXP_A_COMPX R201 24.9/F_4 R166 EV@0_4 VSYNC1
+3V R406 10K_4 E39 M43
R413 10K_4 L_CTRL_CLK PEG_COMPO
E40 L_CTRL_DATA
<18> INT_LVDS_EDIDCLK C37 L_DDC_CLK PEG_RXN[15:0] <17>
D35 J51 PEG_RXN0 R147 IV@150/F_4 INT_TV_COMP
<18> INT_LVDS_EDIDDATA L_DDC_DATA PEG_RX#_0
K40 L51 PEG_RXN1
<18> INT_LVDS_DIGON L_VDD_EN PEG_RX#_1
N47 PEG_RXN2 R145 IV@150/F_4 INT_TV_Y/G
R182 [email protected]_4 LVDS_IBG L41 PEG_RX#_2 PEG_RXN3
<check list & CRB> LVDS_IBG PEG_RX#_3 T45
For Calero : 1.5K IV&EV Dis/Enable LVDS_VBGL43 T50 PEG_RXN4 R144 IV@150/F_4 INT_TV_C/R
T45 LVDS_VBG PEG_RX#_4 PEG_RXN5
setting N41 U40
For Cresstline:2.4K N40
LVDS_VREFH PEG_RX#_5
Y44 PEG_RXN6
LVDS_VREFL PEG_RX#_6 PEG_RXN7
<18> INT_TXLCLKOUT- D46 LVDSA_CLK# PEG_RX#_7 Y40 <check list>
C45 AB51 PEG_RXN8 SDVO/PCIE/LVDS not R157 IV@150/F_4 INT_CRT_BLU
<18> INT_TXLCLKOUT+ LVDSA_CLK PEG_RX#_8
D44 W49 PEG_RXN9
<18> INT_TXUCLKOUT- LVDSB_CLK# PEG_RX#_9 implement
E42 AD44 PEG_RXN10 R148 IV@150/F_4 INT_CRT_GRN
<18> INT_TXUCLKOUT+ LVDSB_CLK PEG_RX#_10 16 lanes NC

LVDS
AD40 PEG_RXN11
PEG_RX#_11 PEG_RXN12 R155 IV@150/F_4 INT_CRT_RED
<18> INT_TXLOUT0- G51 LVDSA_DATA#_0 PEG_RX#_12 AG46
E51 AH49 PEG_RXN13
<18> INT_TXLOUT1- LVDSA_DATA#_1 PEG_RX#_13
F49 AG45 PEG_RXN14
<18> INT_TXLOUT2- LVDSA_DATA#_2 PEG_RX#_14
AG41 PEG_RXN15
PEG_RX#_15

GRAPHICS
PEG_RXP[15:0] <17>
G50 J50 PEG_RXP0
<18> INT_TXLOUT0+ LVDSA_DATA_0 PEG_RX_0
E50 L50 PEG_RXP1
<18> INT_TXLOUT1+ LVDSA_DATA_1 PEG_RX_1
F48 M47 PEG_RXP2
<18> INT_TXLOUT2+ LVDSA_DATA_2 PEG_RX_2
U44 PEG_RXP3
PEG_RX_3 PEG_RXP4
PEG_RX_4 T49
G44 T41 PEG_RXP5
<18> INT_TXUOUT0- LVDSB_DATA#_0 PEG_RX_5
B47 W45 PEG_RXP6
C <18> INT_TXUOUT1- LVDSB_DATA#_1 PEG_RX_6 C
B45 W41 PEG_RXP7
<18> INT_TXUOUT2- LVDSB_DATA#_2 PEG_RX_7
AB50 PEG_RXP8
PEG_RX_8 PEG_RXP9
PEG_RX_9 Y48
E44 AC45 PEG_RXP10
<18> INT_TXUOUT0+ LVDSB_DATA_0 PEG_RX_10
A47 AC41 PEG_RXP11
<18> INT_TXUOUT1+ LVDSB_DATA_1 PEG_RX_11 PEG_TXN[15:0] <17> PEG_TXP[15:0] <17>
A45 AH47 PEG_RXP12
<18> INT_TXUOUT2+ LVDSB_DATA_2 PEG_RX_12
AG49 PEG_RXP13

PCI-EXPRESS
PEG_RX_13 PEG_RXP14 PEG_TXN0 PEG_TXP0
PEG_RX_14 AH45
AG42 PEG_RXP15 PEG_TXN1 PEG_TXP1
PEG_RX_15 PEG_TXN2 PEG_TXP2
INT_TV_COMP E27 N45 C_PEG_TXN0 C305 [email protected]_4 PEG_TXN0 PEG_TXN3 PEG_TXP3
<19> INT_TV_COMP TVA_DAC PEG_TX#_0
INT_TV_Y/G G27 U39 C_PEG_TXN1 C300 [email protected]_4 PEG_TXN1 PEG_TXN4 PEG_TXP4
<19> INT_TV_Y/G TVB_DAC PEG_TX#_1
INT_TV_C/R K27 U47 C_PEG_TXN2 C309 [email protected]_4 PEG_TXN2 PEG_TXN5 PEG_TXP5
<19> INT_TV_C/R TVC_DAC PEG_TX#_2

TV
PEG_TX#_3 N51 C_PEG_TXN3 C307 [email protected]_4 PEG_TXN3 PEG_TXN6 PEG_TXP6
F27 TVA_RTN PEG_TX#_4 R50 C_PEG_TXN4 C308 [email protected]_4 PEG_TXN4 PEG_TXN7 PEG_TXP7
J27 TVB_RTN PEG_TX#_5 T42 C_PEG_TXN5 C301 [email protected]_4 PEG_TXN5 PEG_TXN8 PEG_TXP8
L27 TVC_RTN PEG_TX#_6 Y43 C_PEG_TXN6 C316 [email protected]_4 PEG_TXN6 PEG_TXN9 PEG_TXP9
PEG_TX#_7 W46 C_PEG_TXN7 C331 [email protected]_4 PEG_TXN7 PEG_TXN10 PEG_TXP10
+3V R151 *2.2K_4 TV_DCONSEL_0 M35 W38 C_PEG_TXN8 C320 [email protected]_4 PEG_TXN8 PEG_TXN11 PEG_TXP11
R200 *2.2K_4 TV_DCONSEL_1 P33 TV_DCONSEL_0 PEG_TX#_8
TV_DCONSEL_1 PEG_TX#_9 AD39 C_PEG_TXN9 C311 [email protected]_4 PEG_TXN9 PEG_TXN12 PEG_TXP12
PEG_TX#_10 AC46 C_PEG_TXN10 C326 [email protected]_4 PEG_TXN10 PEG_TXN13 PEG_TXP13
<FAE> PEG_TX#_11 AC49 C_PEG_TXN11 C313 [email protected]_4 PEG_TXN11 PEG_TXN14 PEG_TXP14
If no use can be NC PEG_TX#_12 AC42 C_PEG_TXN12 C322 [email protected]_4 PEG_TXN12 PEG_TXN15 PEG_TXP15
PEG_TX#_13 AH39 C_PEG_TXN13 C318 [email protected]_4 PEG_TXN13
PEG_TX#_14 AE49 C_PEG_TXN14 C315 [email protected]_4 PEG_TXN14
PEG_TX#_15 AH44 C_PEG_TXN15 C329 [email protected]_4 PEG_TXN15

INT_CRT_BLU H32 M45 C_PEG_TXP0 C303 [email protected]_4 PEG_TXP0

<19> INT_CRT_BLU CRT_BLUE PEG_TX_0
G32 CRT_BLUE# PEG_TX_1 T38 C_PEG_TXP1 C299 [email protected]_4 PEG_TXP1
INT_CRT_GRN K29 T46 C_PEG_TXP2 C306 [email protected]_4 PEG_TXP2
<19> INT_CRT_GRN CRT_GREEN PEG_TX_2
J29 CRT_GREEN# PEG_TX_3 N50 C_PEG_TXP3 C304 [email protected]_4 PEG_TXP3
INT_CRT_RED F29 R51 C_PEG_TXP4 C310 [email protected]_4 PEG_TXP4
<19> INT_CRT_RED CRT_RED PEG_TX_4
VGA

B B
E29 CRT_RED# PEG_TX_5 U43 C_PEG_TXP5 C302 [email protected]_4 PEG_TXP5
PEG_TX_6 W42 C_PEG_TXP6 C317 [email protected]_4 PEG_TXP6
PEG_TX_7 Y47 C_PEG_TXP7 C325 [email protected]_4 PEG_TXP7
<19> INT_CRT_DDCCLK K33 CRT_DDC_CLK PEG_TX_8 Y39 C_PEG_TXP8 C321 [email protected]_4 PEG_TXP8
IV&EV Dis/Enable setting <19> INT_CRT_DDCDAT G35 CRT_DDC_DATA PEG_TX_9 AC38 C_PEG_TXP9 C312 [email protected]_4 PEG_TXP9
R169 IV@39_4 HSYNC1 F33 AD47 C_PEG_TXP10 C327 [email protected]_4 PEG_TXP10
<19> INT_HSYNC CRT_HSYNC PEG_TX_10
<check list & CRB> R397 [email protected]/F CRTIREF C32 AC50 C_PEG_TXP11 C324 [email protected]_4 PEG_TXP11
R405 IV@39_4 VSYNC1 E33 CRT_TVO_IREF PEG_TX_11
For Calero : 255 <19> INT_VSYNC CRT_VSYNC PEG_TX_12 AD43 C_PEG_TXP12 C323 [email protected]_4 PEG_TXP12
AG39 C_PEG_TXP13 C319 [email protected]_4 PEG_TXP13
For Cresstline:1.3K/F <FAE> <check list> PEG_TX_13
AE50 C_PEG_TXP14 C314 [email protected]_4 PEG_TXP14
For external VGA:0 ohm Flexible and safe HSYNC/VSYNC PEG_TX_14
AH43 C_PEG_TXP15 C328 [email protected]_4 PEG_TXP15
PEG_TX_15
serial R
place close IV&EV Dis/Enable setting
to NB CRESTLINE_1p0

TV_DCONSEL_0 R513 EV@0_4

TV_DCONSEL_1 R514 EV@0_4

A A

INTEL FAE reuqest PD.

<OrgName>

<OrgAddr1>
<OrgAddr2> PROJECT : ZD1
<OrgAddr3>
<OrgAddr4>
Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
GMCH GRAPHICS(2/7)
Monday, December 11, 2006
1
Sheet 6 of 38
B
 5 4 3 2 1

Strapping table U30B

All strap are sampled with respect to the leading edge of the GMCH power ok signal P36 RSVD1
CFG[17:3] have internal pull-up P37 RSVD2 SM_CK_0 AV29 M_CLK0 <16>
CFG[18:19] have internal pull-down R35 RSVD3 SM_CK_1 BB23 M_CLK1 <16>
Any CFG signal strapping option not list below should be left NC pin N35 RSVD4 SM_CK_3 BA25 M_CLK2 <16>
AR12 RSVD5 SM_CK_4 AV23 M_CLK3 <16>
Pin Name Strap Description Configuration AR13 RSVD6
CFG[2:0] FSB Frequency Select 010 = FSB 800MHz AM12 RSVD7 SM_CK#_0 AW30 M_CLK#0 <16>
011 = FSB 667MHz AN13 RSVD8 SM_CK#_1 BA23 M_CLK#1 <16>

MUXING
CFG[4:3] Reserved J12 RSVD9 SM_CK#_3 AW25 M_CLK#2 <16>

RSVD
CFG5 DMI X2 Select 0 = DMI X2 AR37 RSVD10 SM_CK#_4 AW23 M_CLK#3 <16>
D D
1 = DMI X4 (Default) AM36 RSVD11
CFG6 Reserved AL36 RSVD12 SM_CKE_0 BE29 M_CKE0 <16>
CFG7 CPU Strap 0 = Reserved AM37 RSVD13 SM_CKE_1 AY32 M_CKE1 <16>
1 = Mobile CPU (Default) INTEL CRB C165 .1U_4 D20 BD39
RSVD14 SM_CKE_3 M_CKE2 <16>
CFG8 Low Power PCI Express 0 = Normal mode ADD 0.1UF SM_CKE_4 BG37 M_CKE3 <16>
1 = Low Power mode
CFG9 PCI Express Graphics 0 = Reserved Lanes SM_CS#_0 BG20 M_CS#0 <16>
Lane Reversal 1 = Normal operation (Default) SM_CS#_1 BK16 M_CS#1 <16>
CFG[11:10] Reserved

DDR
SM_CS#_2 BG16 M_CS#2 <16>
CFG[13:12] XOR/ ALLZ/ 00 = Clock gating disable H10 RSVD20 SM_CS#_3 BE13 M_CS#3 <16>
Clock Un gating 01 = ALL-Z Mode Enable B51 RSVD21
10 = XOR Mode Enable BJ20 RSVD22 SM_ODT_0 BH18 M_ODT0 <16>
11 = Normal Cperation (Default) BK22 RSVD23 SM_ODT_1 BJ15 M_ODT1 <16>
CFG[15:14] Reserved BF19 RSVD24 SM_ODT_2 BJ14 M_ODT2 <16>
CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable BH20 RSVD25 SM_ODT_3 BE16 M_ODT3 <16>
1 = Dynamic ODT Enable (Default) BK18 RSVD26
CFG[18:17] Reserved BJ18 BL15 M_RCOMP
RSVD27 SM_RCOMP M_RCOMP#
CFG19 DMI Lane Reversal 0 = Normal operation BF23 RSVD28 SM_RCOMP# BK14
1 = Reverse Lanes (Default) BG23 RSVD29
CFG20 SDVO/PCIe concurrent 0 = Only SDVO or PCIE x1 is operation BC23 BK31 SM_RCOMP_VOH
RSVD30 SM_RCOMP_VOH SM_RCOMP_VOL
(Default) BD24 RSVD31 SM_RCOMP_VOL BL31
1 = SDVO and PCIE x1 are operating
simultaneously via the PEG port AR49 +SM_VREF_MCH
SM_VREF_0
SDVO_CTRLDATA SDVO Present 0 = No SDVO Card present (Default) BH39 RSVD32 SM_VREF_1 AW4
1 = SDVO Card Present AW20 RSVD33
BK20 RSVD34
C48 RSVD35
D47 B42 DREFCLK
RSVD36 DPLL_REF_CLK CLK_DREFCLK <2>
B44 C42 DREFCLK#
RSVD37 DPLL_REF_CLK# CLK_DREFCLK# <2>
INTEL CRB C44 H48 DREFSSCLK
RSVD38 DPLL_REF_SSCLK CLK_DREFSSCLK <2>

CLK
CRESSTLINE SHOULD USE 20OHM A35 H47 DREFSSCLK#
RSVD39 DPLL_REF_SSCLK# CLK_DREFSSCLK# <2>
B37 RSVD40
C CLK_PCIE_3GPLL C
B36 RSVD41 PEG_CLK K44 CLK_PCIE_3GPLL <2>
B34 K45 CLK_PCIE_3GPLL#
RSVD42 PEG_CLK# CLK_PCIE_3GPLL# <2>
C34 RSVD43
M_RCOMP# +1.8VSUS
DMI_TXN[3:0] <13>
<check list & CRB> AN47 DMI_TXN0
R387 <FAE> DMI_RXN_0 DMI_TXN1
R Value select DMI_RXN_1 AJ38
80.6ohm R388 AN42 DMI_TXN2
For Calero : 80.6ohm 20/F_4 DMI_RXN_2 DMI_TXN3
DMI_RXN_3 AN46 DMI_TXP[3:0] <13>
For Cresstline:20ohm 20/F_4
AM47 DMI_TXP0
But check list use 80.6ohm M_RCOMP P27
DMI_RXP_0
AJ39 DMI_TXP1
<2> MCH_BSEL0 CFG_0 DMI_RXP_1
N27 AN41 DMI_TXP2

DMI
<2> MCH_BSEL1 CFG_1 DMI_RXP_2
N24 AN45 DMI_TXP3
<2> MCH_BSEL2 CFG_2 DMI_RXP_3 DMI_RXN[3:0] <13>
MCH_CFG_3 C21
T30 CFG_3
MCH_CFG_4 C23 AJ46 DMI_RXN0
T75 CFG_4 DMI_TXN_0
MCH_CFG_5 F23 AJ41 DMI_RXN1
MCH_CFG_6 CFG_5 DMI_TXN_1
T34 N23 CFG_6 DMI_TXN_2 AM40 DMI_RXN2
MCH_CFG_7 G23 AM44 DMI_RXN3
T24 CFG_7 DMI_TXN_3 DMI_RXP[3:0] <13>

CFG
MCH_CFG_8 J20
+3V T29 CFG_8
DREFSSCLK R411 [email protected]_4 +1.25V MCH_CFG_9 C20 AJ47 DMI_RXP0
DREFSSCLK# R410 [email protected]_4 MCH_CFG_10 CFG_9 DMI_TXP_0
T37 R24 CFG_10 DMI_TXP_1 AJ42 DMI_RXP1
<FAE> MCH_CFG_11 L23 AM39 DMI_RXP2
T28 CFG_11 DMI_TXP_2
If no use DREFCLK PU and DREFCLK# PD MCH_CFG_12 J23 AM43 DMI_RXP3
R170 10K_4 CLK_MCH_OE# MCH_CFG_13 CFG_12 DMI_TXP_3
E23 CFG_13
IV&EV Dis/Enable setting MCH_CFG_14 E20
T25 CFG_14
R395 10K_4 PM_EXTTS#0 MCH_CFG_15 K23
T27 CFG_15
MCH_CFG_16 M20 CFG_16

GRAPHICS VID
R149 10K_4 PM_EXTTS#1 DREFCLK R409 [email protected]_4 +1.25V MCH_CFG_17 M24
T32 CFG_17
DREFCLK# R408 [email protected]_4 MCH_CFG_18 L32
T40 CFG_18
MCH_CFG_19 N33
MCH_CFG_20 CFG_19
<design guide> L35 CFG_20
B B
If no use DREFCLK PU and DREFCLK# PD
E35 MCH_GFX_VID_0
GFX_VID_0 T41
<14> PM_BMBUSY# R184 0_4 PM_BMBUSY#_R G41 A39 MCH_GFX_VID_1
PM_BM_BUSY# GFX_VID_1 T42
<3,12,34> ICH_DPRSTP# R177 0_4 ICH_DPRSTP#_R L39 C38 MCH_GFX_VID_2
PM_DPRSTP# GFX_VID_2 T43
<16> PM_EXTTS#0 R401 0_4 PM_EXTTS#0_R L36 B39 MCH_GFX_VID_3
PM_EXT_TS#_0 GFX_VID_3 T44

PM
<16> PM_EXTTS#1 R150 0_4 PM_EXTTS#1_R J36 E36 R183 *0_4
+3V PM_EXT_TS#_1 GFX_VR_EN SUSB# <14,31>
MCH_CFG_5 R138 *4.02K/F_4 AW49
<3,14,34> DELAY_VR_PWRGOOD PWROK
R140 100_4 RST_IN#_MCH AV20
<13> PLTRST#_NB RSTIN# +1.25V
MCH_CFG_9 R127 *4.02K/F_4 <3,12> PM_THRMTRIP# R130 *0_4 PM_THRMTRIP#_GMCH N20
R407 0_4 PM_DPRSLPVR_GMCH THERMTRIP#
<14,34> PM_DPRSLPVR G36 DPRSLPVR
MCH_CFG_12 R139 *4.02K/F_4
AM49 R422
CL_CLK CL_CLK0 <14>
MCH_CFG_13 R137 *4.02K/F_4 MCH_CFG_19 R171 *4.02K/F_4 AK50
CL_DATA CL_DATA0 <14>
BJ51 AT43 1K/F_4
NC_1 CL_PWROK MPWROK <14,31>
MCH_CFG_16 R129 *4.02K/F_4 MCH_CFG_20 R174 *4.02K/F_4 BK51 AN49
NC_2 CL_RST# CL_RST#0 <14>

ME
BK50 NC_3 CL_VREF AM50 +1.25V_CL_VREF
BL50 NC_4
BL49 NC_5
BL3 C559 R420
NC_6
BL2 NC_7

NC
BK1 .1U_4 392/F
NC_8
BJ1 NC_9 SDVO_CTRL_CLK H35
E1 NC_10 SDVO_CTRL_DATA K36

MISC
A5 NC_11 CLK_REQ# G39 CLK_MCH_OE#
C51 NC_12 ICH_SYNC# G40 MCH_ICH_SYNC# <14>
+SMDDR_VREF B50 NC_13
A50 NC_14
+1.8VSUS R154 1K/F_4 SM_RCOMP_VOH A49 A37 GMCH_TEST1 R178 0_4
+1.8VSUS NC_15 TEST_1
BK2 NC_16 TEST_2 R32 GMCH_TEST2 R168 20K_4

R416 R417 R165 C241 C232 CRESTLINE_1p0

A A
BK1608LL121
*1K/F_4 3.01K/F_4 .01U_4 2.2U

+SM_VREF_MCH SM_RCOMP_VOL
DREFCLK R529 EV@0_4
R418 C295 C143 DREFCLK# R531 EV@0_4
DREFSSCLK R532 EV@0_4
*1K/F_4 .1U_4 .1U_4 R163 C250 C233 DREFSSCLK# R533 EV@0_4 INTEL FAE suggest PD for external graphics PROJECT : ZD1
1K/F_4 .01U_4 2.2U
Quanta Computer Inc.
Size Document Number Rev
GMCH (STRAPPING/OTHER 3/7) B
Date: Monday, December 11, 2006 Sheet 7 of 38
5 4 3 2 1
 5 4 3 2 1

NB(Memory controller)

D D

<16> M_A_DQ[63:0] <16> M_B_DQ[63:0]

U30D U30E
M_A_DQ0 AR43 BB19 M_B_DQ0 AP49 AY17
SA_DQ_0 SA_BS_0 M_A_BS0 <16> SB_DQ_0 SB_BS_0 M_B_BS0 <16>
M_A_DQ1 AW44 BK19 M_B_DQ1 AR51 BG18
SA_DQ_1 SA_BS_1 M_A_BS1 <16> SB_DQ_1 SB_BS_1 M_B_BS1 <16>
M_A_DQ2 BA45 BF29 M_B_DQ2 AW50 BG36
SA_DQ_2 SA_BS_2 M_A_BS2 <16> SB_DQ_2 SB_BS_2 M_B_BS2 <16>
M_A_DQ3 AY46 M_B_DQ3 AW51
SA_DQ_3 M_A_CAS# <16> SB_DQ_3 M_B_CAS# <16>
M_A_DQ4 AR41 BL17 M_B_DQ4 AN51 BE17
M_A_DQ5 SA_DQ_4 SA_CAS# M_B_DQ5 SB_DQ_4 SB_CAS#
AR45 SA_DQ_5 M_A_DM[7:0] <16> AN50 SB_DQ_5 M_B_DM[7:0] <16>
M_A_DQ6 AT42 AT45 M_A_DM0 M_B_DQ6 AV50 AR50 M_B_DM0
M_A_DQ7 SA_DQ_6 SA_DM_0 M_A_DM1 M_B_DQ7 SB_DQ_6 SB_DM_0 M_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
M_A_DQ8 BB45 BD42 M_A_DM2 M_B_DQ8 BA50 BK45 M_B_DM2
C M_A_DQ9 SA_DQ_8 SA_DM_2 M_A_DM3 M_B_DQ9 SB_DQ_8 SB_DM_2 M_B_DM3 C
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
M_A_DQ10 BG47 AW13 M_A_DM4 M_B_DQ10 BA49 BH12 M_B_DM4
M_A_DQ11 SA_DQ_10 SA_DM_4 M_A_DM5 M_B_DQ11 SB_DQ_10 SB_DM_4 M_B_DM5
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
M_A_DQ12 BB47 AY5 M_A_DM6 M_B_DQ12 BA51 BF3 M_B_DM6
M_A_DQ13 SA_DQ_12 SA_DM_6 M_A_DM7 M_B_DQ13 SB_DQ_12 SB_DM_6 M_B_DM7
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
M_A_DQ14 BH49 M_B_DQ14 BF50
SA_DQ_14 M_A_DQS[7:0] <16> SB_DQ_14 M_B_DQS[7:0] <16>
M_A_DQ15 BE45 AT46 M_A_DQS0 M_B_DQ15 BF49 AT50 M_B_DQS0
M_A_DQ16 SA_DQ_15 SA_DQS_0 M_A_DQS1 M_B_DQ16 SB_DQ_15 SB_DQS_0 M_B_DQS1
AW43 BE48 BJ50 BD50
A

SA_DQ_16 SA_DQS_1 SB_DQ_16 SB_DQS_1

B
M_A_DQ17 BE44 BB43 M_A_DQS2 M_B_DQ17 BJ44 BK46 M_B_DQS2
M_A_DQ18 SA_DQ_17 SA_DQS_2 M_A_DQS3 M_B_DQ18 SB_DQ_17 SB_DQS_2 M_B_DQS3
BG42 SA_DQ_18 SA_DQS_3 BC37 BJ43 SB_DQ_18 SB_DQS_3 BK39
M_A_DQ19 BE40 BB16 M_A_DQS4 M_B_DQ19 BL43 BJ12 M_B_DQS4
M_A_DQ20 SA_DQ_19 SA_DQS_4 M_A_DQS5 M_B_DQ20 SB_DQ_19 SB_DQS_4 M_B_DQS5
BF44 SA_DQ_20 SA_DQS_5 BH6 BK47 SB_DQ_20 SB_DQS_5 BL7
M_A_DQ21 M_A_DQS6 M_B_DQ21 M_B_DQS6
MEMORY

BH45 BB2 BK49 BE2

MEMORY
M_A_DQ22 SA_DQ_21 SA_DQS_6 M_A_DQS7 M_B_DQ22 SB_DQ_21 SB_DQS_6 M_B_DQS7
BG40 SA_DQ_22 SA_DQS_7 AP3 M_A_DQS#[7:0] <16> BK43 SB_DQ_22 SB_DQS_7 AV2 M_B_DQS#[7:0] <16>
M_A_DQ23 BF40 AT47 M_A_DQS#0 M_B_DQ23 BK42 AU50 M_B_DQS#0
M_A_DQ24 SA_DQ_23 SA_DQS#_0 M_A_DQS#1 M_B_DQ24 SB_DQ_23 SB_DQS#_0 M_B_DQS#1
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50
M_A_DQ25 AW40 BC41 M_A_DQS#2 M_B_DQ25 BL41 BL45 M_B_DQS#2
M_A_DQ26 SA_DQ_25 SA_DQS#_2 M_A_DQS#3 M_B_DQ26 SB_DQ_25 SB_DQS#_2 M_B_DQS#3
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
M_A_DQ27 AW36 BA16 M_A_DQS#4 M_B_DQ27 BJ36 BK12 M_B_DQS#4
M_A_DQ28 SA_DQ_27 SA_DQS#_4 M_A_DQS#5 M_B_DQ28 SB_DQ_27 SB_DQS#_4 M_B_DQS#5
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
M_A_DQ29 AY41 BC1 M_A_DQS#6 M_B_DQ29 BJ40 BF2 M_B_DQS#6
M_A_DQ30 SA_DQ_29 SA_DQS#_6 M_A_DQS#7 M_B_DQ30 SB_DQ_29 SB_DQS#_6 M_B_DQS#7
AV38 SA_DQ_30 SA_DQS#_7 AP2 BL35 SB_DQ_30 SB_DQS#_7 AV3
M_A_DQ31 AT38 M_B_DQ31 BK37
SA_DQ_31 M_A_A[13:0] <16> SB_DQ_31 M_B_A[13:0] <16>
M_A_DQ32 AV13 BJ19 M_A_A0 M_B_DQ32 BK13 BC18 M_B_A0
M_A_DQ33 SA_DQ_32 SA_MA_0 M_A_A1 M_B_DQ33 SB_DQ_32 SB_MA_0 M_B_A1
AT13 SA_DQ_33 SA_MA_1 BD20 BE11 SB_DQ_33 SB_MA_1 BG28
SYSTEM

M_A_DQ34 AW11 BK27 M_A_A2 M_B_DQ34 BK11 BG25 M_B_A2

SYSTEM
M_A_DQ35 SA_DQ_34 SA_MA_2 M_A_A3 M_B_DQ35 SB_DQ_34 SB_MA_2 M_B_A3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
M_A_DQ36 AU15 BL24 M_A_A4 M_B_DQ36 BC13 BF25 M_B_A4
M_A_DQ37 SA_DQ_36 SA_MA_4 M_A_A5 M_B_DQ37 SB_DQ_36 SB_MA_4 M_B_A5
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
M_A_DQ38 BA13 BJ27 M_A_A6 M_B_DQ38 BC12 BA29 M_B_A6
M_A_DQ39 SA_DQ_38 SA_MA_6 M_A_A7 M_B_DQ39 SB_DQ_38 SB_MA_6 M_B_A7
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
M_A_DQ40 BE10 BL28 M_A_A8 M_B_DQ40 BJ10 AY28 M_B_A8
B M_A_DQ41 SA_DQ_40 SA_MA_8 M_A_A9 M_B_DQ41 SB_DQ_40 SB_MA_8 M_B_A9 B
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
M_A_DQ42 BD8 BC19 M_A_A10 M_B_DQ42 BK5 BG17 M_B_A10
M_A_DQ43 SA_DQ_42 SA_MA_10 M_A_A11 M_B_DQ43 SB_DQ_42 SB_MA_10 M_B_A11
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
M_A_DQ44 BG10 BG30 M_A_A12 M_B_DQ44 BK9 BA39 M_B_A12
M_A_DQ45 SA_DQ_44 SA_MA_12 M_A_A13 M_B_DQ45 SB_DQ_44 SB_MA_12 M_B_A13
AW9 SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
M_A_DQ46 BD7 BJ29 M_A_A14 M_B_DQ46 BJ8 BE24 M_B_A14
DDR

SA_DQ_46 SA_MA_14 M_A_A14 <16> SB_DQ_46 SB_MA_14 M_B_A14 <16>

M_A_DQ47 BB9 M_B_DQ47 BJ6 AV16

DDR
SA_DQ_47 SB_DQ_47 SB_RAS# M_B_RAS# <16>
M_A_DQ48 BB5 BE18 M_B_DQ48 BF4 AY18 TP_SB_RCVEN#
SA_DQ_48 SA_RAS# M_A_RAS# <16> SB_DQ_48 SB_RCVEN# T26
M_A_DQ49 AY7 AY20 TP_SA_RCVEN# M_B_DQ49 BH5
SA_DQ_49 SA_RCVEN# T35 SB_DQ_49
M_A_DQ50 AT5 M_B_DQ50 BG1 BC17
SA_DQ_50 SB_DQ_50 SB_WE# M_B_WE# <16>
M_A_DQ51 AT7 BA19 M_B_DQ51 BC2
SA_DQ_51 SA_WE# M_A_WE# <16> SB_DQ_51
M_A_DQ52 AY6 M_B_DQ52 BK3
M_A_DQ53 SA_DQ_52 M_B_DQ53 SB_DQ_52
BB7 SA_DQ_53 BE4 SB_DQ_53
M_A_DQ54 AR5 M_B_DQ54 BD3
M_A_DQ55 SA_DQ_54 M_B_DQ55 SB_DQ_54
AR8 SA_DQ_55 BJ2 SB_DQ_55
M_A_DQ56 AR9 M_B_DQ56 BA3
M_A_DQ57 SA_DQ_56 M_B_DQ57 SB_DQ_56
AN3 SA_DQ_57 BB3 SB_DQ_57
M_A_DQ58 AM8 M_B_DQ58 AR1
M_A_DQ59 SA_DQ_58 M_B_DQ59 SB_DQ_58
AN10 SA_DQ_59 AT3 SB_DQ_59
M_A_DQ60 AT9 M_B_DQ60 AY2
M_A_DQ61 SA_DQ_60 M_B_DQ61 SB_DQ_60
AN9 SA_DQ_61 AY3 SB_DQ_61
M_A_DQ62 AM9 M_B_DQ62 AU2
M_A_DQ63 SA_DQ_62 M_B_DQ63 SB_DQ_62
AN11 SA_DQ_63 AT2 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0

A A

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
GMCH DDR(4/7)
Monday, December 11, 2006
1
Sheet 8 of 38
B
 5 4 3 2 1

NB(Power-1)
+1.05V
+1.05V_AXG
U30G

AT35 U30F
VCC_1
AT34 VCC_2 VCC_AXG_NCTF_1 T17
AH28 VCC_3 VCC_AXG_NCTF_2 T18 +1.05V AB33 VCC_NCTF_1
D D
AC32 VCC_5 VCC_AXG_NCTF_3 T19 AB36 VCC_NCTF_2
AC31 VCC_4 VCC_AXG_NCTF_4 T21 AB37 VCC_NCTF_3
AK32 T22 C238 C252 C243 C214 AC33 T27
VCC_6 VCC_AXG_NCTF_5 VCC_NCTF_4 VSS_NCTF_1
AJ31 VCC_7 VCC_AXG_NCTF_6 T23 AC35 VCC_NCTF_5 VSS_NCTF_2 T37
AJ28 T25 22U_8 .22U_4 .22U_4 .1U_4 AC36 U24
VCC_8 VCC_AXG_NCTF_7 VCC_NCTF_6 VSS_NCTF_3
AH32 VCC_9 VCC_AXG_NCTF_8 U15 AD35 VCC_NCTF_7 VSS_NCTF_4 U28

VCC CORE
AH31 VCC_10 VCC_AXG_NCTF_9 U16 AD36 VCC_NCTF_8 VSS_NCTF_5 V31
AH29 VCC_11 VCC_AXG_NCTF_10 U17 AF33 VCC_NCTF_9 VSS_NCTF_6 V35
AF32 VCC_12 VCC_AXG_NCTF_11 U19 AF36 VCC_NCTF_10 VSS_NCTF_7 AA19
VCC_AXG_NCTF_12 U20 AH33 VCC_NCTF_11 VSS_NCTF_8 AB17

VSS NCTF
VCC_AXG_NCTF_13 U21 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35
VCC_AXG_NCTF_14 U23 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19
R156 0_4 +1.05V_VCC_GMCH_VCC13 R30 U26 AH37 AD37
VCC_13 VCC_AXG_NCTF_15 VCC_NCTF_14 VSS_NCTF_11
VCC_AXG_NCTF_16 V16 AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17
V17 +1.05V AJ35 AF35
VCC_AXG_NCTF_17 VCC_NCTF_16 VSS_NCTF_13
VCC_AXG_NCTF_18 V19 AK33 VCC_NCTF_17 VSS_NCTF_14 AK17
V20 R100 IV@0_8 AK35 AM17
VCC_AXG_NCTF_19 VCC_NCTF_18 VSS_NCTF_15
VCC_AXG_NCTF_20 V21 AK36 VCC_NCTF_19 VSS_NCTF_16 AM24
V23 R118 IV@0_8 +1.05V_AXG AK37 AP26
VCC_AXG_NCTF_21 VCC_NCTF_20 VSS_NCTF_17
VCC_AXG_NCTF_22 V24 AD33 VCC_NCTF_21 VSS_NCTF_18 AP28
Y15 AJ36 AR15
+1.8VSUS
POWER VCC_AXG_NCTF_23 VCC_NCTF_22 VSS_NCTF_19

VCC NCTF
VCC_AXG_NCTF_24 Y16 AM35 VCC_NCTF_23 VSS_NCTF_20 AR19
VCC_AXG_NCTF_25 Y17 AL33 VCC_NCTF_24 VSS_NCTF_21 AR28
AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19 AL35 VCC_NCTF_25
AU33 VCC_SM_2 VCC_AXG_NCTF_27 Y20 AA33 VCC_NCTF_26
AU35 Y21 +1.05V_AXG AA35
VCC_SM_3 VCC_AXG_NCTF_28 VCC_NCTF_27
AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23 AA36 VCC_NCTF_28
C254 + C552 C247 C249 AW33 Y24 AP35
VCC_SM_5 VCC_AXG_NCTF_30 + C521 + C522 C191 C174 C172 C201 C185 VCC_NCTF_29
AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26 AP36 VCC_NCTF_30
.1U_4 330U_7 22U_8 22U_8 AY35 Y28 AR35
VCC_SM_7 VCC_AXG_NCTF_32 IV@330U_7 IV@330U_7 [email protected] IV@1U IV@10U_8 [email protected]_4 [email protected]_4 VCC_NCTF_31
BA32 VCC_SM_8 VCC_AXG_NCTF_33 Y29 AR36 VCC_NCTF_32
BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16 Y32 VCC_NCTF_33
C C
BA35 AA17 Y33
BB33
BC32
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
AB16
AB19
Y35
Y36
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
POWER
BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16 Y37 VCC_NCTF_37 VSS_SCB1 A3
BC35 VCC_SM_14 VCC_AXG_NCTF_39 AC17 T30 VCC_NCTF_38 VSS_SCB2 B2
VCC SM

VSS SCB
BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19 T34 VCC_NCTF_39 VSS_SCB3 C1
BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15 T35 VCC_NCTF_40 VSS_SCB4 BL1
BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16 U29 VCC_NCTF_41 VSS_SCB5 BL51
BE33 VCC_SM_18 VCC_AXG_NCTF_43 AD17 U31 VCC_NCTF_42 VSS_SCB6 A51
BE35
VCC GFX NCTF AF16 +1.05V_AXG U32
VCC_SM_19 VCC_AXG_NCTF_44 VCC_NCTF_43
BF33 VCC_SM_20 VCC_AXG_NCTF_45 AF19 U33 VCC_NCTF_44
BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15 U35 VCC_NCTF_45
BG32 VCC_SM_22 VCC_AXG_NCTF_47 AH16 U36 VCC_NCTF_46
BG33 AH17 R152 V32
VCC_SM_23 VCC_AXG_NCTF_48 VCC_NCTF_47
BG35 VCC_SM_24 VCC_AXG_NCTF_49 AH19 V33 VCC_NCTF_48
BH32 AJ16 V36 +1.05V
VCC_SM_25 VCC_AXG_NCTF_50 EV@0_4 VCC_NCTF_49
BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17 V37 VCC_NCTF_50
BH35 VCC_SM_27 VCC_AXG_NCTF_52 AJ19
BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16 VCC_AXM_1 AT33
BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19 VCC_AXM_2 AT31
+1.05V

VCC AXM
BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16 VCC_AXM_3 AK29
BK32 VCC_SM_31 VCC_AXG_NCTF_56 AL17 VCC_AXM_4 AK24
BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19 VCC_AXM_5 AK23
BK34 VCC_SM_33 VCC_AXG_NCTF_58 AL20 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26
BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21 AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23
BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23 AL28 VCC_AXM_NCTF_3
AU30 AM15 C239 C235 C262 C203 C220 C263 AM26
VCC_SM_36 VCC_AXG_NCTF_61 VCC_AXM_NCTF_4

VCC AXM NCTF

VCC_AXG_NCTF_62 AM16 AM28 VCC_AXM_NCTF_5
+1.05V_AXG AM19 22U_8 .22U_4 .22U_4 .1U_4 .1U_4 .1U_4 AM29
VCC_AXG_NCTF_63 VCC_AXM_NCTF_6
VCC_AXG_NCTF_64 AM20 AM31 VCC_AXM_NCTF_7
VCC_AXG_NCTF_65 AM21 AM32 VCC_AXM_NCTF_8
R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23 AM33 VCC_AXM_NCTF_9
B B
T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15 AP29 VCC_AXM_NCTF_10
W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16 AP31 VCC_AXM_NCTF_11
W14 VCC_AXG_4 VCC_AXG_NCTF_69 AP17 AP32 VCC_AXM_NCTF_12
Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19 AP33 VCC_AXM_NCTF_13
AA20 VCC_AXG_6 VCC_AXG_NCTF_71 AP20 AL29 VCC_AXM_NCTF_14
AA23 VCC_AXG_7 VCC_AXG_NCTF_72 AP21 AL31 VCC_AXM_NCTF_15
AA26 VCC_AXG_8 VCC_AXG_NCTF_73 AP23 AL32 VCC_AXM_NCTF_16
AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24 AR31 VCC_AXM_NCTF_17
AB21 VCC_AXG_10 VCC_AXG_NCTF_75 AR20 AR32 VCC_AXM_NCTF_18
AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21 AR33 VCC_AXM_NCTF_19
AB29 VCC_AXG_12 VCC_AXG_NCTF_77 AR23
AC20 VCC_AXG_13 VCC_AXG_NCTF_78 AR24
VCC GFX

AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26

AC23 VCC_AXG_15 VCC_AXG_NCTF_80 V26
AC24 V28 CRESTLINE_1p0
VCC_AXG_16 VCC_AXG_NCTF_81
AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AC28 VCC_AXG_18 VCC_AXG_NCTF_83 Y31
AC29 VCC_AXG_19
AD20 VCC_AXG_20
AD23 VCC_AXG_21
AD24 AW45 VCCSM_LF1
VCC_AXG_22 VCC_SM_LF1 VCCSM_LF2
AD28 VCC_AXG_23 VCC_SM_LF2 BC39
VCC SM LF

AF21 BE39 VCCSM_LF3

VCC_AXG_24 VCC_SM_LF3 VCCSM_LF4
AF26 VCC_AXG_25 VCC_SM_LF4 BD17
AA31 BD4 VCCSM_LF5
VCC_AXG_26 VCC_SM_LF5 VCCSM_LF6
AH20 VCC_AXG_27 VCC_SM_LF6 AW8
AH21 AT6 VCCSM_LF7
VCC_AXG_28 VCC_SM_LF7
AH23 VCC_AXG_29
AH24 C156 C154 C151 C171 C264 C257 C291
VCC_AXG_30
AH26 VCC_AXG_31
AD31 .1U_4 .1U_4 .22U_4 .22U_4 .47U 1U 1U
VCC_AXG_32
AJ20 VCC_AXG_33
A A
AN14 VCC_AXG_34

<OrgName>

CRESTLINE_1p0 <OrgAddr1>
<OrgAddr2> PROJECT : ZD1
<OrgAddr3>
<OrgAddr4>
Quanta Computer Inc.
Size Document Number Rev
GMCH Power-1(5/7) B

Date: Tuesday, December 12, 2006 Sheet 9 of 38

5 4 3 2 1
 5 4 3 2 1

NB(Power-2) CRT/TV Disable/Enable guideline

External VGA with EV@part, Internal VGA with IV@ part
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
+3V R172 IV@0
If SDVO Disable If SDVO enable If SDVO enable
C246 R162 Ball Enable Disable Ball Enable Disable Signal LVDS Disable LVDS Disable LVDS enable
<FAE>
INT VGA disable [email protected]_4 EV@0_4 VCCA_CRT 3.3V GND VCCA_C_TVO 3.3V GND VCCD_LVDS GND 1.8V 1.8V
+1.25V L50 10UH_8
VCCSYNC connect to GND VCCD_CRT 1.5V GND VCCD_TVO 1.5V 1.5V VCCA_LVDS GND GND 1.8V

+ C558 C557 VCCDQ_CRT 1.5V GND VCCABG_DAC 3.3V GND VCCTX_LVDS GND GND 1.8V
+3V L47 IV@BKP1608HS181-T
470U_7 .1U_4 VCCA_A_TVO 3.3V GND VSSABG_DAC GND GND
C547 C237 C245 R404 EXTERNAL INTERNAL
D VCCA_B_TVO 3.3V GND VCC_SYNC 3.3V GND D
*IV@22U_8 [email protected]_4 IV@22N_4 EV@0_4

U30H
+1.05V
+3V_VCCSYNC J32 U13
L24 10UH_8 +3V_TV_DAC R396 IV@0 VCCSYNC VTT_1
+1.25V VTT_2 U12
+3V_VCCA_CRT_DAC A33 U11
C544 C546 R403 VCCA_CRT_DAC_1 VTT_3 C134 C144 C137 + C523
B33 VCCA_CRT_DAC_2 VTT_4 U9
+ C338 C296 U8
VTT_5

CRT
[email protected]_4 IV@22N_4 EV@0_4 U7 4.7U_8 2.2U_8 .47U 330U_7
470U_7 .1U_4 +3V_VCCA_DAC_BG A30 VTT_6
IV&EV Dis/Enable setting VCCA_DAC_BG VTT_7 U5
VTT_8 U3
B32 VSSA_DAC_BG VTT_9 U2
VTT_10 U1
VTT_11 T13

VTT
+1.25V_VCCA_DPLLA B49 T11 +1.25VM_AXD R134 0 +1.25V
VCCA_DPLLA VTT_12
VTT_13 T10
+1.25V_VCCA_DPLLB H49 T9
VCCA_DPLLB VTT_14 C221 C202
VTT_15 T7

PLL
+1.25V L14 BKP1608HS181-T +1.25VM_VCCA_HPLL AL2 T6
VCCA_HPLL VTT_16 1U *22U_8
VTT_17 T5
C135 C145 +1.25VM_VCCA_MPLL AM2 T3
VCCA_MPLL VTT_18
VTT_19 T2
22U_8 .1U_4 +1.8VSUS R3
VTT_20

A LVDS
R179 IV@0 +1.8VSUS_VCC_LVDS A41 R2 R124 0 +1.25V
VCCA_LVDS VTT_21
VTT_22 R1
R186 C270 B41
L15 BKP1608HS181-T VSSA_LVDS C196 C182
EV@0_4 IV@1000P_4 AT23
VCC_AXD_1 1U 10U_8
VCC_AXD_2 AU28
C136 K50 AU24
VCCA_PEG_BG VCC_AXD_3

AXD
C R106 R415 0_8 +3V_VCCA_PEG_BG C
+3V VCC_AXD_4 AT29
0.5/F .1U_4 K49 AT25
VSSA_PEG_BG VCC_AXD_5

A PEG
C297 AT30
C132 22U_8 V1.25M_MPLL_RC VCC_AXD_6 R421 0 +1.25V
.1U_4 +1.25V_VCCD_PEG_PLL U51 AR29
VCCA_PEG_PLL VCC_AXD_NCTF C560

+1.25V R390 0 +1.25VM_VCCA_SM AW18 B23 +1.25V_VCC_AXF .1U_4

VCCA_SM_1 VCC_AXF_1
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2

AXF
C535 C539 C173 C538 C163 AU19 A21
+ VCCA_SM_3 VCC_AXF_3 L46 1UH_8
AU18 VCCA_SM_4 +1.8VSUS
100U_7 *22U_8 4.7U 22U_8 1U AU17 AJ50 +1.25V_VCC_DMI
VCCA_SM_5 VCC_DMI C192 C542

A SM
CRB RECOMMEND AT22 R391 1/F +V1.8_SMCK_RC C541 22U_8
VCCA_SM_7
180OHM@100MHz AT21 VCCA_SM_8 VCC_SM_CK_1 BK24 +1.8VSUS_VCC_SM_CK .1U_4 22U_8

SM CK
AT19 BK23
Rdc= 0.09OHM (max) AT18
VCCA_SM_9 VCC_SM_CK_2
BJ24
R185 0 VCCA_SM_10 VCC_SM_CK_3
+1.25V AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
AR17 VCCA_SM_NCTF_1
C265 C253 C258 C225 AR16 IV&EV Dis/Enable setting
VCCA_SM_NCTF_2
L21 *1U *1U 22U_8 .1U_4 A43 +1.8VSUS_VCC_TX_LVDS L48 IV@1UH_8
VCC_TX_LVDS

A CK
IV@BKP1608HS181-T +1.25VM_VCCA_SM_CK BC29 +1.8VSUS
VCCA_SM_CK_1
+3V BB29 VCCA_SM_CK_2
C40 R412 C554 + C553
VCC_HV_1 +3V_VCC_HV
C198 C227 R135 +3V_TV_DAC C25 B40
VCCA_TVA_DAC_1 VCC_HV_2

HV
B25 EV@0_4 IV@1000P_4 IV@220U_7
[email protected]_4 IV@22N_4 EV@0_4 VCCA_TVA_DAC_2
C27 VCCA_TVB_DAC_1
B27 VCCA_TVB_DAC_2 VCC_PEG_1 AD51

TV
B28 VCCA_TVC_DAC_1 VCC_PEG_2 W50
+1.05_PEG

PEG
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
R173 EV@0_4 V49
B VCC_PEG_4 B
VCC_PEG_5 V50

D TV/CRT
R164 IV@0 +1.5V_VCCD_CRT M32
+1.5V_VCCD_TVDAC VCCD_CRT
L29 VCCD_TVDAC
C229 C228 R136 AH50
VCC_RXR_DMI_1

DMI
+1.5V_VCCD_QDAC N28 AH51
[email protected]_4 IV@22N_4 EV@0_4 VCCD_QDAC VCC_RXR_DMI_2
C540 +1.25V R105 0 +1.25VM_MCH_VCCD_HPLL AN2 VCCD_HPLL L22 91nH
VTTLF1 A7 +1.05V

VTTLF
IV@22U_8 C142 +1.25V_VCCD_PEG_PLL U48 F2
VCCD_PEG_PLL VTTLF2
VTTLF3 AH1
.1U_4 C298 J41 C330 + C332
VCCD_LVDS_1 LVDS C138 C524 C532
H42 VCCD_LVDS_2 <FAE>
C543 C226 C215 R146 .1U_4 10U_8 220U_7 VCC_RXR_DMI and VCC_PEG
.47U_4 .47U_4 .47U_4
IV@10U_8 [email protected]_4 IV@22N_4 EV@0_4 L23 BKP1608HS181-T connect to+1.05V
+1.25V
CRESTLINE_1p0

R203
+ C334
1/F_8
220U_7
IV&EV Dis/Enable setting <FAE> +V1.25S_PEGPLL_FB
INT VGA disable
C341
VCCD_TVDAC still +1.5V
10U_8
+1.5V R402 0

C218 C217 D41

.1U_4 22N_4 +1.05V 2 1 +1.05V_SD

A A
R515 +3V_VCC_HV
R414 IV@0 +1.8V_VCCD_LVDS PDZ5.6B
+1.8VSUS

10
R153 IV@100 C279 C555 R187
+3V R181 0
Change to IV@1U *IV@10U_8 EV@0_4
100 ohm Resistor C219 C200 R133 C189 PROJECT : ZD1
C269
[email protected]_4 IV@22N_4 EV@0_4 <CRB>
IV@1U Use site for filter +1.25V AND +1.25M shall be .1U_4 Quanta Computer Inc.
cap with Gfx Size Document Number Rev
+1.5V for Calero Interposer

WWW.AliSaler.Com 5
enabled CS

4 3 2
Date:
GMCH Power-2(6/7)
Friday, December 08, 2006
1
Sheet 10 of 38
B
 5 4 3 2 1

NB(Power-3)

U30I

D D
A13 VSS_1 VSS_100 AW24
A15 AW29 U30J
VSS_2 VSS_101
A17 VSS_3 VSS_102 AW32 C46 VSS_199 VSS_287 W11
A24 VSS_4 VSS_103 AW5 C50 VSS_200 VSS_288 W39
AA21 VSS_5 VSS_104 AW7 C7 VSS_201 VSS_289 W43
AA24 VSS_6 VSS_105 AY10 D13 VSS_202 VSS_290 W47
AA29 VSS_7 VSS_106 AY24 D24 VSS_203 VSS_291 W5
AB20 VSS_8 VSS_107 AY37 D3 VSS_204 VSS_292 W7
AB23 VSS_9 VSS_108 AY42 D32 VSS_205 VSS_293 Y13
AB26 VSS_10 VSS_109 AY43 D39 VSS_206 VSS_294 Y2
AB28 VSS_11 VSS_110 AY45 D45 VSS_207 VSS_295 Y41
AB31 VSS_12 VSS_111 AY47 D49 VSS_208 VSS_296 Y45
AC10 VSS_13 VSS_112 AY50 E10 VSS_209 VSS_297 Y49
AC13 VSS_14 VSS_113 B10 E16 VSS_210 VSS_298 Y5
AC3 VSS_15 VSS_114 B20 E24 VSS_211 VSS_299 Y50
AC39 VSS_16 VSS_115 B24 E28 VSS_212 VSS_300 Y11
AC43 VSS_17 VSS_116 B29 E32 VSS_213 VSS_301 P29
AC47 B30 E47 T29 VSS_GMCH_T29 R142 0_4
VSS_18 VSS_117 VSS_214 VSS_302 VSS_GMCH_T31 R197 0_4
AD1 VSS_19 VSS_118 B35 F19 VSS_215 VSS_303 T31
AD21 B38 F36 T33 VSS_GMCH_T33 R198 0_4
VSS_20 VSS_119 VSS_216 VSS_304 VSS_GMCH_R28 R143 0_4
AD26 VSS_21 VSS_120 B43 F4 VSS_217 VSS_305 R28
AD29 VSS_22 VSS_121 B46 F40 VSS_218
AD3 VSS_23 VSS_122 B5 F50 VSS_219
AD41 VSS_24 VSS_123 B8 G1 VSS_220
AD45 VSS_25 VSS_124 BA1 G13 VSS_221 VSS_306 AA32
AD49 VSS_26 VSS_125 BA17 G16 VSS_222 VSS_307 AB32
AD5 VSS_27 VSS_126 BA18 G19 VSS_223 VSS_308 AD32
AD50 VSS_28 VSS_127 BA2 G24 VSS_224 VSS_309 AF28
AD8 VSS_29 VSS_128 BA24 G28 VSS_225 VSS_310 AF29
AE10 VSS_30 VSS_129 BB12 G29 VSS_226 VSS_311 AT27
AE14 VSS_31 VSS_130 BB25 G33 VSS_227 VSS_312 AV25
AE6 VSS_32 VSS_131 BB40 G42 VSS_228 VSS_313 H50
C C
AF20 BB44 G45
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G48
G8
VSS_229
VSS_230
VSS_231
AF31 VSS_36 VSS_135 BC16 H24 VSS_232
AG2 VSS_37 VSS_136 BC24 H28 VSS_233
AG38 VSS_38 VSS_137 BC25 H4 VSS_234
AG43 VSS_39 VSS_138 BC36 H45 VSS_235
AG47 VSS_40 VSS_139 BC40 J11 VSS_236
AG50 VSS_41 VSS_140 BC51 J16 VSS_237
AH3 VSS_42 VSS_141 BD13 J2 VSS_238
AH40 VSS_43 VSS_142 BD2 J24 VSS_239
AH41 VSS_44 VSS_143 BD28 J28 VSS_240
AH7 BD45 J33
AH9
AJ11
VSS_45
VSS_46
VSS_47
VSS_144
VSS_145
VSS_146
BD48
BD5
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AJ13 VSS_48 VSS_147 BE1
AJ21 VSS_49 VSS_148 BE19 K12 VSS_245
AJ24 VSS_50 VSS_149 BE23 K47 VSS_246
AJ29 VSS_51 VSS_150 BE30 K8 VSS_247
AJ32 VSS_52 VSS_151 BE42 L1 VSS_248
AJ43 VSS_53 VSS_152 BE51 L17 VSS_249
AJ45 VSS_54 VSS_153 BE8 L20 VSS_250
AJ49 VSS_55 VSS_154 BF12 L24 VSS_251
AK20 VSS_56 VSS_155 BF16 L28 VSS_252
AK21 VSS_57 VSS_156 BF36 L3 VSS_253
AK26 VSS_58 VSS_157 BG19 L33 VSS_254
AK28 VSS_59 VSS_158 BG2 L49 VSS_255
AK31 VSS_60 VSS_159 BG24 M28 VSS_256
AK51 VSS_61 VSS_160 BG29 M42 VSS_257
AL1 VSS_62 VSS_161 BG39 M46 VSS_258
AM11 VSS_63 VSS_162 BG48 M49 VSS_259
AM13 VSS_64 VSS_163 BG5 M5 VSS_260
B B
AM3 VSS_65 VSS_164 BG51 M50 VSS_261
AM4 VSS_66 VSS_165 BH17 M9 VSS_262
AM41 VSS_67 VSS_166 BH30 N11 VSS_263
AM45 VSS_68 VSS_167 BH44 N14 VSS_264
AN1 VSS_69 VSS_168 BH46 N17 VSS_265
AN38 VSS_70 VSS_169 BH8 N29 VSS_266
AN39 VSS_71 VSS_170 BJ11 N32 VSS_267
AN43 VSS_72 VSS_171 BJ13 N36 VSS_268
AN5 VSS_73 VSS_172 BJ38 N39 VSS_269
AN7 VSS_74 VSS_173 BJ4 N44 VSS_270
AP4 VSS_75 VSS_174 BJ42 N49 VSS_271
AP48 VSS_76 VSS_175 BJ46 N7 VSS_272
AP50 VSS_77 VSS_176 BK15 P19 VSS_273
AR11 VSS_78 VSS_177 BK17 P2 VSS_274
AR2 VSS_79 VSS_178 BK25 P23 VSS_275
AR39 VSS_80 VSS_179 BK29 P3 VSS_276
AR44 VSS_81 VSS_180 BK36 P50 VSS_277
AR47 VSS_82 VSS_181 BK40 R49 VSS_278
AR7 VSS_83 VSS_182 BK44 T39 VSS_279
AT10 VSS_84 VSS_183 BK6 T43 VSS_280
AT14 VSS_85 VSS_184 BK8 T47 VSS_281
AT41 VSS_86 VSS_185 BL11 U41 VSS_282
AT49 VSS_87 VSS_186 BL13 U45 VSS_283
AU1 VSS_88 VSS_187 BL19 U50 VSS_284
AU23 VSS_89 VSS_188 BL22 V2 VSS_285
AU29 VSS_90 VSS_189 BL37 V3 VSS_286
AU3 VSS_91 VSS_190 BL47
AU36 VSS_92 VSS_191 C12
AU49 C16 CRESTLINE_1p0
VSS_93 VSS_192
AU51 VSS_94 VSS_193 C19
AV39 VSS_95 VSS_194 C28
AV48 VSS_96 VSS_195 C29
A A
AW1 VSS_97 VSS_196 C33
AW12 VSS_98 VSS_197 C36
AW16 VSS_99 VSS_198 C41

CRESTLINE_1p0

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
GMCH Power-3(7/7) B

Date: Friday, December 08, 2006 Sheet 11 of 38

5 4 3 2 1
 5 4 3 2 1

RTC

+VCCRTC

D D
+3VPCU 2 1
D27 RB500V

R_3VRTC 2 1 R348 20K_4 RTC_RST#

D28 RB500V

1
C499 C506 JP5
C461 10P_4
R319 1U 1U
*RTC_RST

1
1K_4
Y3 R280
RTC_N02 1 3 R331 1K R326 1.2K 10M
+5VPCU
32.768KHZ

2
Q20 U34A
MMBT3904 CLK_32KX1 AG25 E5 LAD0 <22,30,31>
2

R320 C448 10P_4 CLK_32KX2 RTCX1 FWH0/LAD0

AF24 RTCX2 FWH1/LAD1 F5 LAD1 <22,30,31>
47K G8 +1.05V
FWH2/LAD2 LAD2 <22,30,31>
RTC_RST# AF23 F6
RTCRST# FWH3/LAD3 LAD3 <22,30,31>
RTC_N03 R314 150K
R304 1M_4 ICH_INTRUDER# AD22 C4 +1.05V
+VCCRTC INTRUDER# FWH4/LFRAME# LFRAME# <22,30,31>
CN39

RTC
LPC
1 ICH_INTVRMEN AF25 G9 LDRQ0#
INTVRMEN LDRQ0# T53
2 LAN100_SLP AD21 E6 ICH_GPIO23 R254 R260
LAN100_SLP LDRQ1#/GPIO23 T50
3
4 B24 AF13 GATEA20 *56.2/F_4 *56.2/F_4 R475
GLAN_CLK A20GATE GATEA20 <31>
A20M# AG26 H_A20M# <3>
RTC CONN D22 56.2/F_4
LAN_RSTSYNC H_DPRSTP#_R R261 0_4
DPRSTP# AF26 ICH_DPRSTP# <3,7,34>
C21 AE26 H_DPSLP#_R R255 0_4
LAN_RXD0 DPSLP# H_DPSLP# <3>
B21 LAN_RXD1
C22 LAN_RXD2 FERR# AD24 H_FERR# <3>

LAN / GLAN
C H_PWRGD_R R480 0_4 C
D21 LAN_TXD0 CPUPWRGD/GPIO49 AG29 H_PWRGD <3>
SB Strap
E20 LAN_TXD1
C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# <3>
T69 ICH_GPIO13 AH21 AE24
GLAN_DOCK#/GPIO13 INIT# H_INIT# <3>
INTR AC20 H_INTR <3>

CPU
INTVRMEN Low = Internal VR disable D25 AH14 RCIN#
GLAN_COMPI RCIN# RCIN# <31> +1.05V
High = Internal VR enable(Default) C25 GLAN_COMPO
NMI AD23 H_NMI <3>
ACZ_BCLK AJ16 AG28 H_SMI#_R
HDA_BIT_CLK SMI# H_SMI# <3>
ACZ_SYNC AJ15 HDA_SYNC R268
STPCLK# AA24 H_STPCLK# <3>
ACZ_RST# AE14
LAN100_SLP Low = Internal VR disable HDA_RST# H_THERMTRIP_R 56.2/F_4
THRMTRIP# AE27
High = Internal VR enable(Default) AJ17
<26> ACZ_SDIN0 HDA_SDIN0
AH17 AA23 ICH_TP8 R258 24/F R267 *0_4
<26> ACZ_SDIN1 HDA_SDIN1 TP8 T59 PM_THRMTRIP# <3,7>
ACZ_SDIN2 AH15 HDA_SDIN2 PDD[15:0] <24>
T83 ACZ_SDIN3 PDD0

IHDA
AD13 HDA_SDIN3 DD0 V1
T61 U2 PDD1 Placement close SB L<2"
+VCCRTC +VCCRTC ACZ_SDOUT DD1 PDD2
<14> ACZ_SDOUT AE13 HDA_SDOUT DD2 V3
T1 PDD3
GPIO33# DD3 PDD4
AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
T65 GPIO34# AG14 T5 PDD5
T71 HDA_DOCK_RST#/GPIO34 DD5 PDD6
DD6 AB2
R259 R252 SATA_LED# AF10 T6 PDD7
<30> SATA_LED# SATALED# DD7
332K/F 332K/F T3 PDD8
DD8 PDD9
<24> SATA_RXN0 AF6 SATA0RXN DD9 R2
ICH_INTVRMEN LAN100_SLP AF5 T4 PDD10
<24> SATA_RXP0 SATA0RXP DD10
C628 S-P@3900P_4 SATA_TXN0_C AH5 V6 PDD11
<24> SATA_TXN0 SATA0TXN DD11
C629 S-P@3900P_4 SATA_TXP0_C AH6 V5 PDD12
<24> SATA_TXP0 SATA0TXP DD12
U1 PDD13
R264 R263 DD13 PDD14
<24> SATA_RXN1 AG3 SATA1RXN DD14 V2
B *0_4 *0_4 PDD15 B
<24> SATA_RXP1 AG4 SATA1RXP DD15 U6

IDE
C627 S_HDD@3900P_4 SATA_TXN1_C AJ4
<24> SATA_TXN1 SATA1TXN PDA[2:0] <24>
C626 S_HDD@3900P_4 SATA_TXP1_C AJ3 AA4 PDA0
<24> SATA_TXP1 SATA1TXP DA0
AA1 PDA1
DA1

SATA
AF2 AB3 PDA2
SATA2RXN DA2
AF1 SATA2RXP
AE4 SATA2TXN DCS1# Y6 PDCS1# <24>
AE3 SATA2TXP DCS3# Y5 PDCS3# <24>

<2> CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 PDIOR# <24>

<2> CLK_PCIE_SATA AC6 SATA_CLKP DIOW# W3 PDIOW# <24>
HDA DDACK# Y2 PDDACK# <24>
AG1 SATARBIAS# IDEIRQ Y3 IRQ14 <24>
R277 24.9/F_4 SATA_BIAS AG2 Y1
SATARBIAS IORDY PIORDY <24>
DDREQ W5 PDDREQ <24>
<check list>
L<500mils ICH8M REV 1.0
ACZ_SDOUT R291 33_4
ACZ_SDOUT_AUDIO <26>
R307 33_4
ACZ_SDOUT_MDC <26>

ACZ_SYNC R487 33_4

ACZ_SYNC_AUDIO <26>
R502 33_4
ACZ_SYNC_MDC <26>

+3V
0810 UR FAE:
ACZ_BCLK R489 33_4
A BIT_CLK_AUDIO <26> RCIN# DOESN'T NEED PU A
R503 33_4
BIT_CLK_MDC <26>
RCIN# R498 *10K_4

GATEA20 R290 8.2K_4

ACZ_RST# R309 33_4

ACZ_RST#_AUDIO <26,27>
PROJECT : ZD1
R289 33_4
ACZ_RST#_MDC <26>
Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
ICH8M HOST(1/4)
Monday, December 11, 2006
1
Sheet 12 of 38
B
 5 4 3 2 1

SB-PCIE/USB/DMI SB-PCI
U34D U34B
<28> AD[0..31]
P27 V27 AD0 D20 A4 REQ0#
<23> PCIE_RXN1 PERN1 DMI0RXN DMI_RXN0 <7> AD0 REQ0# REQ0# <28>
AD1 GNT0#
NEW CARD
<23> PCIE_RXP1
C405 .1U_4 PCIE_TXN1_C
P26
N29
PERP1 DMI0RXP V26
U29
DMI_RXP0 <7>
AD2
E19
D19
AD1 PCI GNT0# D7
E18 REQ1#
GNT0# <28>
<23> PCIE_TXN1 PETN1 DMI0TXN DMI_TXN0 <7> AD2 REQ1#/GPIO50
C397 .1U_4 PCIE_TXP1_C N28 U28 AD3 A20 C18 GNT1#
<23> PCIE_TXP1 DMI_TXP0 <7> T48

Direct Media Interface

PETP1 DMI0TXP AD4 AD3 GNT1#/GPIO51 REQ2#
D17 AD4 REQ2#/GPIO52 B19
M27 Y27 AD5 A21 F18 GNT2#
<22> PCIE_RXN2 PERN2 DMI1RXN DMI_RXN1 <7> AD5 GNT2#/GPIO53 T51
M26 Y26 AD6 A19 A11 REQ3#
<22> PCIE_RXP2 PERP2 DMI1RXP DMI_RXP1 <7> AD6 REQ3#/GPIO54
TV CARD C611 .1U_4 PCIE_TXN2_C L29 W29 AD7 C19 C10 GNT3#
D <22> PCIE_TXN2 PETN2 DMI1TXN DMI_TXN1 <7> AD7 GNT3#/GPIO55 T47 D
C612 .1U_4 PCIE_TXP2_C L28 W28 AD8 A18
<22> PCIE_TXP2 PETP2 DMI1TXP DMI_TXP1 <7> AD8
AD9 B16 C17
AD9 C/BE0# CBE0# <28>

PCI-Express
K27 AB26 AD10 A12 E15
PERN3 DMI2RXN DMI_RXN2 <7> AD10 C/BE1# CBE1# <28>
K26 AB25 AD11 E16 F16
PERP3 DMI2RXP DMI_RXP2 <7> AD11 C/BE2# CBE2# <28>
J29 AA29 AD12 A14 E17
PETN3 DMI2TXN DMI_TXN2 <7> AD12 C/BE3# CBE3# <28>
J28 AA28 AD13 G16
PETP3 DMI2TXP DMI_TXP2 <7> AD13
AD14 A15 C8 IRDY#
AD14 IRDY# IRDY# <28>
H27 AD27 AD15 B6 D9
<22> PCIE_RXN4 PERN4 DMI3RXN DMI_RXN3 <7> AD15 PAR PAR <28>
H26 AD26 +1.5V AD16 C11 G6
<22> PCIE_RXP4 PERP4 DMI3RXP DMI_RXP3 <7> AD16 PCIRST# PCIRST# <22,28>
WLAN C385 .1U_4 PCIE_TXN4_C G29 AC29 AD17 A9 D16 DEVSEL#
<22> PCIE_TXN4 PETN4 DMI3TXN DMI_TXN3 <7> AD17 DEVSEL# DEVSEL# <28>
C389 .1U_4 PCIE_TXP4_C G28 AC28 AD18 D11 A7 PERR#
<22> PCIE_TXP4 PETP4 DMI3TXP DMI_TXP3 <7> AD18 PERR# PERR# <28>
AD19 B12 B7 LOCK#
R474 AD20 AD19 PLOCK# SERR#
<29> PCIE_RXN5 F27 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# <2> <CRB> C12 AD20 SERR# F10 SERR# <28>
F26 T25 DMI_IRCOMP_R<500mils AD21 D10 C16 STOP#
<29> PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH <2> AD21 STOP# STOP# <28>
ROBSON C379 .1U_4 PCIE_TXN5_C E29 24.9/F_4 AD22 C7 C9 TRDY#
<29> PCIE_TXN5 PETN5 AD22 TRDY# TRDY# <28>
C374 .1U_4 PCIE_TXP5_C E28 Y23 AD23 F13 A17 FRAME#
<29> PCIE_TXP5 PETP5 DMI_ZCOMP AD23 FRAME# FRAME# <28>
Y24 DMI_IRCOMP_R AD24 E11
DMI_IRCOMP AD25 AD24 PLT_RST-R# R481 0
<20> GLAN_RXN D27 PERN6/GLAN_RXN E13 AD25 PLTRST# AG24 PLTRST#_NB <7>
D26 G3 AD26 E12 B10 PCLK_ICH
<20> GLAN_RXP PERP6/GLAN_RXP USBP0N USBP0- <25> AD26 PCICLK PCLK_ICH <2>
GLAN C371 .1U_4 GLAN_TXN_SB AD27
<20> GLAN_TXN C29 PETN6/GLAN_TXN USBP0P G2 USBP0+ <25>USB D8 AD27 PME# G7 PCI_PME# <28>
C365 .1U_4 GLAN_TXP_SB C28 H5 AD28 A6
<20> GLAN_TXP PETP6/GLAN_TXP USBP1N USBP1- <25> AD28
AD29
USBP1P H4 USBP1+ <25>USB E8 AD29
C23 H2 AD30 D6
SPI_CLK USBP2N USBP2- <25> AD30
AD31
B23 SPI_CS0# USBP2P H1 USBP2+ <25>USB A3 AD31
E22 SPI_CS1# USBP3N J3 USBP3- <25>

SPI
USBP3P J2 USBP3+ <25>USB Interrupt I/F
D23 K5 INTA# F9 F8 INTE#
SPI_MOSI USBP4N USBP4- <21> <28> INTA# PIRQA# PIRQE#/GPIO2
INTB# INTF#
F21 SPI_MISO USBP4P K4 USBP4+ <21>BLUETOOTH <28> INTB# B5 PIRQB# PIRQF#/GPIO3 G11
K2 INTC# C5 F12 INTG#
USBP5N USBP5- <23> PIRQC# PIRQG#/GPIO4
USBOC#0 INTD# INTH# R211 *0_4
AJ19 OC0# USBP5P K1 USBP5+ <23>NEW CARD A10 PIRQD# PIRQH#/GPIO5 B3 CRT_SENSE# <19,31>
USBOC#1 AG16 L3
OC1#/GPIO40 USBP6N USBP6- <22>
USBOC#2 ICH8M REV 1.0
C
AG15 OC2#/GPIO41 USB USBP6P L2 USBP6+ <22>MINI PCIE C
USBOC#3 AE15 M5
OC3#/GPIO42 USBP7N USBP7- <18>
USBOC#4 AF15 OC4#/GPIO43 USBP7P M4 USBP7+ <18>CCD
USBOC#5 AG17 M2
OC5#/GPIO29 USBP8N USBP8- <22>
USBOC#6 AD12 OC6#/GPIO30 USBP8P M1 USBP8+ <22>3G CARD
NC_EN# AJ18 N3 USBP9-
<23> NC_EN# OC7#/GPIO31 USBP9N T57
USBOC#8 AD14 N2 USBP9+
OC8# USBP9P T58
USBOC#9 AH18 OC9#
USBRBIAS# F2
F3 USB_RBIAS_PN
USBRBIAS
ICH8M REV 1.0
R226
<CRB>
1.USB_RBIAS_PN<500mils 22.6/F
2.Avoid routing next to
clock/high speed signals

A16 SWAP Override strap

PCI_GNT#3 Low = A16 swap override enabled +3V +3V

High = Default
RP33 RP35
6 5 DEVSEL# 6 5
GNT3# R217 *1K_4 REQ0# 7 4 INTF# 7 4 STOP#
B INTG# REQ1# B
8 3 8 3
INTH# 9 2 INTC# SERR# 9 2 FRAME#
+3V 10 1 INTB# +3V 10 1 REQ2#

8.2KX8 8.2KX8

USBOC#8 R248 8.2K_4 +3V_S5

USBOC#9 R491 8.2K_4 +3V_S5

+3V_S5 +3V
RP38 RP34
+3V
USBOC#1 6 5 TRDY# 6 5
USBOC#5 7 4 USBOC#4 LOCK# 7 4 INTE#
NC_EN# 8 3 USBOC#6 IRDY# 8 3 INTD#
C457 USBOC#0 9 2 USBOC#3 PERR# 9 2 REQ3#
+3V_S5 10 1 USBOC#2 +3V 10 1 INTA#
.1U_4
U15 8.2KX8 8.2KX8
5

PLT_RST-R# 2
4 PLTRST# <14,17,20,22..24,29..31>
1

TC7SH08FU R295
3

A A
100K

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
ICH8M PCIE\PCI\USB(2/4) B

Date: Monday, December 11, 2006 Sheet 13 of 38

5 4 3 2 1
 5 4 3 2 1

SB-GPIO
U34C
PCLK_SMB AJ26 AJ12 GPIO21
<2,16,22,23> PCLK_SMB SMBCLK SATA0GP/GPIO21
PDAT_SMB AD19 AJ10 BOARD_ID2 T81
<2,16,22,23> PDAT_SMB SMBDATA SATA1GP/GPIO19
CL_RST#1 GPIO36

SATA
AG21 AF11

GPIO
<22> CL_RST#1 LINKALERT# SATA2GP/GPIO36

SMB
<FAE> SMB_CLK_ME AC17 AG11 GPIO37 T67
CRB STP_PCI# PU is no stuff. SMB_DATA_ME SMLINK0 SATA3GP/GPIO37 T72
AE19 SMLINK1
CRB STP_CPU# always keeps high to +3V AG9 14M_ICH
CLK14 14M_ICH <2>
RI#

Clocks
ensure ME alive in M1 state. AF17 G5 CLKUSB_48
RI# CLK48 CLKUSB_48 <2>
(CLK_MCH_BCLK/# must keep alive to
make ME work) T49 LPC_PD# F4 D3
SYS_RST# SUS_STAT#/LPCPD# SUSCLK
I think there will be update for this design, <3> SYS_RST# AD15 SYS_RESET#
I suggest you to keep PU and 0Ω AG23 SLP_S3# R303 100/F_4
SLP_S3# SUSB# <7,31>
isolation resistors for this signal. AG12 AF21 SLP_S4# R288 100/F_4
<7> PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# SUSC# <31>
R504 R317 AD18 SLP_S5#
*10K_4 *10K_4 SMB_ALERT# SLP_S5# T64 <FAE>
AG22 SMBALERT#/GPIO11
D ICH_GPIO26 Since your CPU VRM has no D
S4_STATE#/GPIO26 AH27
R306 0_4 PM_STPPCI_ICH# T77

GPIO
<2> PM_STPPCI# AE20 DPRSTP# pin, connect
PM_STPCPU_ICH# STP_PCI#/GPIO15

SYS
R490 0_4 AG18 AE23 ICH_PWROK PM_DPRSLPVR to IMVP6 is correct
<2> PM_STPCPU# STP_CPU#/GPIO25 PWROK
+3V CLKRUN# AH11 AJ14 PM_DPRSLPVR_R R501 100/F_4 If no use internal LAN MAC connect
<28,31> CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR <7,34>

Power MGT
LAN_RST# to PLTRST#
.1U_4 C475 PCIE_WAKE# AE17 AE21 PM_BATLOW#_R Use internal LAN MAC connect
<20,22,31> PCIE_WAKE# WAKE# BATLOW#
U36 SERIRQ AF12 LAN_RST# to RSMRST#
<28,30,31> SERIRQ SERIRQ
1 5 THERM_ALERT# AC13 C2 DNBSWON# should go high no sooner than 10 ms
<3,17> THERM_ALERT# THRM# PWRBTN# DNBSWON# <31>
<34> VR_PWRGD_CK410# 2 after both VccLAN3_3 and VccLAN1_5
3 4 VR_PWRGD_CLKEN AJ20 AH20 PM_LAN_ENABLE_R R494 0_4 have reached their nominal voltages.
VRMPWRGD LAN_RST# PLTRST# <13,17,20,22..24,29..31>
NC7SZ04 T79 TP7 AJ22 AG27 PM_RSMRST#_R
TP7 RSMRST#
BAS316 D42 KBSMI#_ICH AJ8 E1
<31> KBSMI# TACH1/GPIO1 CK_PWRGD CK_PWRGD <2>
BAS316 D43 LID591#_ICH AJ9 +3V_S5 +3V
<22,23,31> LID591# TACH2/GPIO6
T80 ICH_GPIO7 AH9 E3
TACH3/GPIO7 CLPWROK MPWROK <7,31>
SCI# AE16
<31> SCI# GPIO8
T62 ICH_GPIO12 AC19 AJ25
BOARD_ID0 GPIO12 SLP_M#
AG8 TACH0/GPIO17
BOARD_ID1 AH12 F23
GPIO18 CL_CLK0 CL_CLK0 <7>
BOARD_ID3 AE11 AE18 R299 R210
GPIO20 CL_CLK1 CL_CLK1 <22>

GPIO
Controller Link
T70 ICH_GPIO22 AG10 3.24K/F 3.24K/F
T85 ICH_GPIO27 SCLOCK/GPIO22
AH25 QRT_STATE0/GPIO27 CL_DATA0 F22 CL_DATA0 <7>
T63 ICH_GPIO28 AD16 AF19
QRT_STATE1/GPIO28 CL_DATA1 CL_DATA1 <22>
+3V SATACLKREQ# AG13
<2> SATACLKREQ# SATACLKREQ#/GPIO35
T68 ICH_GPIO38 AF9 D24 CL_VREF0_SB
R500 ICH_GPIO39 SLOAD/GPIO38 CL_VREF0 CL_VREF1_SB
AJ11 SDATAOUT0/GPIO39 CL_VREF1 AH23
T66 ICH_GPIO48 AD10
*10K_4 SDATAOUT1/GPIO48 C458
CL_RST# AJ23 CL_RST#0 <7>
<check list> PCSPK AD9 C382
<26> PCSPK SPKR
internal PD AJ27 ICH_GPIO24 .1U_4 R213
MEM_LED/GPIO24

MISC
C R497 0_4 MCH_ICH_SYNC#_R ICH_GPIO10 T78 R286 453/F_4 .1U_4 C
<7> MCH_ICH_SYNC# AJ13 MCH_SYNC# ME_EC_ALERT/GPIO10 AJ24
AF22 ICH_GPIO14 T82 453/F_4
ICH_TP3 EC_ME_ALERT/GPIO14 ICH_GPIO9 T84
AJ21 TP3 WOL_EN/GPIO9 AG19

ICH8M REV 1.0

No Reboot strap
Controller Link 1 VREF for IAMT support only
+3V_S5
HDA_SPKR Low = Default
High = No Reboot

RI# R272 10K_4

XOR Chain Entrance Strap CL_RST#1 R305 *10K_4 +3V
CLKUSB_48 14M_ICH INTEL FAE (08/17)
ICH_RSV0 HDA_SDOUT Description SMB_CLK_ME R250 10K_4 "Add RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)"
PCSPK R257 *10K_4
R225 R294 SMB_DATA_ME R269 10K_4
0 0 RSVD KBSMI#_ICH R522 10K_4
*10_4 *33_4 PCLK_SMB R496 2.2K_4 +3VSUS
LID591#_ICH R534 10K_4
0 1 Enter XOR Chain PDAT_SMB R262 2.2K_4
C380 C462
SMB_ALERT# R287 10K_4 R51
1 0 Normal opration(Default) *10P_4 *10P_4 ICH_GPIO39 R485 10K_4
PCIE_WAKE# R265 1K_4 Q6 4.7K_4
INTEL CRB SHOW IT MMBT3906
1 1 Set PCIE port config bit 1 PM_BATLOW#_R R249 8.2K_4
PM_RSMRST#_R 3 1
B RSMRST# <31> B
SYS_RST# R256 10K_4
+3V PM_LAN_ENABLE_R R493 *0_4 TO ICH8 FROM uR(EC)
ICH_GPIO10 R519 10K_4

2
R61
DISABLE LAN: STUFF 10K_4

2
R321
*1K D6
+3V 3 BAV99
ACZ_SDOUT <12>
ICH_GPIO14 R520 10K_4
ICH_TP3 SATACLKREQ# R310 10K_4

1
ICH_GPIO9 R278 100K_4
THERM_ALERT# R251 8.2K_4

2
VR_PWRGD_CLKEN R492 100K_4
SERIRQ R292 10K_4 D5
R495 ICH_PWROK R266 10K_4 3 BAV99
*1K_4 CLKRUN# R484 8.2K_4

SCI# R488 10K_4 R64

1
2.2K_4

+3V

C620 .1U_4
+3V +3V +3V +3V
5

DELAY_VR_PWRGOOD 1 U14 Board ID ID3 ID2 ID1 ID0

<3,7,34> DELAY_VR_PWRGOOD
4 ICH_PWROK
PWROK_EC 2
<17,31> PWROK_EC
A TC7SH08FU 0 0 0 0 R308 R506 R486 R505 A
3

R479 100K_4
*10K_4 *10K_4 *10K_4 *10K_4
0 0 0 1
BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0

0 0 1 0
R293 R483 R499 R482 PROJECT : ZD1
0 0 1 1
10K_4 10K_4 10K_4 10K_4
Quanta Computer Inc.
0 1 0 0 Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
ICH8M GPIO(3/4)
Monday, December 11, 2006
1
Sheet 14 of 38
B
 5 4 3 2 1

+3V_S5 +3V
+VCCRTC
C427 C424 C434 +1.05V

2
D18 D19 +1.05V
1U_4 .1U_4 .1U_4 U34F
AD25 VCCRTC VCC1_05[01] A13
PDZ5.6B PDZ5.6B B13 C396 .1U_4 U34E
VCC1_05[02]
A16 C13 A23 K7

1
R227 10 R244 100 +5VREF_SB V5REF[1] VCC1_05[03] C398 .1U_4 VSS[001] VSS[099]
+5V_S5 +5V T7 V5REF[2] VCC1_05[04] C14 A5 VSS[002] VSS[100] L1
VCC1_05[05] D14 AA2 VSS[003] VSS[101] L13
C391 C419 +5VREF_SUS_SB G4 E14 AA7 L15
V5REF_SUS VCC1_05[06] VSS[004] VSS[102]
VCC1_05[07] F14 A25 VSS[005] VSS[103] L26
.1U_4 .1U_4 AA25 G14 AB1 L27
D VCC1_5_B[01] VCC1_05[08] +1.5V VSS[006] VSS[104] D
AA26 VCC1_5_B[02] VCC1_05[09] L11 AB24 VSS[007] VSS[105] L4
AA27 VCC1_5_B[03] VCC1_05[10] L12 AC11 VSS[008] VSS[106] L5
AB27 VCC1_5_B[04] VCC1_05[11] L14 AC14 VSS[009] VSS[107] M12
AB28 L16 VCCDMIPLL_ICH 1UH_12 L54 +1.5V_ICH R471 1_8 AC25 M13
VCC1_5_B[05] VCC1_05[12] VSS[010] VSS[108]
AB29 VCC1_5_B[06] VCC1_05[13] L17 AC26 VSS[011] VSS[109] M14
D28 VCC1_5_B[07] VCC1_05[14] L18 AC27 VSS[012] VSS[110] M15
D29 M11 C615 C616 AD17 M16
VCC1_5_B[08] VCC1_05[15] VSS[013] VSS[111]

CORE
+1.5V L25 +1.5V_B E25 M18 AD20 M17
FBMJ2125HS420-T_8 VCC1_5_B[09] VCC1_05[16] .01U_4 10U VSS[014] VSS[112]
E26 VCC1_5_B[10] VCC1_05[17] P11 AD28 VSS[015] VSS[113] M23
E27 VCC1_5_B[11] VCC1_05[18] P18 AD29 VSS[016] VSS[114] M28
Intel use 0.5UH inductor + C395 C414 C413 C388 F24 T11 AD3 M29
VCC1_5_B[12] VCC1_05[19] +1.25V VSS[017] VSS[115]
F25 VCC1_5_B[13] VCC1_05[20] T18 AD4 VSS[018] VSS[116] M3
220U_7 22U_8 22U_8 2.2U G24 U11 AD6 N1
VCC1_5_B[14] VCC1_05[21] VSS[019] VSS[117]
H23 VCC1_5_B[15] VCC1_05[22] U18 AE1 VSS[020] VSS[118] N11
H24 V11 +1.25V_DMI R478 0_8 +1.05V AE12 N12
VCC1_5_B[16] VCC1_05[23] VSS[021] VSS[119]
J23 VCC1_5_B[17] VCC1_05[24] V12 AE2 VSS[022] VSS[120] N13
J24 VCC1_5_B[18] VCC1_05[25] V14 AE22 VSS[023] VSS[121] N14
+1.5V K24 V16 C619 R243 0 AD1 N15
VCC1_5_B[19] VCC1_05[26] VSS[024] VSS[122]
K25 VCC1_5_B[20] VCC1_05[27] V17 AE25 VSS[025] VSS[123] N16
L23 V18 22U_8 AE5 N17
VCC1_5_B[21] VCC1_05[28] C430 C431 C423 VSS[026] VSS[124]
L24 VCC1_5_B[22] AE6 VSS[027] VSS[125] N18

VCCA3GP
+1.5V_APLL L25 R29 AE9 N26
VCC1_5_B[23] VCCDMIPLL .1U_4 .1U_4 4.7U VSS[028] VSS[126]
M24 VCC1_5_B[24] AF14 VSS[029] VSS[127] N27
L29 C455 C456 M25 AE28 AF16 N4
10UH_8 VCC1_5_B[25] VCC_DMI[1] VSS[030] VSS[128]
N23 VCC1_5_B[26] VCC_DMI[2] AE29 AF18 VSS[031] VSS[129] N5
<Part Number> 10U 1U N24 +3V AF3 N6
VCC1_5_B[27] +1.05V_V_CPU_IO VSS[032] VSS[130]
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AF4 VSS[033] VSS[131] P12
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AG5 VSS[034] VSS[132] P13
P25 VCC1_5_B[30] AG6 VSS[035] VSS[133] P14
R24 VCC1_5_B[31] VCC3_3[01] AF29 AH10 VSS[036] VSS[134] P15
R25 VCC1_5_B[32] AH13 VSS[037] VSS[135] P16
R26 VCC1_5_B[33] VCC3_3[02] AD2 AH16 VSS[038] VSS[136] P17
C C
R27 VCC1_5_B[34] AH19 VSS[039] VSS[137] P23
T23 VCC1_5_B[35] VCC3_3[03] AC8 AH2 VSS[040] VSS[138] P28
T24 VCC1_5_B[36] VCC3_3[04] AD8 AF28 VSS[041] VSS[139] P29

VCCP_CORE
T27 AE8 C436 C437 AH22 R11
VCC1_5_B[37] VCC3_3[05] VSS[042] VSS[140]
T28 VCC1_5_B[38] VCC3_3[06] AF8 AH24 VSS[043] VSS[141] R12
T29 .1U_4 .1U_4 AH26 R13
C433 VCC1_5_B[39] VSS[044] VSS[142]
U24 VCC1_5_B[40] VCC3_3[07] AA3 AH3 VSS[045] VSS[143] R14
U25 VCC1_5_B[41] VCC3_3[08] U7 AH4 VSS[046] VSS[144] R15
1U V23 V7 C420 AH8 R16
VCC1_5_B[42] VCC3_3[09] VSS[047] VSS[145]
V24 VCC1_5_B[43] VCC3_3[10] W1 AJ5 VSS[048] VSS[146] R17
V25 W6 .1U_4 B11 R18

IDE
VCC1_5_B[44] VCC3_3[11] VSS[049] VSS[147]
W25 VCC1_5_B[45] VCC3_3[12] W7 B14 VSS[050] VSS[148] R28
Y25 VCC1_5_B[46] VCC3_3[13] Y7 B17 VSS[051] VSS[149] R4
B2 VSS[052] VSS[150] T12
AJ6 VCCSATAPLL VCC3_3[14] A8 B20 VSS[053] VSS[151] T13
VCC3_3[15] B15 B22 VSS[054] VSS[152] T14
AE7 VCC1_5_A[01] VCC3_3[16] B18 B8 VSS[055] VSS[153] T15
C426 AF7 B4 C24 T16
VCC1_5_A[02] VCC3_3[17] VSS[056] VSS[154]

ARX
AG7 VCC1_5_A[03] VCC3_3[18] B9 C26 VSS[057] VSS[155] T17
1U AH7 C15 C369 C367 C378 C27 T2
VCC1_5_A[04] VCC3_3[19] VSS[058] VSS[156]
AJ7 D13 C6 U12
VCC1_5_A[05] PCI VCC3_3[20]
D5 .1U_4 .1U_4 .1U_4 D12
VSS[059] VSS[157]
U13
VCC3_3[21] VSS[060] VSS[158]
AC1 VCC1_5_A[06] VCC3_3[22] E10 D15 VSS[061] VSS[159] U14
AC2 VCC1_5_A[07] VCC3_3[23] E7 D18 VSS[062] VSS[160] U15
ATX

AC3 F11 R516 0 +3V D2 U16

VCC1_5_A[08] VCC3_3[24] VSS[063] VSS[161]
AC4 VCC1_5_A[09] D4 VSS[064] VSS[162] U17
AC5 AC12 +3V_1.5V_HDA_IO_ICH R247 *0 +1.5V E21 U23
VCC1_5_A[10] VCCHDA VSS[065] VSS[163]
E24 VSS[066] VSS[164] U26
AC10 AD11 +VCCSUSHDA R245 *0 +1.5V_S5 E4 U27
VCC1_5_A[11] VCCSUSHDA C429 VSS[067] VSS[165]
AC9 VCC1_5_A[12] E9 VSS[068] VSS[166] U3
J6 TP_VCCSUS1_05_ICH_1 C422 R517 0 +3V_S5 Can be connect to F15 U5
VCCSUS1_05[1] TP_VCCSUS1_05_ICH_2 .1U_4 VSS[069] VSS[167]
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 +3V or +1.5V E23 VSS[070] VSS[168] V13
B .1U B
AA6 VCC1_5_A[14] Can be connect to F28 VSS[071] VSS[169] V15
AC16 TP_VCCSUS1_5_ICH_1 +3V_S5 or +1.5V_S5 F29 V28
VCCSUS1_5[1] VSS[072] VSS[170]
G12 VCC1_5_A[15] F7 VSS[073] VSS[171] V29
C377 G17 J7 TP_VCCSUS1_5_ICH_2 +3V_S5 G1 W2
VCC1_5_A[16] VCCSUS1_5[2] VSS[074] VSS[172]
H7 VCC1_5_A[17] E2 VSS[075] VSS[173] W26
.1U_4 C3 G10 W27
VCCSUS3_3[01] VSS[076] VSS[174]
AC7 VCC1_5_A[18] G13 VSS[077] VSS[175] Y28
AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 G19 VSS[078] VSS[176] Y29
AC21 C368 C366 G23 Y4
VCCSUS3_3[03] VSS[079] VSS[177]
D1 VCCUSBPLL VCCSUS3_3[04] AC22 G25 VSS[080] VSS[178] AB4
VCCPSUS

AG20 .1U_4 .022U_4 G26 AB23

VCCSUS3_3[05] VSS[081] VSS[179]
F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 G27 VSS[082] VSS[180] AB5
USB CORE

L6 VCC1_5_A[21] H25 VSS[083] VSS[181] AB6

C403 L7 P6 H28 AD5
VCC1_5_A[22] VCCSUS3_3[07] VSS[084] VSS[182]
M6 VCC1_5_A[23] VCCSUS3_3[08] P7 H29 VSS[085] VSS[183] U4
.1U_4 M7 C1 H3 W24
+1.5V VCC1_5_A[24] VCCSUS3_3[09] +V3.3A_USB_ICH R241 0_8 VSS[086] VSS[184]
VCCSUS3_3[10] N7 H6 VSS[087]
W23 VCC1_5_A[25] VCCSUS3_3[11] P1 J1 VSS[088] VSS_NCTF[01] A1
VCCSUS3_3[12] P2 J25 VSS[089] VSS_NCTF[02] A2
F17 P3 C411 J26 A28
VCCLAN1_05[1] VCCSUS3_3[13] VSS[090] VSS_NCTF[03]
VCCPUSB

G18 VCCLAN1_05[2] VCCSUS3_3[14] P4 J27 VSS[091] VSS_NCTF[04] A29

P5 4.7U J4 AH1
R231 0 +3V_VCCLAN VCCSUS3_3[15] VSS[092] VSS_NCTF[05]
+3V F19 VCCLAN3_3[1] VCCSUS3_3[16] R1 J5 VSS[093] VSS_NCTF[06] AH29
G20 VCCLAN3_3[2] VCCSUS3_3[17] R3 K23 VSS[094] VSS_NCTF[07] AJ1
C386 R5 TP_VCCSUS1_05_ICH_1 C392 .1U K28 AJ2
+1.5V_VCCGLANPLL VCCSUS3_3[18] TP_VCCSUS1_05_ICH_2 C454 .1U VSS[095] VSS_NCTF[08]
A24 VCCGLANPLL VCCSUS3_3[19] R6 K29 VSS[096] VSS_NCTF[09] AJ28
.1U_4 K3 AJ29
VSS[097] VSS_NCTF[10]
GLAN POWER

+1.5V_GLAN A26 G22 TP_VCCCL1_05_ICH TP_VCCSUS1_5_ICH_1 K6 B1

VCCGLAN1_5[1] VCCCL1_05 T60 VSS[098] VSS_NCTF[11]
A27 TP_VCCSUS1_5_ICH_2 B29
VCCGLAN1_5[2] T54 VSS_NCTF[12]
B26 A22 VCCCL1_5_INT_ICH TP_VCCCL1_05_ICH
VCCGLAN1_5[3] VCCCL1_5 T52
+1.5V R445 1_8 +1.5V_GLANP L52 1UH_12 B27 ICH8M REV 1.0
VCCGLAN1_5[4] +V3.3M_ICH C574 C575
B28 VCCGLAN1_5[5] VCCCL3_3[1] F20
A C573 C576 A
VCCCL3_3[2] G21
B25 1U *.1U_4
10U 2.2U VCCGLAN3_3
ICH8M REV 1.0

+1.5V R452 0

C577 PROJECT : ZD1

R228 0 +3V
4.7U
+3V R209 0 +3V_GLAN Quanta Computer Inc.
Size Document Number Rev
ICH8M Power(4/4) B

Date: Friday, December 08, 2006 Sheet 15 of 38

5 4 3 2 1
 5 4 3 2 1

+SMDDR_VREF +1.8VSUS +1.8VSUS +SMDDR_VREF +1.8VSUS +1.8VSUS

CN25 +SMDDR_VTERM CN24 +SMDDR_VTERM
1 2 RP17 56X2_4 1 2 RP20 56X2_4
VREF VSS46 M_A_DQ4 M_A_A10 VREF VSS46 M_B_DQ4 M_B_A0
3 VSS47 DQ4 4 1 2 3 VSS47 DQ4 4 1 2
M_A_DQ0 5 6 M_A_DQ5 M_A_BS0 3 4 M_B_DQ0 5 6 M_B_DQ5 M_B_A1 3 4 +SMDDR_VREF +1.8VSUS
M_A_DQ1 DQ0 DQ5 RP22 56X2_4 M_B_DQ1 DQ0 DQ5 RP19 56X2_4
7 DQ1 VSS15 8 7 DQ1 VSS15 8
9 10 M_A_DM0 M_A_A2 1 2 9 10 M_B_DM0 M_B_A3 1 2 R204 *1K_4
M_A_DQS#0 VSS37 DM0 M_A_A4 M_B_DQS#0 VSS37 DM0 M_B_A5 R202 *1K_4
11 DQS#0 VSS5 12 3 4 11 DQS#0 VSS5 12 3 4
M_A_DQS0 13 14 M_A_DQ6 RP21 56X2_4 M_B_DQS0 13 14 M_B_DQ6 RP23 56X2_4
DQS0 DQ6 M_A_DQ7 M_A_A5 DQS0 DQ6 M_B_DQ7 M_B_A4
15 VSS48 DQ7 16 1 2 15 VSS48 DQ7 16 1 2
M_A_DQ2 17 18 M_A_A3 3 4 M_B_DQ3 17 18 M_B_A6 3 4
M_A_DQ3 DQ2 VSS16 M_A_DQ12 RP25 56X2_4 M_B_DQ2 DQ2 VSS16 M_B_DQ12 RP26 56X2_4
19 DQ3 DQ12 20 19 DQ3 DQ12 20
D M_A_DQ13 M_A_A6 M_B_DQ13 M_B_A7 D
21 VSS38 DQ13 22 1 2 21 VSS38 DQ13 22 1 2
M_A_DQ8 23 24 M_A_A7 3 4 M_B_DQ8 23 24 M_B_A11 3 4
M_A_DQ9 DQ8 VSS17 M_A_DM1 RP24 56X2_4 M_B_DQ9 DQ8 VSS17 M_B_DM1 RP29 56X2_4
25 DQ9 DM1 26 25 DQ9 DM1 26
27 28 M_A_A8 1 2 27 28 M_B_A9 1 2
M_A_DQS#1 VSS49 VSS53 M_CLK0 M_A_A1 M_B_DQS#1 VSS49 VSS53 M_CLK2 M_B_A12
29 DQS#1 CK0 30 3 4 29 DQS#1 CK0 30 3 4
M_A_DQS1 31 32 M_CLK#0 RP27 56X2_4 M_B_DQS1 31 32 M_CLK#2 RP18 56X2_4
DQS1 CK0# M_A_A11 DQS1 CK0# M_B_BS1
33 VSS39 VSS41 34 1 2 33 VSS39 VSS41 34 1 2
M_A_DQ11 35 36 M_A_DQ10 M_A_A9 3 4 M_B_DQ10 35 36 M_B_DQ15 M_B_A2 3 4
M_A_DQ14 DQ10 DQ14 M_A_DQ15 RP6 56X2_4 M_B_DQ11 DQ10 DQ14 M_B_DQ14 RP7 56X2_4
37 DQ11 DQ15 38 37 DQ11 DQ15 38
39 40 M_ODT0 1 2 39 40 M_ODT2 1 2
VSS50 VSS54 M_A_A13 VSS50 VSS54 M_B_A13
3 4 3 4
41 42 RP14 56X2_4 41 42 RP16 56X2_4
M_A_DQ16 VSS18 VSS20 M_A_DQ20 M_A_RAS# M_B_DQ17 VSS18 VSS20 M_B_DQ16 M_B_BS0
43 DQ16 DQ20 44 1 2 43 DQ16 DQ20 44 1 2
M_A_DQ21 45 46 M_A_DQ17 M_A_BS1 3 4 M_B_DQ20 45 46 M_B_DQ21 M_B_WE# 3 4
DQ17 DQ21 RP31 56X2_4 DQ17 DQ21 RP32 56X2_4
47 VSS1 VSS6 48 47 VSS1 VSS6 48
M_A_DQS#2 49 50 PM_EXTTS#0 M_A_A12 1 2 M_B_DQS#2 49 50 PM_EXTTS#1 M_CKE2 1 2
M_A_DQS2 DQS#2 NC3 M_A_DM2 M_A_BS2 M_B_DQS2 DQS#2 NC3 M_B_DM2 M_B_BS2
51 DQS2 DM2 52 3 4 51 DQS2 DM2 52 3 4
RP13 56X2_4 RP12 56X2_4
PC4800 DDR2 SDRAM

PC4800 DDR2 SDRAM

53 VSS19 VSS21 54 53 VSS19 VSS21 54
M_A_DQ19 55 56 M_A_DQ18 M_A_WE# 1 2 M_B_DQ19 55 56 M_B_DQ18 M_B_CAS# 1 2
M_A_DQ23 DQ18 DQ22 M_A_DQ22 M_A_CAS# M_B_DQ23 DQ18 DQ22 M_B_DQ22 M_B_A10
57 DQ19 DQ23 58 3 4 57 DQ19 DQ23 58 3 4
59 60 RP10 56X2_4 59 60 RP15 56X2_4
M_A_DQ24 VSS22 VSS24 M_A_DQ28 M_CS#0 M_B_DQ25 VSS22 VSS24 M_B_DQ29 M_CS#2
61 DQ24 DQ28 62 1 2 61 DQ24 DQ28 62 1 2
M_A_DQ25 63 64 M_A_DQ29 M_A_A0 3 4 M_B_DQ24 63 64 M_B_DQ28 M_B_RAS# 3 4
DQ25 DQ29 RP28 56X2_4 DQ25 DQ29 RP30 56X2_4
SO-DIMM (200P)

SO-DIMM (200P)
65 VSS23 VSS25 66 65 VSS23 VSS25 66
M_A_DM3 67 68 M_A_DQS#3 M_CKE0 1 2 M_B_DM3 67 68 M_B_DQS#3 M_CKE3 1 2
DM3 DQS#3 M_A_DQS3 M_CKE1 DM3 DQS#3 M_B_DQS3 M_B_A8
69 NC4 DQS3 70 3 4 69 NC4 DQS3 70 3 4
71 72 RP9 56X2_4 71 72 RP8 56X2_4
M_A_DQ31 VSS9 VSS10 M_A_DQ26 M_CS#1 M_B_DQ26 VSS9 VSS10 M_B_DQ31 M_CS#3
73 DQ26 DQ30 74 1 2 73 DQ26 DQ30 74 1 2
M_A_DQ30 75 76 M_A_DQ27 M_ODT1 3 4 M_B_DQ27 75 76 M_B_DQ30 M_ODT3 3 4
DQ27 DQ31 DQ27 DQ31 PM_EXTTS#1
77 VSS4 VSS8 78 77 VSS4 VSS8 78 <7> PM_EXTTS#1
M_CKE0 79 80 M_CKE1 M_A_A14 R180 56_4 M_CKE2 79 80 M_CKE3 M_B_A14R175 56_4
CKE0 CKE1 CKE0 CKE1 PM_EXTTS#0
81 VDD7 VDD8 82 81 VDD7 VDD8 82 <7> PM_EXTTS#0
C C
83 NC1 A15 84 83 NC1 A15 84
M_A_BS2 85 86 M_A_A14 M_B_BS2 85 86 M_B_A14 PDAT_SMB
A16_BA2 A14 A16_BA2 A14 <2,14,22,23> PDAT_SMB
87 VDD9 VDD11 88 87 VDD9 VDD11 88
M_A_A12 89 90 M_A_A11 M_B_A12 89 90 M_B_A11 PCLK_SMB
A12 A11 A12 A11 <2,14,22,23> PCLK_SMB
M_A_A9 91 92 M_A_A7 M_B_A9 91 92 M_B_A7
M_A_A8 A9 A7 M_A_A6 +SMDDR_VTERM M_B_A8 A9 A7 M_B_A6 M_CS#[3:0]
93 A8 A6 94 93 A8 A6 94 <7> M_CS#[3:0]
95 96 C169 .1u_4 95 96 +SMDDR_VTERM
M_A_A5 VDD5 VDD4 M_A_A4 C190 .1u_4 M_B_A5 VDD5 VDD4 M_B_A4 C283 .1u_4 M_ODT[3:0]
97 A5 A4 98 97 A5 A4 98 <7> M_ODT[3:0]
M_A_A3 99 100 M_A_A2 C175 .1u_4 M_B_A3 99 100 M_B_A2 C183 .1u_4
M_A_A1 A3 A2 M_A_A0 C234 .1u_4 M_B_A1 A3 A2 M_B_A0 C199 .1u_4 M_CKE[3:0]
101 A1 A0 102 101 A1 A0 102 <7> M_CKE[3:0]
103 104 C222 .1u_4 103 104 C251 .1u_4
M_A_A10 VDD10 VDD12 M_A_BS1 C275 .1u_4 M_B_A10 VDD10 VDD12 M_B_BS1 C187 .1u_4 M_CLK#[3:0]
105 A10/AP BA1 106 105 A10/AP BA1 106 <7> M_CLK#[3:0]
M_A_BS0 107 108 M_A_RAS# C231 .1u_4 M_B_BS0 107 108 M_B_RAS# C240 .1u_4
M_A_WE# BA0 RAS# M_CS#0 C274 .1u_4 M_B_WE# BA0 RAS# M_CS#2 C230 .1u_4 M_CLK[3:0]
109 WE# S0# 110 109 WE# S0# 110 <7> M_CLK[3:0]
111 112 C277 .1u_4 111 112 C271 .1u_4
M_A_CAS# VDD2 VDD1 M_ODT0 C176 .1u_4 M_B_CAS# VDD2 VDD1 M_ODT2 C272 .1u_4
113 CAS# ODT0 114 113 CAS# ODT0 114
M_CS#1 115 116 M_A_A13 C276 .1u_4 M_CS#3 115 116 M_B_A13 C170 .1u_4
S1# A13 C178 .1u_4 S1# A13 C255 .1u_4 M_A_CAS#
117 VDD3 VDD6 118 117 VDD3 VDD6 118 <8> M_A_CAS#
M_ODT1 119 120 C278 .1u_4 M_ODT3 119 120 C236 .1u_4
ODT1 NC2 C177 .1u_4 ODT1 NC2 C261 .1u_4 M_A_RAS#
121 VSS11 VSS12 122 121 VSS11 VSS12 122 <8> M_A_RAS#
M_A_DQ37 123 124 M_A_DQ36 M_B_DQ32 123 124 M_B_DQ37 C273 .1u_4
M_A_DQ33 DQ32 DQ36 M_A_DQ32 M_B_DQ36 DQ32 DQ36 M_B_DQ33 M_A_WE#
125 DQ33 DQ37 126 125 DQ33 DQ37 126 <8> M_A_WE#
127 VSS26 VSS28 128 127 VSS26 VSS28 128
M_A_DQS#4 129 130 M_A_DM4 +SMDDR_VREF M_B_DQS#4 129 130 M_B_DM4 M_A_BS[2:0]
DQS#4 DM4 DQS#4 DM4 +SMDDR_VREF <8> M_A_BS[2:0]
M_A_DQS4 131 132 M_B_DQS4 131 132
DQS4 VSS42 M_A_DQ38 C333 .1u_4 DQS4 VSS42 M_B_DQ34 M_A_DM[7:0]
133 VSS2 DQ38 134 133 VSS2 DQ38 134 <8> M_A_DM[7:0]
M_A_DQ34 135 136 M_A_DQ39 M_B_DQ39 135 136 M_B_DQ35 C335 .1u_4
M_A_DQ35 DQ34 DQ39 C337 2.2u_4 M_B_DQ38 DQ34 DQ39 M_A_DQS#[7:0]
137 DQ35 VSS55 138 137 DQ35 VSS55 138 <8> M_A_DQS#[7:0]
139 140 M_A_DQ44 139 140 M_B_DQ41 C336 2.2u_4
M_A_DQ40 VSS27 DQ44 M_A_DQ45 +1.8VSUS M_B_DQ44 VSS27 DQ44 M_B_DQ40 M_A_DQS[7:0]
141 DQ40 DQ45 142 141 DQ40 DQ45 142 <8> M_A_DQS[7:0]
M_A_DQ41 143 144 M_B_DQ45 143 144 +1.8VSUS
DQ41 VSS43 M_A_DQS#5 C545 330u_7343 DQ41 VSS43 M_B_DQS#5 M_A_A[14:0]
145 VSS29 DQS#5 146 145 VSS29 DQS#5 146 <8> M_A_A[14:0]
B M_A_DM5 M_A_DQS5 M_B_DM5 M_B_DQS5 C519 330u_7343 B
+

147 DM5 DQS5 148 147 DM5 DQS5 148

C244 2.2u_4 M_A_DQ[63:0]

+
149 VSS51 VSS56 150 149 VSS51 VSS56 150 <8> M_A_DQ[63:0]
M_A_DQ47 151 152 M_A_DQ46 C260 2.2u_4 M_B_DQ47 151 152 M_B_DQ46 C259 2.2u_4
M_A_DQ43 DQ42 DQ46 M_A_DQ42 C194 2.2u_4 M_B_DQ43 DQ42 DQ46 M_B_DQ42 C216 2.2u_4
153 DQ43 DQ47 154 153 DQ43 DQ47 154
155 156 C184 2.2u_4 155 156 C197 2.2u_4
M_A_DQ53 VSS40 VSS44 M_A_DQ52 C266 2.2u_4 M_B_DQ48 VSS40 VSS44 M_B_DQ52 C267 2.2u_4 M_B_CAS#
157 DQ48 DQ52 158 157 DQ48 DQ52 158 <8> M_B_CAS#
M_A_DQ48 159 160 M_A_DQ49 C212 .1u_4 M_B_DQ49 159 160 M_B_DQ53 C223 2.2u_4
DQ49 DQ53 C242 .1u_4 DQ49 DQ53 C204 .1u_4 M_B_RAS#
161 VSS52 VSS57 162 161 VSS52 VSS57 162 <8> M_B_RAS#
163 164 M_CLK1 C224 .1u_4 163 164 M_CLK3 C211 .1u_4
NCTEST CK1 M_CLK#1 C248 .1u_4 NCTEST CK1 M_CLK#3 C195 .1u_4 M_B_WE#
165 VSS30 CK1# 166 165 VSS30 CK1# 166 <8> M_B_WE#
M_A_DQS#6 167 168 M_B_DQS#6 167 168 C268 .1u_4
M_A_DQS6 DQS#6 VSS45 M_A_DM6 M_B_DQS6 DQS#6 VSS45 M_B_DM6 M_B_BS[2:0]
169 DQS6 DM6 170 169 DQS6 DM6 170 <8> M_B_BS[2:0]
171 VSS31 VSS32 172 171 VSS31 VSS32 172
M_A_DQ50 173 174 M_A_DQ54 +3V M_B_DQ50 173 174 M_B_DQ54 M_B_DM[7:0]
DQ50 DQ54 DQ50 DQ54 +3V <8> M_B_DM[7:0]
M_A_DQ51 175 176 M_A_DQ55 M_B_DQ51 175 176 M_B_DQ55
DQ51 DQ55 C123 .1u_4 DQ51 DQ55 M_B_DQS#[7:0]
177 VSS33 VSS35 178 177 VSS33 VSS35 178 <8> M_B_DQS#[7:0]
M_A_DQ56 179 180 M_A_DQ60 M_B_DQ56 179 180 M_B_DQ60 C125 .1u_4
M_A_DQ61 DQ56 DQ60 M_A_DQ57 C127 2.2u_4 M_B_DQ57 DQ56 DQ60 M_B_DQ61 M_B_DQS[7:0]
181 DQ57 DQ61 182 181 DQ57 DQ61 182 <8> M_B_DQS[7:0]
183 184 183 184 C122 2.2u_4
M_A_DM7 VSS3 VSS7 M_A_DQS#7 M_B_DM7 VSS3 VSS7 M_B_DQS#7 M_B_A[14:0]
185 DM7 DQS#7 186 185 DM7 DQS#7 186 <8> M_B_A[14:0]
187 188 M_A_DQS7 187 188 M_B_DQS7
M_A_DQ62 VSS34 DQS7 M_B_DQ58 VSS34 DQS7 M_B_DQ[63:0]
189 DQ58 VSS36 190 189 DQ58 VSS36 190 <8> M_B_DQ[63:0]
M_A_DQ59 191 192 M_A_DQ58 M_B_DQ59 191 192 M_B_DQ62
DQ59 DQ62 M_A_DQ63 DQ59 DQ62 M_B_DQ63 +3V
193 VSS14 DQ63 194 193 VSS14 DQ63 194
PDAT_SMB 195 196 PDAT_SMB 195 196
PCLK_SMB SDA VSS13 A_SA0 A_SA0 R99 10K_4 PCLK_SMB SDA VSS13 B_SA0 B_SA0 R95 10K_4
197 SCL SA0 198 197 SCL SA0 198
199 200 A_SA1 A_SA1 R94 10K_4 199 200 B_SA1 B_SA1 R96 10K_4
+3V VDD(SPD) SA1 +3V VDD(SPD) SA1
DDR2_SODIMM_H5.2_RVS DDR2_SODIMM_H9.2_RVS

SMbus address A0 Close to DIMM0 SMbus address A2 Close to DIMM1

A
SO-DIMM0 SO-DIMM1 A

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
DDRII SO-DIMM B

WWW.AliSaler.Com 5 4 3 2
Date: Tuesday, December 12, 2006

1
Sheet 16 of 38
 5 4 3 2 1

VIN CN27A CN27B

1 125 EV_LVDS_UCLK# 148 207 HDMICLK-

PWR_SRC CLK_REQ# <18> EV_LVDS_UCLK# LVDS_UCLK# DVI_A_CLK# HDMICLK- <23>
3 EV_LVDS_UCLK 150 209 HDMICLK+
PWR_SRC <18> EV_LVDS_UCLK LVDS_UCLK DVI_A_CLK HDMICLK+ <23>
5 PWR_SRC
7 PWR_SRC
D PLTRST# EV_LVDS_UTX#0 HDMITX0N D
4Amp 9 PWR_SRC PEX_RST# 127 PLTRST# <13,14,20,22..24,29..31> <18> EV_LVDS_UTX#0 172 LVDS_UTX0# DVI_A_TX0# 225 HDMITX0N <23>
11 EV_LVDS_UTX#1 166 219 HDMITX1N
PWR_SRC <18> EV_LVDS_UTX#1 LVDS_UTX1# DVI_A_TX1# HDMITX1N <23>
13 EV_LVDS_UTX#2 160 213 HDMITX2N

DVI-A
PWR_SRC <18> EV_LVDS_UTX#2 LVDS_UTX2# DVI_A_TX2# HDMITX2N <23>
15 PWR_SRC 154 LVDS_UTX3#
121 CLK_MXM#
+5V PEX_REFCLK# CLK_MXM# <2>
123 CLK_MXM 227 HDMITX0P
PEX_REFCLK CLK_MXM <2> DVI_A_TX0 HDMITX0P <23>
0.5Amp EV_LVDS_UTX0 174 221 HDMITX1P
PEG_RXN[15:0] <18> EV_LVDS_UTX0 LVDS_UTX0 DVI_A_TX1 HDMITX1P <23>
18 EV_LVDS_UTX1 168 215 HDMITX2P
5VRUN PEG_RXN[15:0] <6> <18> EV_LVDS_UTX1 LVDS_UTX1 DVI_A_TX2 HDMITX2P <23>
EV_LVDS_UTX2 162
+3V <18> EV_LVDS_UTX2 LVDS_UTX2
115 PEG_RXN0 156 205 HDMI_HP_A
PEX_RX0# LVDS_UTX3 DVI_A_HPD HDMI_HP_A <23>
109 PEG_RXN1
PEX_RX1# PEG_RXN2
1.5Amp 226 3V3RUN PEX_RX2# 103

LVDS
228 97 PEG_RXN3 EV_LVDS_LCLK# 178
3V3RUN PEX_RX3# <18> EV_LVDS_LCLK# LVDS_LCLK#
230 91 PEG_RXN4 EV_LVDS_LCLK 180 220 MXM_HDMI_DDCCLK

DVI
3V3RUN PEX_RX4# <18> EV_LVDS_LCLK LVDS_LCLK DDCB_CLK MXM_HDMI_DDCCLK <23>
85 PEG_RXN5 218 MXM_HDMI_DDCDATA
+2.5V PEX_RX5# DDCB_DAT MXM_HDMI_DDCDATA <23>
79 PEG_RXN6
PEX_RX6# PEG_RXN7 EV_LVDS_LTX#0
0.5Amp PEX_RX7# 73 <18> EV_LVDS_LTX#0 202 LVDS_LTX0#
222 67 PEG_RXN8 EV_LVDS_LTX#1 196
2V5RUN PEX_RX8# <18> EV_LVDS_LTX#1 LVDS_LTX1#
61 PEG_RXN9 EV_LVDS_LTX#2 190 177
+1.8V PEX_RX9# <18> EV_LVDS_LTX#2 LVDS_LTX2# IGP/DVI_B_CLK#
55 PEG_RXN10 184 179
PEX_RX10# PEG_RXN11 LVDS_LTX3# IGP/DVI_B_CLK
PEX_RX11# 49
2 43 PEG_RXN12

DVI-B
1V8RUN PEX_RX12# PEG_RXN13 EV_LVDS_LTX0
3.5Amp 4 1V8RUN PEX_RX13# 37 <18> EV_LVDS_LTX0 204 LVDS_LTX0 IGP/DVI_B_TX0# 201
6 31 PEG_RXN14 EV_LVDS_LTX1 198 195
1V8RUN PEX_RX14# <18> EV_LVDS_LTX1 LVDS_LTX1 IGP/DVI_B_TX1#
8 25 PEG_RXN15 EV_LVDS_LTX2 192 189
1V8RUN PEX_RX15# <18> EV_LVDS_LTX2 LVDS_LTX2 IGP_/DVI_B_TX2#
10 1V8RUN 186 LVDS_LTX3
12 PEG_RXP[15:0]
1V8RUN PEG_RXP[15:0] <6>
14 EV_LVDS_VDDEN 212 203
1V8RUN <18> EV_LVDS_VDDEN LVDS_PPEN IGP/DVI_B_TX0
117 PEG_RXP0 EV_LVDS_BLON 216 197
PEX_RX0 <23> EV_LVDS_BLON LVDS_BLEN IGP/DVI_B_TX1
111 PEG_RXP1 EV_LVDS_BL_BRGHT 214 191
PEX_RX1 <18> EV_LVDS_BL_BRGHT LVDS_BL_BRGHT IGP_DVI_B_TX2
17 105 PEG_RXP2
GND PEX_RX2 PEG_RXP3 EV_LVDS_DDCCLK
19 GND PEX_RX3 99 <18> EV_LVDS_DDCCLK 210 DDCC_CLK DVI_B_HPD/GND 181
C PEG_RXP4 EV_LVDS_DDCDAT C
20 GND PEX_RX4 93 <18> EV_LVDS_DDCDAT 208 DDCC_DAT
21 87 PEG_RXP5
GND PEX_RX5 PEG_RXP6
22 GND PEX_RX6 81
23 75 PEG_RXP7
GND PEX_RX7 PEG_RXP8 EV_CRT_HSYNC
24 GND PEX_RX8 69 <19> EV_CRT_HSYNC 139 VGA_HSYNC IGP 147
29 63 PEG_RXP9 EV_CRT_VSYNC 141 149
GND PEX_RX9 <19> EV_CRT_VSYNC VGA_VSYNC IGP
32 57 PEG_RXP10 151
GND PEX_RX10 IGP

CRT
35 51 PEG_RXP11 EV_CRT_R 136 159
GND PEX_RX11 <19> EV_CRT_R VGA_RED IGP
38 45 PEG_RXP12 EV_CRT_G 140 161
GND PEX_RX12 <19> EV_CRT_G VGA_GREEN IGP
41 39 PEG_RXP13 EV_CRT_B 144 163
GND PEX_RX13 <19> EV_CRT_B VGA_BLUE IGP
44 33 PEG_RXP14 165
GND PEX_RX14 PEG_RXP15 EV_CRT_DDCCLK IGP
47 GND PEX_RX15 27 <19> EV_CRT_DDCCLK 143 DDCA_CLK IGP 167
50 EV_CRT_DDCDAT 145 169 +3V
GND <19> EV_CRT_DDCDAT DDCA_DAT IGP
53 GND IGP 171
56 GND IGP 173
59 PEG_TXN[15:0]
GND PEG_TXN[15:0] <6>
62 EV_TV_Y/G 128 185
GND <19> EV_TV_Y/G TV_Y/HDTV_Y/TV_CVBS RSVD
65 118 PEG_TXN0 183
GND PEX_TX0# RSVD

TV
68 112 PEG_TXN1 EV_TV_C/R 124 155 R530
GND PEX_TX1# <19> EV_TV_C/R TV_C/HDTV_Pr RSVD
71 106 PEG_TXN2 153 *10K_4
GND PEX_TX2# PEG_TXN3 EV_TV_COMP RSVD
74 GND PEX_TX3# 100 <19> EV_TV_COMP 132 TV_CVBS/HDTV_Pb RSVD 131
77 94 PEG_TXN4 129
GND PEX_TX4# PEG_TXN5 RSVD
80 GND PEX_TX5# 88
83 82 PEG_TXN6
GND PEX_TX6# PEG_TXN7 R196 EV@0_4 THERM# 137 MXM_PWROK_EC R528 EV@0_4
86 GND PEX_TX7# 76 <3,14> THERM_ALERT# THERM# RUNPWROK 16 PWROK_EC <14,31>
89 70 PEG_TXN8
GND PEX_TX8# PEG_TXN9 MXMDATA MXM_ACIN D44 EV@BAS316
92 GND PEX_TX9# 64 133 SMB_DAT AC/BATT# 157 ACIN <22,31,32>
95 58 PEG_TXN10 MXMCLK 135
GND PEX_TX10# PEG_TXN11 SMB_CLK
98 GND PEX_TX11# 52
101 46 PEG_TXN12
GND PEX_TX12# PEG_TXN13 EV@MXM CONNECTOR_2
104 GND PEX_TX13# 40
107 34 PEG_TXN14
B GND PEX_TX14# PEG_TXN15 B
110 GND PEX_TX15# 28
113 GND
116 PEG_TXP[15:0]
GND PEG_TXP[15:0] <6>
119 GND
126 120 PEG_TXP0 +2.5V VIN
GND PEX_TX0 PEG_TXP1 +3V
130 GND PEX_TX1 114
134 108 PEG_TXP2
GND PEX_TX2 PEG_TXP3 Q7
138 GND PEX_TX3 102
2

142 96 PEG_TXP4 EV@RHU002N06 C280 C286 C289 C287 C288 C290 C64 C50
GND PEX_TX4 PEG_TXP5
146 GND PEX_TX5 90
152 84 PEG_TXP6 MXMCLK 1 3 MXM_CLK <31>
SPDIF_MXM GND PEX_TX6 PEG_TXP7
158 GND PEX_TX7 78
164 72 PEG_TXP8 EV@1u_4 [email protected]_4 EV@10u_8 EV@10u_8 EV@10u_8 [email protected]_4 [email protected]_4 [email protected]_4
GND PEX_TX8 PEG_TXP9
170 GND PEX_TX9 66
175 60 PEG_TXP10 +3V
GND PEX_TX10 PEG_TXP11
176 GND PEX_TX11 54
182 48 PEG_TXP12 Q8
GND PEX_TX12
2

187 42 PEG_TXP13 EV@RHU002N06

GND PEX_TX13 PEG_TXP14 +3V
188 GND PEX_TX14 36
193 30 PEG_TXP15 MXMDATA 1 3 MXM_DATA <31>
GND PEX_TX15
194 GND
199 GND
200 C284 C282 C256 C294 C562 C561
GND
206 GND
211 GND
217 GND
223 EV@10u_8 [email protected]_4 *[email protected]_4 *[email protected]_4 *[email protected]_4 *[email protected]_4
GND EVPRSNT1# R188 EV@0_4
224 GND PRSNT1# 122
229 GND PRSNT2# 26

A
EV@MXM CONNECTOR_2 +3V A
+1.8V +5V

MXMCLK R81 [email protected]_4 C548 C550 C549 C551

MXMDATA R86 [email protected]_4 PROJECT : ZD1

EV@0_4 R297 SPDIF_MXM
<26> MXM_SPDIF_OUT
change from 10k to 4.7k , NV suggestion. on 10/20 EV@10u_8 [email protected]_4 EV@1u_4 [email protected]_4
Quanta Computer Inc.
Size Document Number Rev
MXM B
Date: Monday, December 11, 2006 Sheet 17 of 38
5 4 3 2 1
 5 4 3 2 1

LVDS

+5V +3V
TXLCLKOUT- RN6 2 1 IV@0X2 INT_TXLCLKOUT- <6>
TXLCLKOUT+ 4 3 INT_TXLCLKOUT+ <6>
CN1 R5 0_8
D EC_L_BKLT_CTRL <31> D
TXLOUT0- RN15 4 3 IV@0X2 R7 *EV@0_8
INT_TXLOUT0- <6> 1 2 EV_LVDS_BL_BRGHT <17>
TXLOUT0+ 2 1 LCDVCC LVDS_VADJ R6 *IV@0_8
INT_TXLOUT0+ <6> 3 4 L_BKLT_CTRL <6>
5 6 CCD_POWER <21>
TXLOUT1- RN17 2 1 IV@0X2 USBP7-_R 3 4
INT_TXLOUT1- <6> <23> DISPON 7 8 USBP7- <13>
TXLOUT1+ 4 3 VIN R9 0_8 INVCC0 USBP7+_R 1 2
INT_TXLOUT1+ <6> 9 10 USBP7+ <13>
TXLOUT2- RN12 4 11 12
3 IV@0X2 INT_TXLOUT2- <6> 13 14
TXUOUT1+ RP1 0X2
TXLOUT2+ 2 1 TXUOUT1-
INT_TXLOUT2+ <6> 15 16
TXUOUT2+
TXUOUT2- 17 18 TXLCLKOUT+
19 20 TXLCLKOUT-
TXLOUT0+ 21 22
TXLOUT0- 23 24 TXLOUT1+
25 26 TXLOUT1-
RN5 27 28
1 2 EV@0X2 EV_LVDS_LCLK# <17>
TXLOUT2+
29 30
3 4 TXLOUT2- TXUOUT0+
EV_LVDS_LCLK <17> 31 32 TXUOUT0-
RN14 3 TXUCLKOUT+ 33 34
4 EV@0X2 EV_LVDS_LTX#0 <17> 35 36
1 2 TXUCLKOUT- LCD_EDIDDATA
EV_LVDS_LTX0 <17> 37 38 LCD_EDIDCLK
RN16 1 39 40
2 EV@0X2 EV_LVDS_LTX#1 <17> 41 42
3 4 EV_LVDS_LTX1 <17>
RN11 3 4 EV@0X2 ACES_88242-40XX_LVDS
EV_LVDS_LTX#2 <17>
1 2 EV_LVDS_LTX2 <17>

+5V +3V

C C
C12 C4

1000P_4 1000P_4

TXUCLKOUT- RN2 2 1 IV@0X2 INT_TXUCLKOUT- <6>

TXUCLKOUT+ 4 3 INT_TXUCLKOUT+ <6>
TXUOUT0- RN4 4 3 IV@0X2 INT_TXUOUT0- <6>
TXUOUT0+ 2 1 INT_TXUOUT0+ <6>
TXUOUT1- RN8 2 1 IV@0X2 INT_TXUOUT1- <6>
TXUOUT1+ 4 3 INT_TXUOUT1+ <6>
TXUOUT2- RN10 4 3 IV@0X2 INT_TXUOUT2- <6>
TXUOUT2+ 2 1 INT_TXUOUT2+ <6>

RN1 1 2 EV@0X2 EV_LVDS_UCLK# <17>

3 4 EV_LVDS_UCLK <17>
RN3 3 4 EV@0X2 EV_LVDS_UTX#0 <17>
1 2 EV_LVDS_UTX0 <17>
RN7 1 2 EV@0X2
B EV_LVDS_UTX#1 <17> B
3 4 EV_LVDS_UTX1 <17>
RN9 3 4 EV@0X2 EV_LVDS_UTX#2 <17>
1 2 EV_LVDS_UTX2 <17>

+3V

C3 U1
+3V
.1U_4 6 1 LCDVCC_1 R10 0_8 LCDVCC
IN OUT
4 2 C14 C13 C16
IN GND C23 C17
R399 R14 IV@0_4 DISP_ON 3 5 .1U_4 .01U_4 10U_8
<6> INT_LVDS_DIGON ON/OFF GND .1U_4 10U_8
2.2K_4 R13 EV@0_4
<17> EV_LVDS_VDDEN
AAT4280
R400 EV@0_4 LCD_EDIDCLK
VIN <17> EV_LVDS_DDCCLK
R398 IV@0_4 R12
<6> INT_LVDS_EDIDCLK
<demo circuit>
+3V Crestline suggest 100K
G73 suggest 10K(ZS1 Default)100K_4
R393 (Need to confirm with Max)
C21 + C22
A 2.2K_4 A
*10U 1000P_4 R394 EV@0_4 LCD_EDIDDATA
<17> EV_LVDS_DDCDAT
R392 IV@0_4
<6> INT_LVDS_EDIDDATA

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
LVDS
Monday, December 11, 2006
1
Sheet 18 of 38
B
 1 2 3 4 5 6 7 8

CRT Select CRT CONNECTOR AND ESD

R30 EV@0_4 SYS_VGA_RED
<17> EV_CRT_R
R32 EV@0_4 SYS_VGA_GRN D1 SSM14 CRTVDD3 CN13

16
<17> EV_CRT_G +5V
R35 EV@0_4 SYS_VGA_BLU CRT
<17> EV_CRT_B
6
R28 EV@0_4 HSYNC SYS_VGA_RED L3 BLM18BA220SN1 CRT_R1 1 11 CRT_11 T1
<17> EV_CRT_HSYNC
7
R25 EV@0_4 VSYNC SYS_VGA_GRN L2 BLM18BA220SN1 CRT_G1 2 12 DDCDAT_1
<17> EV_CRT_VSYNC
8
R20 EV@0_4 CRTDCLK SYS_VGA_BLU L1 BLM18BA220SN1 CRT_B1 3 13 CRTHSYNC
A <17> EV_CRT_DDCCLK A
9
R17 EV@0_4 CRTDDAT 4 14 CRTVSYNC
<17> EV_CRT_DDCDAT
R15 R11 R8 C26 C20 C15 C11 C19 C25 10
5 15 DDCCLK_1
150/F_4 150/F_4 150/F_4 10P_4 10P_4 10P_4 10P_4 10P_4 10P_4

R29 IV@0_4
<6> INT_CRT_RED

17
R31 IV@0_4
<6> INT_CRT_GRN
R34 IV@0_4
<6> INT_CRT_BLU
R27 IV@0_4
<6> INT_HSYNC
R24 IV@0_4
<6> INT_VSYNC
R19 IV@0_4 D3
<6> INT_CRT_DDCCLK
*MTW355
R18 IV@0_4
<6> INT_CRT_DDCDAT

D2 MTW355 CRT_SENSE# <13,31>

+5V
U2
CRTVDD3 1 16 CRT_VSYNC1 L4 BLM18BA220SN1 CRTVSYNC
C30 VCC_SYNC SYNC_OUT2 CRT_HSYNC1 L5 BLM18BA220SN1 CRTHSYNC C10 .1U_4 CRTVDD3
SYNC_OUT1 14
.1U_4 7
CRT_BYP VCC_DDC C9 *10P_4 CRTVSYNC
8 BYP
C28 .22U/25V 15 VSYNC CRTVDD3
B SYNC_IN2 HSYNC C18 *10P_4 CRTHSYNC B
+3V 2 VCC_VIDEO SYNC_IN1 13

C8 10P_4 DDCCLK_1
C29 SYS_VGA_RED 3 10 CRTDCLK R23 2.7K_4 R26 R21
VIDEO_1 DDC_IN1 +3V
.1U_4 SYS_VGA_GRN 4 11 CRTDDAT R22 2.7K_4 2.7K_4 2.7K_4 C24 10P_4 DDCDAT_1
SYS_VGA_BLU VIDEO_2 DDC_IN2
5 VIDEO_3
9 DDCCLK_1
DDC_OUT1 DDCDAT_1
6 GND DDC_OUT2 12

IP4772

TV Out (SVHS) MiniDIN 7-pin

CN22

7
L40 BLM18PG181SN1D L42 BLM18PG181SN1D
R380 EV@0_4 SYS_TV_Y/G SYS_TV_C/R TV-CHROMA 4 3 TV-LUMA SYS_TV_Y/G

7
<17> EV_TV_Y/G 4 3
R373 EV@0_4 SYS_TV_C/R
C <17> EV_TV_C/R C
R377 EV@0_4 SYS_TV_COMP 9 8
<17> EV_TV_COMP 9 8
R372 C525 C526 C531 C533 R381

150/F_4 6P_4 6P_4 6P_4 6P_4 150/F_4

R379 IV@0_4
<6> INT_TV_Y/G
2 2 1 1

5
R371 IV@0_4
<6> INT_TV_C/R

5
R374 IV@0_4 TV_OUT
<6> INT_TV_COMP

L41 BLM18PG181SN1D
TV-COMP SYS_TV_COMP

C528 C527 R375

6P_4 6P_4 150/F_4

+3V +3V +3V

1

D D37 D36 D38 D

3 TV-COMP 3 TV-CHROMA 3 TV-LUMA

*DA204U *DA204U *DA204U

2

<OrgName>

<OrgAddr1> PROJECT : ZD1

<OrgAddr2>
<OrgAddr3>
<OrgAddr4> Quanta Computer Inc.
Size Document Number Rev
CRT/TVOUT B

Date: Monday, December 11, 2006 Sheet 19 of 38

1 2 3 4 5 6 7 8
 5 4 3 2 1

LAN +3V_S5

Q11

2
DTC144EUA R107
4.7K_4
+3V_S5

3 1 PCIE_WAKE_R#
<14,22,31> PCIE_WAKE#
VAUX_25
+3V_S5

VDDP+AVDD)
D D
U21
C120 C112 1 24
.1U-16V_4 .1U-16V_4 VAUX_25 TX0P TCT1 MCT1 X-TX0P
2 TD1+ MX1+ 23 X-TX0P <21>
L7 BLM11A601S TX0N 3 22 X-TX0N
TD1- MX1- X-TX0N <21>
VAUX_12 BIASVDD

15
19
56
61

17
68
4 TCT2 MCT2 21

6
TX1P 5 20 X-TX1P
TD2+ MX2+ X-TX1P <21>
5 C73 TX1N 6 19 X-TX1N

VDDP
VDDP
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDC TD2- MX2- X-TX1N <21>
13 36 .1U-16V_4
VDDC BIASVDD
20 VDDC 7 TCT3 MCT3 18
34 L13 BLM11A601S TX2P 8 17 X-TX2P
VDDC TD3+ MX3+ X-TX2P <21>
55 23 XTALVDD TX2N 9 16 X-TX2N
VDDC XTALVDD TD3- MX3- X-TX2N <21>
60 VDDC
L10 BLM11A601S C107 10 15
AVDDL TX3P TCT4 MCT4 X-TX3P
39 AVDDL AVDD 38 .1U-16V_4 11 TD4+ MX4+ 14 X-TX3P <21>
44 L9 BLM11A601S TX3N 12 13 X-TX3N
C78 C72 46
AVDDL
AVDDL
BCM5787M
10mm X 10mm AVDD 45 AVDD_F14 TD4- MX4-
NS892402P
X-TX3N <21>
51 AVDDL
4.7U-10V_8 .1U-16V_4 68-Pin QFN 52
L8 BLM11A601S AVDD C88 C71 R40 R39 R38 R37
VAUX_12 GPHY_PLLVDD 35 .1U-16V_4 .1U-16V_4 75/F_4 75/F_4 75/F_4 75/F_4
C68 C74 GPHY_PLLVDD
49 TX3N
4.7U-10V_8 .1U-16V_4 TRD3- TX3P
TRD3+ 50
L11 BLM11A601S
PCIE_PLLVDD 30 48 TX2N
C87 C98 PCIE_PLLVDD TRD2- TX2P C36
TRD2+ 47
1500P/2KV_1808
4.7U-10V_8 .1U-16V_4 42 TX1N
L12 BLM11A601S TRD1- TX1P
27 PCIE_VDD TRD1+ 43
PCIE_SDS_VDD 33
C C96 C92 PCIE_VDD TX0N C
TRD0- 41
40 TX0P
4.7U-10V_8 .1U-16V_4 TRD0+
24 PCIE_GND
2 LINKLED#
LINKLED# 100# +3V_S5
SPD100LED# 1
67 1000#
C103 .1U-16V_4 GLAN_TXP_5787 26 SPD1000LED# LAN_ACTLED#
<13> GLAN_RXP PCIE_TXDP TRAFFICLED# 66 LAN_ACTLED# <21>
C105 .1U-16V_4 GLAN_TXN_5787 25
<13> GLAN_RXN PCIE_TXDN
<13> GLAN_TXP 31 PCIE_RXDP GPIO2 8 T12
32 R88 R92 R97 C114
<13> GLAN_TXN PCIE_WAKE_R# PCIE_RXDN 4.7K_4 *4.7K_4 4.7K_4 .1U-16V_4
12 WAKE#
R91 0_4 -LAN_RST 10 9 T13
<13,14,17,22..24,29..31> PLTRST# PERST# UART_MODE BCM_WP
<2> CLK_PCIE_LAN 29 REFCLK+ GPIO1_SERIALDI 7
<2> CLK_PCIE_LAN# 28 REFCLK- GPIO0_SERIALDO 4 T11
U5

+3V_S5 R71 1K_4 AUX_PRES 54 8 1

R70 1K_4 VMA_PRES 53 VAUXPRSNT VCC A0
+3V VMAINPRSNT 7 WP A1 2
R90 4.7K_4 3 65 BCM_SCL 6 3
LOW_PWR SCLK SI SCL NC
SI 63 5 SDA GND 4
R77 47K LAN_SMBC 58 64 BCM_SDA
R73 47K LAN_SMBD SMB_CLK SO CS#
+3V_S5 57 SMB_DATA CS# 62
AT24C64
CLK_LAN_X2
CLK_LAN_X1
22 XTALO NC/(ENERGY_DET) 59 T9 Broadcom recommended cost down solution
21 XTALI
+3V_S5
RDAC 37 RDAC

3
18 LAN REGCTL25 C119 C133 D8 BAS316
R66 REGCTL25 Q9 LINKLED# 1 LAN_LINKLED#
2 LAN_LINKLED# <21>
CLK_LAN_X1 1.21K 1 MMJT9435 .1U-16V_4 4.7U-10V_8 D9 BAS316
C110 27P_4 100# 1 2
2

14 LAN REGCTL12 D7 BAS316

B Y1 REGCTL12 1000# 1 B
2

2
4
25MHZ VAUX_25
T14 11
1

CLK_LAN_X2 NC(CLK_REQ#)
REG_GND 16
C108 27P_4 LAN_REG1_2V
GND

3
C139 C141
VAUX_25 +3V_S5

10U/10V_8
Q10
MMJT9435 .1U-16V_4
U10 1
69

2
4 VAUX_12
C124 C121

C131 C140 .1U-16V_4 47U-6.3V_12

C66 C67
.1U-16V_4 10U-6.3V_8 .01U_4 .01U_4
VAUX_12

C115 C85 C104 C118 C109 C95 C117 C65

Close Transformer
.1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4 4.7U-10V_8

LAN_REG1_2V R112 1.5_12 +3V_S5

A BCM_SCL R85 *4.7K_4 A
+3V_S5
SI R84 *4.7K_4 R109 *1_12 VAUX_25
CS# R83 4.7K_4
C116 C106 C111 C101 C113 <OrgName>

.1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4 4.7U-10V_8 A1A: (9/1 BCM recommend)

in order to pull up C321/C51 and Q17 pin 3 to
<OrgAddr1> PROJECT : ZD1
<OrgAddr2>
3V_LAN rail. <OrgAddr3>
<OrgAddr4> Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
BCM5787 LAN/TRANSFORMER
Tuesday, December 12, 2006
1
Sheet 20 of 38
B
 1 2 3 4 5 6 7 8

RJ45-11 CAMERA MODULE CONNECTOR

C27 1000P_4

C31 1000P_4

A A
CN14 CCD_POWER
CCD_POWER <18>
+3V_S5 R33 220_4 +3V_LED1 1 LED1_YELP_Y +3V
LAN_ACTLED# 2 +3V 1 3
<20> LAN_ACTLED# LED1_YELN_Y
C1 10U_8

+
Q1 R1

2
X-TX3N 3 AO3413 C2 1000P_4 4.7K
<20> X-TX3N RX2-
X-TX3P 4
<20> X-TX3P RX2+

3
X-TX1N 5
<20> X-TX1N RX1-
X-TX2N 6 15 2
<20> X-TX2N TX2- GND15 CCD_POWERON <31>
TIPL
X-TX2P 7 16
<20> X-TX2P TX2+ GND16 Q2

1
X-TX1P 8 17 C34 DTC144EU
<20> X-TX1P RX1+ GND17 470pF/3KV_C CN3
X-TX0N 9 18
<20> X-TX0N TX1- GND18 1
X-TX0P 2
<20> X-TX0P 10 TX1+ FI-S2P-HF(JAE)
C35
470pF/3KV_C
+3V_S5 R36 220_4 +3V_LED2 11 RINGL
LED2_P_A2
LAN_LINKLED# 12
<20> LAN_LINKLED# LED2_GRNN_A3

B TIPL B
13 TIP
RINGL 14 RING

FOXCONN_JM34F23-P2053

C33 1000P_4
BLUETOOTH MODULE CONNECTOR
C32 1000P_4

Q19
AO3413

+3VSUS 1 3 BT_POWER_R L31 BK2125HS330_8 BT_POWER

2nd FAN
C464 10U_8

+
CIR

2
C467 1000P_4

C C
+3V +5V +5V +5V
BT_POWERON# <31>

Change from +3VSUS to +3VPCU R541 R542 R543

10K_4 10K_4 10K_4
+3VPCU
U37
1

CN12
1 Q33
<31> CIRRX2
2 AO3413 BT_POWER 1
3 2 2
4 RP39 1 2 0X2 USBP4+_R 3
<13> USBP4+
5 3 4 USBP4-_R 4
<13> USBP4-
3

BT_LED 5
CN31 <22> BT_LED
6
3

EVER_IRM-V038_TRI-P 7
2 2ND_FAN_ON
1
Q31 2 Aces 88266-0500
3
3

2N7002E C490 C480 C495

1

C635 *22P_4 *22P_4 .01U_4

BAS316 D45 2 0.1U/X7R-50V FAN_CON
<22> FAN_OT#
Q34
2N7002E
1

D D

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
BT/CCD/RJ45-11/CIR/2nd FAN B
Date: Monday, December 11, 2006 Sheet 21 of 38
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

MINI-Card +1.5V

+3V R67 0 +3V_MC L6 FBJ3216HS800_12 +3V_MINI-CARD

+ C62 C79

10U_8 .1U_4
+3VSUS R59 *0
R78 *0_4
A <13,28> PCIRST# A
R72 *0_4
<2,30> PCLK_DEBUG
CN19
51 52 +3V_MINI-CARD
R80 *0_4 CL_RST#0_CN Reserved +3.3V
<14> CL_RST#1 49 Reserved GND 50
R76 *0_4 CL_DATA1_CN 47 48 +1.5V
<14> CL_DATA1 Reserved +1.5V
R74 *0_4 CL_CLK1_CN 45 46
<14> CL_CLK1 Reserved LED_WPAN#
R69 0_4 KEDRON_GND_43 43 44 WL_LED#
+3V_MINI-CARD Reserved LED_WLAN#
41 Reserved LED_WWAN# 42
39 Reserved GND 40
R68 0_4 KEDRON_GND_37 37 38 USBP6+_R RP4 3 4 0X2 + C514 C513
Reserved USB_D+ USBP6+ <13>
35 36 USBP6-_R 1 2
GND USB_D- USBP6- <13>
33 34 10U_8 .1U_4
<13> PCIE_TXP4 PETp0 GND
<13> PCIE_TXN4 31 PETn0 SMB_DATA 32 PDAT_SMB <2,14,16,23>
29 GND SMB_CLK 30 PCLK_SMB <2,14,16,23>
27 GND +1.5V 28
<13> PCIE_RXP4 25 PERp0 GND 26
<13> PCIE_RXN4 23 PERn0 +3.3Vaux 24
21 GND PERST# 22 PLTRST# <13,14,17,20,23,24,29..31>
19 20 RF_EN_RR R65 0_4
Reserved Reserved RF_EN <31>
17 Reserved GND 18 Q24
15 16 LFRAME#_R R60 0_4 DTA114YUA
GND Reserved LFRAME# <12,30,31>
13 14 LAD3_R R57 0_4 +3V
+3VSUS <2> CLK_PCIE_MINI1 REFCLK+ Reserved LAD3 <12,30,31>
11 12 LAD2_R R53 0_4 R352
<2> CLK_PCIE_MINI1# REFCLK- Reserved LAD2 <12,30,31>
9 10 LAD1_R R52 0_4 1 3 WL_LED
GND Reserved LAD1 <12,30,31>

47K
7 8 LAD0_R R50 0_4
CLKREQ# Reserved LAD0 <12,30,31>
5 6 330_4
Reserved +1.5V

10K
3 Reserved GND 4
Q5 1 2
WAKE# +3.3V
2

R49

2
*DTC144EU *4.7K_4 Alltop_MINI CARD
WL_LED#
B WL_LED# B
3 1 PCIE_WAKE#_MINI-Card
<14,20,31> PCIE_WAKE#

Media Key +5V +3V CN5

<30,31> MX4_WL# 1
WL_LED 2
<30,31> MX2_WWW# 3
<30,31> MX1_EMAIL# 4
R540 R536 5
<30,31> MX5_BT#
3G/TV MINI CARD R131
10K_4
R132
10K_4 0 0
<21> BT_LED
<30,31> MX3_3G#
3G MINI_LED
6
7
8
<31> TV_KEY 9
+1.5V +3G_VDD +3G_VDD CN8 MY0 10
+3G_VDD 11
R525 0_4 MMB_A_KEY 1
<31> A_KEY 2 12
CN34 MINIPCI EXP_Aces R526 0_4 MMB_MX0_E_KEY#
<30,31> MX0_E_KEY# 3
CVBS 51 52 R527 0_4 MMB_MY0
Reserved +3.3V <30,31> MY0 4
FAN_OT# 49 50 L19 LZA10-2ACB104MT TBCLK_R Aces 88501-120N
Reserved GND <31> TB2CLK 5
Audio Right 47 48 L18 LZA10-2ACB104MT TBDATA_R
Reserved +1.5V <31> TB2DATA 6
Audio Left 45 46 +3V_MMB
Reserved LED_WPAN# +5V_MMB 7 +3VPCU
43 Reserved LED_WLAN# 44 8
41 42 3G_LED# R274 0_4 3G MINI_LED#
Reserved LED_WWAN# R539 Aces 88501-0801
39 Reserved GND 40
37 38 USBP8+_D RP37 3 4 0X2 USBP8+ <13>
Reserved USB_D+

1
C 35 36 USBP8-_D 1 2 C
GND USB_D- USBP8- <13> 0_4
PCIE_TXP2 33 34
PCIE_TXN2 PETp0 GND PDAT_SMB_3G R253 0_4 PDAT_SMB
31 PETn0 SMB_DATA 32 47K
29 30 PCLK_SMB_3G R477 0_4 PCLK_SMB
GND SMB_CLK
27 GND +1.5V 28 2
PCIE_RXP2 25 26 10K
PERp0 GND

3
PCIE_RXN2 23 24
PERn0 +3.3Vaux PLTRST# Q32 Q35
21 GND PERST# 22
S-Video-Y 19 20 2N7002 DTA114YUA
3G_ON <31>

3
S-Video-C UIM_C4 W_DISABLE# +3VSUS
17 UIM_C8 GND 18 <17,31,32> ACIN 2

15 16 UIM_VPP +3V
CLK_PCIE_TV GND UIM_VPP UIM_RST
13 REFCLK+ UIM_RST 14
CLK_PCIE_TV# 11 12 UIM_CLK CN4

1
REFCLK- UIM_CLK UIM_DATA
9 GND UIM_DATA 10
7 8 UIM_PWR AC_IN 1
+5V_TV-CARD CLKREQ# UIM_PWR
5 Reserved +1.5V 6 2
3 4 CLK_PCIE_TV 3
GND

GND

Reserved GND CLK_PCIE_TV <2>

1 2 CLK_PCIE_TV# 4
WAKE# +3.3V CLK_PCIE_TV# <2> <30> CAPSLED
PCIE_RXP2 5
PCIE_RXP2 <13> <30> NUMLED
CVBS PCIE_RXN2 6
PCIE_RXN2 <13> <30> IDE_LED
53

54

+1.5V S-Video-Y PCIE_TXP2 7

PCIE_TXP2 <13> <31> NBSWON#
S-Video-C R512 PCIE_TXN2 UIM_VPP 8
PCIE_TXN2 <13>
R511 UIM_RST 9
R510 150/F_4 UIM_CLK 10
FAN_OT# <21>
150/F_4 UIM_DATA 11
C428 150/F_4 UIM_PWR 12
.1U_4 13
<14,23,31> LID591#
Q18 14
DTA114YUA
+3V Close near Mini-card connector +3V Aces 88501-1401-14P-L
D +5V R270 D
L27 FBJ3216HS800_12 +3G_VDD 1 3 3G MINI_LED

47K
L59 FBJ3216HS800_12 +5V_TV-CARD CN30
S-Video-Y 10 9 330_4

10K
C432 C383 C421 C438 C442 S-Video-C 8 7
10U/10V/X5R_8 10U/10V/X5R_8 .1U_4 .1U_4 10P-50V_4 + C193 C213 R507 CVBS 6 5
R508 Audio Right 4 3
PROJECT : ZD1

2
10U_8 .1U_4 150/F_4 R509 Audio Left 2 1
150/F_4 3G MINI_LED#
150/F_4 3G MINI_LED#
TV_CONNECTOR Quanta Computer Inc.
Size Document Number Rev
MINI PCI-E card/3G/TV/Media Key B

Date: Monday, December 11, 2006 Sheet 22 of 38

1 2 3 4 5 6 7 8

WWW.AliSaler.Com
 5 4 3 2 1

CN44
New card CN9 NEW CARD'S POWER SWITCH
29 GND5 26 GND1 GND29 29
26 PCIE_TXP1 25 30
GND1 PCIE_TXN1 PETp0 GND30
<13> PCIE_TXP1 25 PETp0 24 PETn0
24 23 U33
<13> PCIE_TXN1 PETn0 PERP3 GND2 QFN-TPS2231RGP
23 GND2 22 PERp0 REV:B MODIFY
<13> PCIE_RXP1
C381
C376
PERP3
PERN3
22 PERp0
PERN3 21 PERn0 +3V 2 3.3VIN 3.3VOUT 3 +NEW_3V
1.3A
<13> PCIE_RXN1 21 PERn0 20 GND3 4 3.3VIN 3.3VOUT 5
20 CLK_PCIE_NEW_C 19
GND3 REFCLK+
<2> CLK_PCIE_NEW_C 19 REFCLK+
CLK_PCIE_NEW_C#
NC_EN#
18 REFCLK- +3V_S5 17 AUXIN AUXOUT 15 +NEW_3VAUX
275mA
<2> CLK_PCIE_NEW_C# 18 REFCLK- 17 CPPE#
<13> NC_EN# 17 CPPE# +NEW_3V
16 CLKREQ# +1.5V 12 1.5VIN 1.5VOUT 11 +NEW_1.5V
650mA
16 CLKREQ# 15 +3.3V1 14 1.5VIN 1.5VOUT 13
+NEW_3V 15 14
D +3.3V1 PERST# +3.3V2 PLTRST#_NEW D
14 +3.3V2 13 PERST# 6 *SYSRST# *STBY# 1
PERST# 13 +NEW_3VAUX 12 20 10 CPPE#
PERST# +3.3VAUX *SHDN# *CPPE#
+NEW_3VAUX 12 +3.3VAUX +NEW_1.5V
11 WAKE# *CPUSB# 9 CPUSB#
TI : AL002231001
11 WAKE# 10 +1.5V1 18 *RCLKEN
+NEW_1.5V 10 +1.5V1 NEW_SMDATA
9 +1.5V2 16 NC PERST# 8 PERST#
RICOH : AL005538001
9 +1.5V2 8 SMB_DATA 7 GND OC# 19
NEW_SMDATA
NEW_SMCLK
8 SMB_DATA
NEW_SMCLK 7 SMB_CLK 21 GNDPAD GMT : AL000577008
7 SMB_CLK 6 RESERVED1
6 RESERVED1 5 RESERVED2
5 RESERVED2 4 CPUSB#
4 USBP5+_R 3
R441 0_4 USBP5+_R 3 CPUSB# USBP5-_R USB_D+
<13> USBP5+ USB_D+ 2 USB_D-
R442 0_4 USBP5-_R 2 1 +3V
<13> USBP5- USB_D- GND4
1 GND4
30 GND6

2
*Taitwun_NEW CARD
*Aces_NEW CARD
3 1 PLTRST#_NEW
CN43 <13,14,17,20,22,24,29..31> PLTRST# Q37
2N7002
26 GND1 GND29 29
PCIE_TXP1 25 30 REV:B MODIFY
PCIE_TXN1 PETp0 GND30 +NEW_3V
24 PETn0
23 GND2
PERP3 22
PERN3 PERp0
21 PERn0
20 +3V_S5 +3V +1.5V
GND3

4
2
CLK_PCIE_NEW_C 19
CLK_PCIE_NEW_C# REFCLK+ +NEW_3VAUX RP41
18 REFCLK-
NC_EN# 17 Q30
CPPE# C599 C581 C582 C598 C597 10KX2_4
16 CLKREQ#
+NEW_3V 15 C351 2N7002E
+3.3V1

2
C .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 C
14

3
1
PERST# +3.3V2 .1U_4
13 PERST#
+NEW_3VAUX 12 3 1 NEW_SMDATA
+3.3VAUX <2,14,16,22> PDAT_SMB
11 WAKE#
+NEW_1.5V 10 +1.5V1
9 +1.5V2
NEW_SMDATA 8
NEW_SMCLK SMB_DATA +NEW_3V
7 SMB_CLK
6 +NEW_3V +NEW_1.5V
RESERVED1 Q29
5 RESERVED2
4 CPUSB#
USBP5+_R 3 C579 C354 C357 C348 C344 2N7002E
USB_D+

2
USBP5-_R 2 USB_D- 4.7U_8 .1U_4 .1U_4 4.7U_8 .1U_4
1 GND4
3 1 NEW_SMCLK
<2,14,16,22> PCLK_SMB
FOX_EXPCARD

LID SWITCH HDMI

+5V

+5V
CN21

SHELL1 20
+3V HDMITX2P 19
<17> HDMITX2P D2+
D35 D34 18
HDMITX2N D2 Shield
NV suggestion near <17> HDMITX2N 17 D2-
HDMITX1P 16
B BAS316 BAS316 HDMI connector <17> HDMITX1P
15
D1+ B
HDMITX1N D1 Shield
<17> HDMITX1N 14 D1-
R194 R354 R353 HDMITX0P 13
<17> HDMITX0P D0+
10K_4 12 D0 Shield
HDMITX0N 11 23
<17> HDMITX0N D0- GND
HDMICLK+ 10
<17> HDMICLK+ CK+
DISPON D11 BAS316 2K_4 2K_4 9 22
<18> DISPON LID591# <14,22,31> CK Shield GND
HDMICLK- 8
<17> HDMICLK- CK-
L39 7
HDMI_DDCCLK CE Remote
<17> MXM_HDMI_DDCCLK 6 NC
HDMI_DDCCLK 5
HDMI_DDCCLK DDC CLK
220R@100MHZ HDMI_DDCDATA 4
HDMI_DDCDATA DDC DATA
C515 3
D10 BAS316 R190 IV@0_4 GND
INT_LVDS_BLON <6> 2 +5V
*.1U_4 HDMI_HP_A R359 EV@10K_4 HP_DET 1
<17> HDMI_HP_A HP DET
R189 EV@0_4 21
EV_LVDS_BLON <17> SHELL2
HDMI monitor default have PU
R356 HDMI CON
R192 *1K_4 to 5V.So ZY3 PD for level EV@10K_4
change.And serial R for
L38
current limited
HDMI_DDCDATA
<17> MXM_HDMI_DDCDATA
R191
220R@100MHZ
<demo circuit> C516 +5V U26 *RClamp0514M_AG
HDMITX0P 1 HDMITX0P
100K_4
Crestline suggest 100K
*.1U_4 HDMITX0N 1 10 10 HDMITX0N
2 9 9
G73 suggest 10K(ZS1 Default) 3
2
(Need confirm with Max) C632 C631 C633 HDMI_HP_A VCC GND 8 HDMI_HP_A
4 4 7 7
5 5 6 6
.1u_4 .1u_4 .1u_4
3

A A

2 EC_FPBACK# <31>

Q12
1

U27 *RClamp0514M_AG U25 *RClamp0514M_AG

DTC144EU HDMITX2P 1 1 10 10
HDMITX2P HDMICLK+ 1 1 10 10
HDMICLK+ PROJECT : ZD1
HDMITX2N 2 HDMITX2N HDMICLK- HDMICLK-
2 9 9 2 2 9 9
3 GND 8 3 GND 8
HDMITX1P 4
VCC
4 7 7
HDMITX1P HDMI_DDCCLK 4
VCC
4 7 7
HDMI_DDCCLK Quanta Computer Inc.
HDMITX1N 5 HDMITX1N HDMI_DDCDATA HDMI_DDCDATA
5 6 6 5 5 6 6 Size Document Number Rev
NEW CARD/HDMI/LID B
Date: Monday, December 11, 2006 Sheet 23 of 38
5 4 3 2 1
 1 2 3 4

SATA HDD2
SATA HDD1

Main
CN33 CN32

GND23 23 GND23 23

GND1 1 GND1 1
A A
RXP 2 SATA_TXP1 <12> RXP 2 SATA_TXP0 <12>
RXN 3 SATA_TXN1 <12> RXN 3 SATA_TXN0 <12>
GND2 4 GND2 4
5 SATA_RXN1_C C361 .01U_4 SATA_RXN1 <12> 5 SATA_RXN0_C C583 .01U_4 SATA_RXN0 <12>
TXN SATA_RXP1_C C370 .01U_4 TXN SATA_RXP0_C C585 .01U_4
TXP 6 SATA_RXP1 <12> TXP 6 SATA_RXP0 <12>
GND3 7 GND3 7

8 +3.3VSATA1 R229 0_8 +3V +3.3VSATA1 +3.3VSATA1 +3.3VSATA1 8 +3.3VSATA2 R464 0_8 +3V +3.3VSATA2 +3.3VSATA2 +3.3VSATA2
3.3V 3.3V
3.3V 9 3.3V 9
3.3V 10 3.3V 10
11 C400 C401 C390 11 C601 C595 C592
GND 4.7U-6.3V_8 4.7U-6.3V_8 .1U-10V_4 GND 4.7U-6.3V_8 4.7U-6.3V_8 .1U-10V_4
GND 12 GND 12
GND 13 GND 13
14 HDDA5V 14 HDDB5V
5V 5V
5V 15 5V 15
5V 16 5V 16
GND 17 GND 17
RSVD 18 RSVD 18
GND 19 GND 19
20 R246 0_8 HDDA5V 20 R476 0_8 HDDB5V
12V +5V 12V +5V
12V 21 + 12V 21

+
12V 22 12V 22
C439 C425 C415 C417 C416 C418 C621 C614 C617 C618 C606 C607
24 150U-6.3V_7343 4.7U-6.3V_8 .1U-16V_4 .1U-16V_4 .01U-16V_4 .01U-16V_4 24 150U-6.3V_7343 4.7U-6.3V_8 .1U-16V_4 .1U-16V_4 .01U-16V_4 .01U-16V_4
GND24 GND24
SA@C16654-122A4-L_Serial_ATA SA@C16654-122A4-L_Serial_ATA

B B

ODD (PATA)

CN28
SUYIN-ODDREV-800194MR050S110ZL
+5V
1 2
IDERST# 3 4 PDD8
ODDLED# R193 10K_4 PDD7 5 6 PDD9
PDD6 7 8 PDD10 +3V +5V
PDD5 9 10 PDD11
PDD4 11 12 PDD12
13 14

2
C PDD3 PDD13 R199 C
PDD2 15 16 PDD14
PDD1 17 18 PDD15 10K_4
PDD0 19 20 PDDREQ
21 22 PDDREQ <12>
PDIOR# PLTRST# 1 3 IDERST#
23 24 PDIOR# <12> <13,14,17,20,22,23,29..31> PLTRST#
PDIOW# Q13 DTC144EU
<12> PDIOW# 25 26
PIORDY PDDACK#
<12> PIORDY 27 28 PDDACK# <12>
IRQ14
<12> IRQ14 29 30
PDA1 PDIAG# R195 *10K_4
31 32 +5V
PDA0 PDA2
PDCS1# 33 34 PDCS3#
<12> PDCS1# 35 36 PDCS3# <12>
ODDLED#
<30> IDELED# 37 38
+5V_ODD 39 40 +5V_ODD L49 0_8
41 42 +5V
43 44 PDD[15..0] <12>
+

C293 C292 C281 C285 C556

RCSEL 45 46
47 48 PDA[2..0] <12>
1000P_4 .1U_4 .1U_4 .1U_4 150U/6.3V_7343
51
52

R176 49 50
51
52

470_4

D D

<OrgName>

<OrgAddr1>
<OrgAddr2> PROJECT : ZD1
<OrgAddr3>
<OrgAddr4>
Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com 1 2 3
Date:
SATA-HDD & PATA-ODD
Monday, December 11, 2006
4
Sheet 24 of 38
B
 5 4 3 2 1

USB USBPWR1

C536 +5V_S5
C537
100U_3528 1000P_4
CN17
+5V_S5 CN23
U28 1 5 1
USBPWR1 RP11 3 USBP0-_R 1 5 USBON#
2 IN1 OUT3 8 <13> USBP0- 4 0X2_4 2 2 6 6 2
3 7 1 2 USBP0+_R 3 7 USBP1- RP40 1 2 0X2_4 USBP1-_R 3 6
IN2 OUT2 <13> USBP0+ 3 7 <13> USBP1-
6 4 8 USBP1+ 3 4 USBP1+_R 4 7
D OUT1 4 8 <13> USBP1+ D
<31> USBON# 4 EN# 5
1 Alltop_USB
GND R389 *6.34K/F
9 GND-C OC# 5
U29 Aces 87212-05G0
TPS2061DGNR CM1293-04SO
1 6 +5V_S5
CH1 CH4
2 VN VP 5

3 CH2 CH3 4
+5V_S5 Close near CN17
USBPWR2

C508 C38
EMI SOLUTION
C37
1000P_4 C637
3 4 USBP3-_R *100U_3528 100U_3528 1000P_4
<13> USBP3-
1 2 USBP3+_R CN18
<13> USBP3+
+5V_S5 U20 RP2 0X2_4 1 5
U3 CM1293-04SO 2 6
2 8 USBPWR2 1 6 +5V_S5 3 7
IN1 OUT3 CH1 CH4
3 IN2 OUT2 7 4 8
OUT1 6 2 VN VP 5 9 10
4 EN# 11 12
1 GND 3 CH2 CH3 4
9 5 R41 *6.34K/F +5V_S5 +5V_S5 +5V_S5
GND-C OC# Suyin_dual_usb
G548A2P8U RP3 1 2 0X2_4 USBP2+_R C507
<13> USBP2+
3 4 USBP2-_R
<13> USBP2-
C534 C509
.1U_4 .1U_4
C .1U_4 C

HOLES
HOLE28 HOLE2 HOLE20 HOLE25 HOLE5
*H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 HOLE9 HOLE13 HOLE14 HOLE17 HOLE18 HOLE10
2 5 2 5 2 5 2 5 2 5 *H-C236D142P2-8 *H-C236D142P2-8 *H-C236D142P2-8 *H-C236D142P2-8 *H-C236D142P2-8 *H-C236D142P2-8
3 6 3 6 3 6 3 6 3 6 2 5 2 5 2 5 2 5 2 5 2 5
4 7 4 7 4 7 4 7 4 7 3 6 3 6 3 6 3 6 3 6 3 6
4 7 4 7 4 7 4 7 4 7 4 7
8
1
9

8
1
9

8
1
9

8
1
9

8
1
9

8
1
9

8
1
9

8
1
9

8
1
9

8
1
9

8
1
9
ADOGND ADOGND
ADOGND

HOLE27 HOLE11 HOLE1 HOLE19 HOLE22

*H-TC256BC315D118P2-8 *H-TC256BC315D118P2-8 *H-TC354BC256D118P2-8 *H-TC256BC217D118P2-8 *H-TC256BC315D118P2-8
B B
2 5 2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6 3 6 HOLE24 HOLE23 HOLE8 HOLE12
4 7 4 7 4 7 4 7 4 7 *H-TC98BC197D59P2 *H-TC98BC197D59P2 *H-TC98BC197D59P2 *H-TC98BC197D59P2
2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6
8
1
9

8
1
9

8
1
9

8
1
9

8
1
9

4 7 4 7 4 7 4 7

8
1
9

8
1
9

8
1
9

8
1
9
HOLE26 HOLE29
*H-TC256BC315D118P2-8 *H-TC236BC217D118P2-8
2 5 2 5
3 6 3 6
4 7 4 7
HOLE7 HOLE16 HOLE6 HOLE15 HOLE21
*H-C236D142P2 *H-C236D142P2 *H-C236D142P2 *H-C236D142P2 *H-C236D142P2
8
1
9

8
1
9

2 5 2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6 3 6
ADOGND ADOGND 4 7 4 7 4 7 4 7 4 7
8
1
9

8
1
9

8
1
9

8
1
9

8
1
9
ADOGND
HOLE3 HOLE4
*H-TC197BC98D59P2-8 *H-TC197BC98D59P2-8
2 5 2 5
3 6 3 6
4 7 4 7
8
1
9

8
1
9

A A
PAD1 PAD2

*EMIPAD *EMIPAD

PROJECT : ZD1
1

Quanta Computer Inc.

Size Document Number Rev
USB/HOLE B

Date: Monday, December 11, 2006 Sheet 25 of 38

5 4 3 2 1
 5 4 3 2 1

CODEC(ALC268) LINE OUT Amplifier R313 10K

C463 47P_4

Gain = -(Rf/Ri)
+5V +5V_ADO U18

L30 TI321611U480_1206
FRONT-L C465 4.7U-6.3V_8 R312 10K 4 - 5 HPL
INL OUTL HPL <27>
C441 C443 C479 C487 C501 C469 + 9
.1U-10V_4 10U-10V_8 .1U-10V_4 .1U-10V_4 .1U-10V_4 10U-10V_8 NC1
D +3V_AVDD 3 SVDD NC2 11 D
MIC1-VREFO-R 15 12
MIC1-VREFO-R <27> PVDD NC3
+3V_AVDD R296 100K_4 14
NC4
6 SVSS SGND 2
ADOGND MIC2-VREFO +NVDD 10 13
MIC2-VREFO <27> NVDD PGND
<27> MUTE# 1 2 TPAD 17
D24 MTW355
+3V R276 0 MIC1-VREFO-L 1 2 1412MUTE# 1
MIC1-VREFO-L <27> <27> SECNTL SHDNR#
D23 *MTW355 16 ADOGND
SHDNL#
+ 7
R275 *0 +AZA_VDD FRONT-R C477 4.7U-6.3V_8 R324 10K OUTR
+1.5V 8 INR -
FRONT-L +5V_ADO

FRONT-R C502 10U-10V_8 G1412

C449
C450
4.7U .1U-10V_4 ADOGND L28 C478 47P_4

36

35

34

33

32

31

30

29

28

27

26

25
+3V 1 2 +3V_AVDD
U19 BLM11A601S R325 10K HPR
HPR <27>

VREF
FRONT-R

FRONT-L

NC

MIC1-VREFO-R

GPIO1

MIC1-VREFO-L

AVSS1

AVDD1
Sense B

LINE1-VREFO
MIC2-VREFO
C435 C468 C447
*10U-10V_8 10U-10V_8 .1U-10V_4
R523 268@0_4 MONO_OUT_268
37 24 LINE1-R
<27> MONO_OUT_L MONO-OUT LINE1-R LINE1-R <27>
ADOGND ADOGND
+5V_ADO 38 23 LINE1-L C460 4.7U/6.3V
AVDD2 LINE1-L LINE1-L <27>
SURR-L 39 22 MIC1-R +NVDD
<27> SURR-L HP-OUT-L MIC1-R MIC1-R <27> +3V_AVDD +NVDD U35
C C
ADOGND R329 20K/F 40 21 MIC1-L
JDREF MIC1-L MIC1-L <27>
1 VOUT C+ 6
<27> SURR-R SURR-R 41 20 C489 .1U-10V_4 C630
HP-OUT-R CD-R 1412MUTE#
4.7U/6.3V 2 VIN /SHDN 5
ADOGND 42 19 C483 .1U-10V_4
AVSS2 CD-GND ADOGND 3 4
<27> MONO_OUT_L 43 NC
Acer ALC268&888 CD-L 18 C481 .1U-10V_4
ADOGND
C- GND

44 17 MIC2_INT_R C474 1U-16V G5930

<27> MONO_OUT_R NC MIC2-R MIC2_INTR1 <27>
Change C19 to 4.7u ADOGND
45 16 MIC2_INT_L C466 1U-16V
NC MIC2-L MIC2_INTL1 <27>
46 DMIC-CLK NC 15

<27> EAPD EAPD R538 268@0_4 EAPD_268 47 14

DMIC-1/2/GPIO0

DMIC-3/4/GPIO3

EAPD NC
SPDIF_OUT 48 SENSEA R346 20K/F
SDATA-OUT
<27> SPDIF_OUT SPDIFO Sense A 13 MIC1_JD <27>

SDATA-IN
VR

PCBEEP
RESET#
BIT-CLK
MXM_SPDIF_OUT R347 10K/F
DVDD1

DVDD2
DVSS1

DVSS2
LINEIN_JD <27>

SYNC
R311 268@0_4
R349 5.1K/F VR1
LINE_JD <27>
DIGVOL_UP 2 1
<31> DIGVOL_UP A C
1

10

11

12
4 4

DIGVOL_DN 3 5
+3V <31> DIGVOL_DN B 5

7
SPDIF_OUT_888

+AZA_VDD

VR_XRE094_NOBLE

B PCBEEP C453 1U-16V BEEP_1 R273 10K_4 PCSPK B

PCSPK <14>
MUTE_888

C440 R279
100P-50V 1K_4
R335 0 +3V +1.5V
C444 C452 R537
10U-10V_8 .1U-10V_4
ADOGND
888@0_4 R16 R4 +3V_S5
Tied at one point only 0 *0
MDC
BIT_CLK268

ACZ_SDIN268

under the codec or CN2

ACZ_RST#_AUDIO <12,27>
near the codec 1 GND RSV 2
C5
ACZ_SDOUT_MDC 3 4
<12> ACZ_SDOUT_MDC AC_SDO RSV
5 6 .1U-10V_4
ACZ_SYNC_AUDIO <12> GND 3.3V
ACZ_SYNC_MDC 7 8
<12> ACZ_SYNC_MDC AC_SYNC GND
R3 22_4 MDC_SDIN1 9 10
<12> ACZ_SDIN1 AC_SDI GND
R281 22_4 11 12
ACZ_SDIN0 <12> <12> ACZ_RST#_MDC AC_RST# AC_BCLK BIT_CLK_MDC <12>
15 GND GND 16
R282 22_4
BIT_CLK_AUDIO <12>
+5V +5V_ADO MDC
C451 22P-50V_4
U16 C7 R2
R271 *0 4 3 *10P-50V_4 *22_4
VEN VOUT ACZ_SDOUT_AUDIO <12>
5 EAPD
GND

VIN
ADJ

C6
R302 *10P-50V_4
A A
*36K_4 R524 888@0_4 MXM_SPDIF_OUT MXM_SPDIF_OUT <17>
2

*G961-18ADJTEU(SOT89-5)

The pin2 of ALC888 define MXM_SPDIF_OUT

R301 PROJECT : ZD1
*12K_4

Quanta Computer Inc.

Size Document Number Rev
Vo=1.2*(R371+R372)/R371= 4.8V ADOGND REALTEK ALC268&888/MDC/VR B

Date: Monday, December 11, 2006 Sheet 26 of 38

5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

SYSTEM LINE OUT/SPDIF

Speaker Amplifier +5V_ADO

+3V_AVDD
C471 1U-16V
+3V_SPD
R316 0_4 SPDIFO
C485 C446 <26> SPDIF_OUT
ADOGND LINEOUT_JD:
10U-10V_8 .1U-10V_4 HP not insert->H
SECNTL HP insert->L
SECNTL <26>
C473 Pin5 connect to Pin3 on Jack
.1U-10V_4
Gain = -(Rf/Ri) BLACK
ADOGND

15

14

23
4

6
8
U17 B1A: Add R588 & R591 CN40
C494 2.2U/10V_8 SURR-L-1 R336 10K SURR-L-2 1 20 LINEOUT_JD 5 9

CT
VDD3

SECNTL
LVDD
RVDD

NC
D <26> SURR-L LIN1 VOL D
4
C476 2.2U/10V_8 SURR-R-1 R300 10K 18 10
<26> SURR-R RIN1
SURR-R-2 HPL R342 75/F_4 L35 BK1608LL121 HPL_SYS 3
<26> HPL
INSPKL+ R330 10K 2 13 ADOGND HPR R341 75/F_4 L34 BK1608LL121 HPR_SYS 2
LIN2 IN1/IN2 <26> HPR
C484 330P_4 17 1
+5V_ADO INSPKR+ R315 10K RIN2 INSPKR+
ROUT+ 19
C470 330P_4 12 INSPKR- R340 R343 C491 C492 7 LED
ROUT- INSPKL+ *1K_4 *1K_4 470P-50V_4 470P-50V_4 SPDIFO Drive
LOUT+ 24 8
4.7U/6.3V C445 16 7 INSPKL- 6 IC
ADOGND RBYPASS LOUT-
3 LBYPASS
R328 4.7U/6.3V C482 2SJ1371-0010A1_SPDIF

THRMPAD
100K_4 ADOGND ADOGND

GND/HS
GND/HS
GND/HS
GND/HS
1441 MUTE R327 0_4 5 Normal OPEN Jack
1441 MUTE SHDN
R298 0_4 11 SE/BTL
3

Q22 G1441 +5V_ADO

25
22
21
10
9
MUTE# 2 ADOGND D33
1 Q21
LINEOUT_JD ME2347
2N7002 3

+3V 1 3 +3V_SPD
1

2
ADOGND
ADOGND +3V_AVDD *DA204U ADOGND

2
LINEOUT_JD
EC MUTE
1 2 R283
<31> AMP_MUTE#
D22 MTW355 10K_4 Foxconn DFTJ10FR470 2FB5441-BKMC-7F
+5V
1 2 MUTE# Singatron DFTJ10FR437 2SJ1371-0010A1
<26> EAPD MUTE# <26>
D20 MTW355 LINE_JD
LINE_JD <26>
1 2 R595
<12,26> ACZ_RST#_AUDIO

3
D21 MTW355 10K_4
C +5V Q43 2N7002 C

SPEAKER R594
2

3
CN35 22K_4 Q42 2N7002
INSPKR- L55 BK1608LL121 INSPKR-N

1
INSPKR+ L56 BK1608LL121 INSPKR+N 1 R337 *0 LINEOUT_JD
25 2
INSPKL- L57 BK1608LL121 INSPKL-N R284 *0
INSPKL+ L58 BK1608LL121 INSPKL+N 36 C472 .1U-10V_4
4 C459 1000P-50V_4
C623 C624 C625 C622

1
47P-50V_4 47P-50V_4 47P-50V_4 47P-50V_4 ADOGND

85204-04001_SPEAKER-CON

ADOGND

SYSTEM LINE IN/SUBWOOFER MIC

R345 2.2K_4 CN41
<26> MIC1-VREFO-L
1 7
C493 2.2U MIC1_L1 L33 BK1608LL121 MIC1_L 2
<26> MIC1-L
6
BLUE R339 2.2K_4 MIC1_R1 L32 BK1608LL121 MIC1_R 3
<26> MIC1-VREFO-R
CN42 <26> MIC1_JD 4
1 7 C497 2.2U 8
<26> MIC1-R
C503 4.7U-6.3V_8 LINE1-L_1 L37 BK1608LL121 LINEINL_SYS 2 5
<26> LINE1-L
6 2SJ-T351-S11
C504 4.7U-6.3V_8 LINE1-R_1 L36 BK1608LL121 LINEINR_SYS 3
B <26> LINE1-R B
4 C498 C496 Normal OPEN Jack
<26> LINEIN_JD
8 470P-50V_4 470P-50V_4
C500 C505 5

470P-50V_4 470P-50V_4 2SJ-T351-S15

ADOGND

Normal OPEN Jack

For ESD close to audio out connecter
ADOGND +5V_ADO

+5V_ADO D32
D31

1
INT MIC array 1
MIC1_JD
LINEIN_JD R333 4.7K_4 3
3 1 2 MIC2-VREFO <26>
D29 MTW355 ADOGND
2
2 *DA204U
*DA204U MIC2_INTR1
MIC2_INTR1 <26>
For ESD close to audio out connecter ADOGND

+5V
Singatron DFTJ06FR732 2SJ-T351-S15 C486 Singatron DFTJ06FR741 2SJ-T351-S11
*22P-50V_4
Foxconn DFTJ06FRA21 JA6233L-U3T4-7F Foxconn DFTJ06FRA39 JA6233L-P3T4-7F
CN16 Alltop DFTJ06FR902 C12107-906A9-L Alltop DFTJ06FR899 C12107-D06A9-L
1441 MUTE 1 ADOGND
2
<26> MONO_OUT_L 3 6
<26> MONO_OUT_R CN11
4 7 MIC2_INTR1
5 1
SUBWOOFER 2 MIC2_INTL1 R285 0
6 3
4 R332 4.7K_4 1 2 MIC2-VREFO <26>
85204-0200L_INT_MIC D30 MTW355 ADOGND
A A
ADOGND
ADOGND MIC2_INTL1
MIC2_INTL1 <26>

C488
*22P-50V_4

ADOGND PROJECT : ZD1

Size Document Number Rev
Quanta
AMP /AUDIO JACK CONN Computer Inc. B

Date: Monday, December 11, 2006 Sheet 27 of 38

5 4 3 2 1
 5 4 3 2 1

+3V +3V R5C832 : AJ5C8320H26 +3V 1394

R5C833 : AJ5C8330H05
U32B
C570 C610 C603 C564 C364 C580
C566 10 67 TPBIAS0
4.7U .01u/16V_4 .1u/16V_4 .01u/16V_4 4.7U .01u/16V_4 .01u/16V_4 VCC_PCI1 VCC_3V
20 VCC_PCI2
27 C399 C591 R459 R461 C584 C588
VCC_PCI3
32 VCC_PCI4
41 .01u/16V_4 4.7U FW^.33u/10V FW^.01u/16V_4
VCC_PCI5 FW^56.2/F_4 FW^56.2/F_4
128 VCC_PCI6
61 VCC_RIN
VCC_ROUT_832 16 VCC_ROUT1 RN18 FW^0_4P2R
34 VCC_ROUT2
D C571 C572 64 TPA0P 3 4 L1394_TPA0+ D
C593 C586 VCC_ROUT3 AS CLOSE AS TPA0N L1394_TPA0-
114 VCC_ROUT4 1 2
.01u/16V_4 .01u/16V_4 .47u/6.3V_4 .47u/6.3V_4 120 POSSIBLE TO
VCC_ROUT5 TPB0N L1394_TPB0-
R5C833 3 4
86 TPB0P 1 2 L1394_TPB0+
VCC_MD RN13 FW^0_4P2R COMMON MODE CHOKE
R467 R465 NEAR CONN.
<13> AD[31..0] GND1 4
GND2 13 CN26
AD31 125 22 FW^56.2/F_4 FW^56.2/F_4
AD30 AD31 GND3
126 AD30 GND4 28 5
AD29 127 54 L1394_TPB0- 1
AD28 AD29 GND5 L1394_TPA0-
1 AD28 GND6 62 3 6
AD27 2 63 1394_COM L1394_TPA0+ 4
AD26 AD27 GND7 L1394_TPB0+
3 AD26 GND8 68 2
AD25 5 118 +3V R468 C590 7
AD24 AD25 GND9
6 AD24 GND10 122 8
AD23 9 FW^270p_4 SUYIN_1394
AD22 AD23 FW^5.1K/F_4
11 AD22 When HWSPND# is
AD21 12 99 38M030006-00
AD20 14
AD21 AGND1
102 R469 controlled by system, the IEEE 1394 CONN 6POLE R/A 787956-1 DIP AMP
AD19 AD20 AGND2 10K_4 pull-up resistor(R755)
15 AD19 AGND3 103 <MOUNTED>
AD18 17 107 dose not need to apply.
AD17 AD18 AGND4
REQ2# AD25 AD16
18 AD17 AGND5 111
GNT2# INTA#,B# AD15
19 AD16
36 AD15
AD14 37
AD25 R208 150/F_4 PCM_IDSEL AD13 AD14
38 AD13
AD12 39
AD11 AD12
40 AD11

PCI / OTHER
AD10 42 69 832_SUS#
AD9
AD8
AD7
43
44
AD10
AD9
AD8
HWSPND#
+3V 5 IN 1 CARD READER
46 AD7
AD6 47 58 R463 10K_4
AD5 AD6 MSEN
PowerOnReset for VccCore 48 AD5
AD4 49 55 R458 10K_4
AD3 AD4 XDEN
When GRESET# is controlled by system, 50 AD3
C AD2 51 R460 100K_4 Memory Card Power Supply C
the pull-up resistor(R762) and AD1 52
AD2
57 R462 *100K_4 * NOT Use EEPROM : PU +3V
capacitor(C492) do not need to apply. AD0 AD1 UDIO5
53 AD0 * Use EEPROM : PD
PAR 33
<13> PAR PAR VCC_XD VCC_XD
CBE3# 7 65 SCL_CARD R242
<13> CBE3# C/BE3# UDIO3
CBE2# 21 59 SDA_CARD Q16
<13> CBE2# C/BE2# UDIO4

1
+3V CBE1# 35 CN37 10K_4
<13> CBE1# C/BE1#
PCLK_PCM CBE0# 45 56 23 2N7002
<13> CBE0# C/BE0# UDIO2 (4)SD-VCC
PCM_IDSEL 8 XD_D0/MS_D0/SD_D0 25 Q17
IDSEL XD_D1/MS_D1/SD_D1 (7)SD-DAT0 MC_PWR_CTRL_0#
UDIO1 60 29 (8)SD-DAT1 1 3 2
R473 REQ0# 124 XD_D2/MS_D2/SD_D2 10 33
<13> REQ0# REQ# (9)SD-DAT2 (18)XD-VCC
100K_4 GNT0# 123 72 SERIRQ XD_D3/MS_D3/SD_D3 11 ME2347
<13> GNT0# GNT# UDIO0/SRIRQ# SERIRQ <14,30,31> (1)SD-DAT3
R457 FRAME# 23 XD_RE#/CLK 24 34 XD_CDZ
<13> FRAME#

2
GRST#_832 IRDY# FRAME# XD_WE#/MS_BS/SD_CMD (5)SD-CLK (19)XD-CD XD_R/B#/SD_WP#
<13> IRDY# 24 12 1

3
*22_4 TRDY# IRDY# SD_CDZ (2)SD-CMD (2)XD-R/B XD_RE#/CLK
25 36 2
<13> TRDY#
DEVSEL# 26
TRDY# XD_R/B#/SD_WP# 35
SD-CD (3)XD-RE
3 XD_CE# 30mil
<13> DEVSEL# DEVSEL# SD-WP (4)XD-CE VCC_XD
C613 STOP# 29 115 INTA# 4 XD_CLE MC_PWR_CTRL_0
<13> STOP# STOP# INTA# INTA# <13> (5)XD-CLE
C578 PERR# 30 5 XD_ALE
<13> PERR# PERR# (6)XD-ALE
.22u/10V_4 SERR# 31 116 INTB# 6 XD_WE#/MS_BS/SD_CMD R240 C412
<13> SERR# SERR# INTB# INTB# <13> (7)XD-WE
*22p_4 7 XD_WPO#
GRST#_832 +3V (8)XD-WP 100K_4 4.7u/6.3V
71 GBRST#
PCIRST# 119 14 8 XD_D0/MS_D0/SD_D0
<13,22> PCIRST# PCIRST# (9)MS-VCC (10)XD-D0
L53 XD_D0/MS_D0/SD_D0 19 9 XD_D1/MS_D1/SD_D1
PCLK_PCM 1394_AVCC XD_D1/MS_D1/SD_D1 (4)MS-DATA0 (11)XD-D1 XD_D2/MS_D2/SD_D2
Ground guard <2> PCLK_PCM 121 PCICLK 20 (3)MS-DATA1 (12)XD-D2 26
BK1608HS220_6_1A XD_D2/MS_D2/SD_D2 18 27 XD_D3/MS_D3/SD_D3
PCI_PME# XD_D3/MS_D3/SD_D3 (5)MS-DATA2 (13)XD-D3 XD_D4 VCC_XD
<13> PCI_PME# 70 PME# TEST 66 16 (7)MS-DATA3 (14)XD-D4 28
C594 C589 C373 C587 XD_RE#/CLK 15 30 XD_D5
CLKRUN# MS_CDZ (8)MS-SCLK (15)XD-D5 XD_D6
<14,31> CLKRUN# 117 CLKRUN# 17 (6)MS-INS (16)XD-D6 31
4.7U .1u/16V_4 .01u/16V_4 1000p_4 XD_WE#/MS_BS/SD_CMD 21 32 XD_D7
R5C832T_V00 (2)MS-BS (17)XD-D7
U32A C409 C407
13 37 C410
(3)SD/(1)MS/(1)XD-GND SDIO-GND .01u/16V_4 .01u/16V_4
AVCC_PHY1 98 22 (6)SD/(10)MS/(9)XD-GND SDIO-GND1 38
106 .01u/16V_4
C604 1394_XIN AVCC_PHY2
94 XI AVCC_PHY3 110
112 CARD_READER_TTN_R013-B10-XX-C ADOGND
AVCC_PHY4
2

FW^22p_4
Y5 113 TPBIAS0
FW^24.576MHz TPBIAS0 TPB0N
B TPBN0 104 B
105 TPB0P
1

C605 1394_XOUT 95 TPBP0 TPA0N VCC_XD VCC_XD

XO TPAN0 108
109 TPA0P VCC_XD VCC_XD
FW^22p_4 TPAP0 CN36
23 CN38
XD_D7 XD_D0/MS_D0/SD_D0 (4)SD-VCC
MDIO17 87 25 (7)SD-DAT0 21 SD-VCC
C602 FIL0_PWR 96 92 XD_D6 XD_D1/MS_D1/SD_D1 29 XD_D0/MS_D0/SD_D0 31
FIL0 MDIO16 XD_D5 XD_D2/MS_D2/SD_D2 (8)SD-DAT1 XD_D1/MS_D1/SD_D1 SD-DAT0
MDIO15 89 10 (9)SD-DAT2 (18)XD-VCC 33 34 SD-DAT1
FW^.01u/16V_4 91 XD_D4 XD_D3/MS_D3/SD_D3 11 XD_D2/MS_D2/SD_D2 9 38
MDIO14 XD_D3/MS_D3/SD_D3 XD_RE#/CLK (1)SD-DAT3 XD_CDZ XD_D3/MS_D3/SD_D3 SD-DAT2 XD-VCC
MDIO13 90 24 (5)SD-CLK (19)XD-CD 34 11 SD-DAT3
R466 REXT 101 93 XD_D2/MS_D2/SD_D2 XD_WE#/MS_BS/SD_CMD 12 1 XD_R/B#/SD_WP# XD_RE#/CLK 25 2 XD_CDZ
REXT MDIO12 XD_D1/MS_D1/SD_D1 SD_CDZ (2)SD-CMD (2)XD-R/B XD_RE#/CLK XD_WE#/MS_BS/SD_CMD SD-CLK XD-CD XD_R/B#/SD_WP#
MDIO11 81 36 SD-CD (3)XD-RE 2 15 SD-CMD XD-R/B 3
FW^10K/F_4 82 XD_D0/MS_D0/SD_D0 XD_R/B#/SD_WP# 35 3 XD_CE# SD_CDZ 39 4 XD_RE#/CLK
MDIO10 SD-WP (4)XD-CE XD_CLE XD_R/B#/SD_WP# SD-C/D XD-RE XD_CE#
(5)XD-CLE 4 41 SD-WP XD-CE 5
C596 VREF_PWR 100 75 XD_WPO# +3V 5 XD_ALE 6 XD_CLE
VREF MDIO05 (6)XD-ALE XD-CLE
IEEE1394/SD

88 XD_WE#/MS_BS/SD_CMD 6 XD_WE#/MS_BS/SD_CMD 19 7 XD_ALE

FW^.01u/16V_4 MDIO08 XD_ALE (7)XD-WE XD_WPO# SD-VSS1 XD-ALE XD_WE#/MS_BS/SD_CMD
MDIO19 83 (8)XD-WP 7 29 SD-VSS2 XD-WE 8
85 XD_CLE 40 13 XD_WPO#
MDIO18 XD_CE# R472 XD_D0/MS_D0/SD_D0 SD-GND XD-WP
MDIO02 78 14 (9)MS-VCC (10)XD-D0 8
GUARD GND 77 XD_R/B#/SD_WP# XD_D0/MS_D0/SD_D0 19 9 XD_D1/MS_D1/SD_D1 12 23 XD_D0/MS_D0/SD_D0
MDIO03 10K_4 XD_D1/MS_D1/SD_D1 (4)MS-DATA0 (11)XD-D1 XD_D2/MS_D2/SD_D2 XD_D0/MS_D0/SD_D0 MS-VCC XD-D0 XD_D1/MS_D1/SD_D1
20 (3)MS-DATA1 (12)XD-D2 26 22 MS-DATA0 XD-D1 27
80 SD_CDZ 2 1 XD_CDZ XD_D2/MS_D2/SD_D2 18 27 XD_D3/MS_D3/SD_D3 XD_D1/MS_D1/SD_D1 24 30 XD_D2/MS_D2/SD_D2
MDIO00 D40 BAS316 XD_D3/MS_D3/SD_D3 (5)MS-DATA2 (13)XD-D3 XD_D4 XD_D2/MS_D2/SD_D2 MS-DATA1 XD-D2 XD_D3/MS_D3/SD_D3
16 (7)MS-DATA3 (14)XD-D4 28 20 MS-DATA2 XD-D3 32
79 MS_CDZ 2 1 XD_RE#/CLK 15 30 XD_D5 XD_D3/MS_D3/SD_D3 16 33 XD_D4
MDIO01 D39 BAS316 MS_CDZ (8)MS-SCLK (15)XD-D5 XD_D6 XD_RE#/CLK MS-DATA3 XD-D4 XD_D5
17 (6)MS-INS (16)XD-D6 31 14 MS-SCLK XD-D5 35
84 MS_SD_CLK R470 56.2/F_4 XD_RE#/CLK XD_WE#/MS_BS/SD_CMD 21 32 XD_D7 MS_CDZ 18 36 XD_D6
MDIO09 MC_PWR_CTRL_0 (2)MS-BS (17)XD-D7 XD_WE#/MS_BS/SD_CMD MS-INS XD-D6 XD_D7
MDIO04 76 26 MS-BS XD-D7 37
74 TP_XD_LED# T76 10
MDIO06 MS-VSS1
97 RSV MDIO07 73 13 (3)SD / (1)MS / (9)XD-GND GND1 37 28 MS-VSS2
22 (6)SD / (10)MS / (19)XD-GND GND2 38 42 GND XG-GND1 1
43 GND XD-GND2 17
> 1 ms >60 ns
R5C832T_V00 *CARD_READER_PLASTREN-CM47-X-38P-L ADOGND *PROCONN-MXP038-A0-4010
ADOGND

VCC +3V * NOT Use EEPROM :

R759 : installed
R760,U43,C505 : NOT installed
A * Use EEPROM : A
GRST# R234 R230 R760,U43,C505 : installed
R759 : NOT installed
PRST# > 100 ns
*10K_4 *10K_4 U12
SDA_CARD 5 1
SCL_CARD SDA A0
6 SCL A1 2
A2 3
HWSPND# 7 +3V
WP
4 GND VCC 8 PROJECT : ZD1
PCLK(33MHz) *FW^24LC08 C408
Quanta Computer Inc.
*FW^.1u/16V_4
Size Document Number Rev
R5C832/833(5IN1/1394) B

Date: Monday, December 11, 2006 Sheet 28 of 38

5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

ROBSON
DIAMOND-LAKE ASIC
+3V RBS_AVDDL RBS_AVDDT RBS_AVDD +1.2V

U8
18 AVDD VDD1 3
24 AVDDT VDD2 8
27 AVDDL VDD3 13
VDD4 41
2 45 +3V PLACEMENT NOTE:
D VDDO1 VDD5 +1.5V D
15 47
38
VDDO2 VDD6 PLACE TERMINATION RESISTERS
VDDO3
52 VDDO4 VDDR1 46
INTEL NAND FLASH AT 10% TO 25% DISTANCE FROM
61 48 PLACE CLOSE TO NAND FALSH R120
69
VDDO5 VDDR2
44 DIS_REG12 R160 1K_4 1K_4 NAND FLASH.
GND_PAD DIS_REG12
POWER
WE#[0]_RBS R126 33_4 WE#[0]_R 54 57 NF_IO_00 U7
NF_WE[0]# NF_IO[0] NF_IO_01 READY_BUSY_RBS
55 NF_WE[1]# NF_IO[1] 59 7 R/B1# PRE/VSS 38
62 NF_IO_02 6 29 NF_IO_00_R R113 33_4 NF_IO_00
RE#[0]_RBS R158 33_4 RE#[0]_R NF_IO[2] NF_IO_03 CE#[0]_RBS NC24 I/O[0] NF_IO_01_R R114 33_4 NF_IO_01
39 NF_RE[0]# NF_IO[3] 64 9 CE1# I/O[1] 30
40 66 NF_IO_04 10 31 NF_IO_02_R R115 33_4 NF_IO_02
NF_RE[1]# NF_IO[4] NF_IO_05 RE#[0]_RBS NC25 I/O[2] NF_IO_03_R R116 33_4 NF_IO_03
NF_IO[5] 68 8 RE# I/O[3] 32
CE#[0]_RBS R159 33_4 CE#[0]_R 42 4 NF_IO_06 ALE_RBS 17 41 NF_IO_04_R R119 33_4 NF_IO_04
NF_CE[0]# NF_IO[6] NF_IO_07 CLE_RBS ALE I/O[4] NF_IO_05_R R121 33_4 NF_IO_05
43 NF_CE[1]# NF_IO[7] 6 16 CLE I/O[5] 42
49 58 NF_IO_08 WE#[0]_RBS 18 43 NF_IO_06_R R122 33_4 NF_IO_06
NF_CE[2]# NF_IO[8] NF_IO_09 WP#_RBS WE# I/O[6] NF_IO_07_R R125 33_4 NF_IO_07
50 NF_CE[3]# NF_IO[9] 60 19 WP# I/O[7] 44
63 NF_IO_10
CLE_RBS R161 33_4 CLE_RBS_R NF_IO[10] NF_IO_11
51 NF_CLE NF_IO[11] 65 1 NC1 NC14 26
ALE_RBS R128 33_4 ALE_RBS_R 53 67 NF_IO_12 2 33
WP#_RBS NF_ALE NF_IO[12] NF_IO_13 NC2 NC15
56 NF_WP# NF_IO[13] 1 3 NC3 NC16 34
READY_BUSY_RBS 37 5 NF_IO_14 4 35
R141 330_4 DISK_BUSY_R NF_RB NF_IO[14] NF_IO_15 NC4 NC17
1 2 33 BUSY NF_IO[15] 7 5 NC5 NC18 39
11 NC6 NC19 40
LED1 NAND I/F 14 45
*LED_G_LTST-C190KGKT TP_RBS_RSVD2 TP_RBS_RSVD7 NC7 NC20
T16 9 RSVD[02] RSVD[07] 31 T36 15 NC8 NC21 46
T15 TP_RBS_RSVD3 10 32 TP_RBS_RSVD8 T33 23 47
TP_RBS_RSVD4 RSVD[03] RSVD[08] NC9 NC22
T18 11 RSVD[04] 24 NC10 NC23 48
T17 TP_RBS_RSVD5 12 28 TP_RBS_RSVD9 T31 25 20
TP_RBS_RSVD6 RSVD[05] RSVD[09] TP_RBS_RSVD10 +3V NC11 DNU1
T19 14 RSVD[06] RSVD[10] 21 T22 27 NC12 DNU2 21
20 TP_RBS_RSVD11 T23 28 22
R117 1.4K/F_4 ISET_RBS RSVD[11] TP_RBS_RSVD12 NC13 DNU3
19 ISET RSVD[12] 34 T38
C C
12 VCC1 VSS1 13
RESERVED 37 36
TP_RBS_RSVD0 C159 C158 C157 VCC2 VSS2
<2> PCIE_CLK_RBS 30 CLKP RSVD[00] 16 T20
29 17 TP_RBS_RSVD1 T21 FLASH(48P)512MB
<2> PCIE_CLK_RBS# CLKN RSVD[01] .01U_4 .1U_4 1U_4 <Part Number>
CLOCK TSOP48-ZS1
26 23 TXP_RBS_R C162 .1U_4
<13> PCIE_TXP5 RXP TXP PCIE_RXP5 <13>
25 22 TXN_RBS_R C160 .1U_4 U6
<13> PCIE_TXN5 RXN TXN PCIE_RXN5 <13>
7 R/B1# PRE/VSS 38
6 29 NF_IO_08_R R87 33_4 NF_IO_08
CLRREQ#_RBS CE#[0]_RBS NC24 I/O[0] NF_IO_09_R R89 33_4 NF_IO_09
T39 35 CLKREQ# 9 CE1# I/O[1] 30
36 10 31 NF_IO_10_R R93 33_4 NF_IO_10
<13,14,17,20,22..24,30,31> PLTRST# PERST# NC25 I/O[2]
RE#[0]_RBS 8 32 NF_IO_11_R R98 33_4 NF_IO_11
PCIE I/F ALE_RBS RE# I/O[3] NF_IO_12_R R102 33_4 NF_IO_12
17 ALE I/O[4] 41
Diamond_Lake CLE_RBS 16 42 NF_IO_13_R R103 33_4 NF_IO_13
<Part Number> WE#[0]_RBS CLE I/O[5] NF_IO_14_R R104 33_4 NF_IO_14
18 WE# I/O[6] 43
QFN68-8X8-4-69P-ZS1 WP#_RBS 19 44 NF_IO_15_R R108 33_4 NF_IO_15
WP# I/O[7]
1 NC1 NC14 26
NF_IO_00 2 33
NC2 NC15
3 NC3 NC16 34
R123
PLACE AS CLOSE AS POSSIBLE TO *10K_4
4
5
NC4 NC17 35
39
NC5 NC18
DIAMOND-LAKE ASIC. STUFF: INDICATES A 2KB VIRTUAL PAGE. => 256MB 11
14
NC6 NC19 40
45
DESTUFF: INDIACTESS A 4KB VIRTUAL PAGE => 512MB & 1024MB NC7 NC20
15 NC8 NC21 46
23 NC9 NC22 47
24 NC10 NC23 48
25 NC11 DNU1 20
+3V 27 21
NC12 DNU2
28 NC13 DNU3 22
B B
12 VCC1 VSS1 13
37 VCC2 VSS2 36
+1.2V C128 C129 C126
+3V +1.5V FLASH(48P)512MB
.01U_4 .1U_4 1U_4 <Part Number>
TSOP48-ZS1

C164 C188 C210 C150 C207 C209 C148 C205 C149 C208 C206

.1U_4 .01U_4 .1U_4 1U_4 .1U_4 1U_4 .1U_4 .1U_4 .01U_4 .01U_4 1U_4

LAYOUT NOTE:
ANY VIA ADDED BENEATH THE NAND FLASH
NEEDS TO HAVE A SOLDERMASK ON IT.

+3V RBS_AVDD +1.5V RBS_AVDDT +1.5V RBS_AVDDL

L16 L17 L20

BK1608HS800-T BK1608HS800-T BK1608HS800-T

C147 C152 C146 C155 C161 C166 C167 C168 C186 C179 C180 C181

.1U_4 .01U_4 .1U_4 1U_4 .1U_4 .01U_4 .1U_4 1U_4 .1U_4 .01U_4 .1U_4 1U_4

A A

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
ROBSON B

Date: Monday, December 11, 2006 Sheet 29 of 38

5 4 3 2 1
 5 4 3 2 1

INT K/B
+3V

CN6 CPU FAN

MY15 MY0 1 R351
<31> MY15
MY14 MY1 2
<31> MY14
MY13 MY2 3 10K_4
<31> MY13
MY12 MY3 4
<31> MY12 +3VSUS
MY11 MY4 5
<31> MY11
MY10 MY5 6
<31> MY10
MY9 MY6 7 <31> FANSIG
<31> MY9 CN20
MY8 MY7 8
<31> MY8
MY7 MY8 9 RP5 U23
<31> MY7
MY6 MY9 10 10 1 MX4_WL# 2 3 TH_FAN_POWER
<31> MY6 +5V VIN VO 1
MY5 MY10 11 MX3_3G# 9 2 MX5_BT# 5
D <31> MY5 GND 2 D
MY4 MY11 12 MX2_WWW# 8 3 MX6 CPUFAN#_ON 1 6
<31> MY4 <3> CPUFAN#_ON /FON GND 3
MY3 MY12 13 MX1_EMAIL# 7 4 MX7 7 C512 C511 C510
<31> MY3 GND
MX7 MY13 14 MX0_E_KEY# 6 5 4 8
<31> MX7 <31> CPUFAN# VSET GND
MX6 MY14 15 10U_8 .01U_4 *.01U_4
<31> MX6
MY2 MY15 16 10KX8 G995 FAN_CON
<31> MY2
MX5_BT# MY16 17
<22,31> MX5_BT#
MX4_WL# MY17 18
<22,31> MX4_WL#
MX3_3G# MX7 19
<22,31> MX3_3G#
MX2_WWW# MX6
<22,31> MX2_WWW#
MY1 MX5_BT#
20
21
FANPWR = 1.6*VSET
<31> MY1
MY0 MX4_WL# 22
<22,31> MY0
MX1_EMAIL# MX3_3G# 23
<22,31> MX1_EMAIL#
MX0_E_KEY# MX2_WWW# 24
<22,31> MX0_E_KEY#
MY16 MX1_EMAIL# 25
<31> MY16
MY17 MX0_E_KEY# 26
<31> MY17

Aces 88502-2641

LED DEBUG PORT

+3V +3V +3V +3V

C C

R323 R322 R318 R334 EC Debug Port Reserved for LPC debug card
10K_4
10K_4 10K_4 330_4
IDE_LED
IDE_LED <22> +3VPCU LAD0
<12,22,31> LAD0 T87
3 <12,22,31> LAD1
LAD1
T88
D26 BAS316 1 LAD2
<24> IDELED# 1 <12,22,31> LAD2 T89
EC_SOUT_CR_DEBUG 2 LAD3
<31> EC_SOUT_CR_DEBUG 2 <12,22,31> LAD3 T90
D25 BAS316 2 EC_SWD_DEBUG 3
<12> SATA_LED# Q23 <31> EC_SWD_DEBUG 3 <2,22> PCLK_DEBUG T91
4 LFRAME#
4 <12,22,31> LFRAME# T92
PLTRST#
<13,14,17,20,22..24,29,31> PLTRST# T93
2N7002E CN10 SERIRQ
<14,28,31> SERIRQ T94
*ACES_88231-0400
1

Reserve to debug

+3VPCU

LED2
R344 330_4 1 4
B SUSLED# <31> B
2 3 PWRLED# <31>
LED_DUAL_LIGHT

T/P
LED3
R338 330_4 1 4 BATLED1# <31>
2 3 +5V
BATLED0# <31>
LED_DUAL_LIGHT +5V

L45
BLM21P300S

+TPVDD
R386 R385
10K_4 10K_4 C529 .1U-16V_4 CN7

L44 LZA10-2ACB104MT TPDATA_R 1

<31> TBDATA 2
L43 LZA10-2ACB104MT TPCLK_R
<31> TBCLK 3
4
Q15 Q14 5
DTA114YUA DTA114YUA 6
+3V +3V ACES_88058-0601
R235 R221
A NUMLED CAPSLED A
1 3 NUMLED <22> 1 3 CAPSLED <22>
47K

47K

330_4 330_4
10K

10K

<OrgName>
2

NUMLED# <OrgAddr1>
<31> NUMLED#
<31> CAPSLED#
CAPSLED# <OrgAddr2> PROJECT : ZD1
<OrgAddr3>
<OrgAddr4>
Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com 5 4 3 2
Date:
FAN,LED,KB,DEBUG PORT,TP
Monday, December 11, 2006
1
Sheet 30 of 38
B
 5 4 3 2 1

+3VPCU +3VPCU
1/13 Comfirm by vendor mail: SM BUS PU +3VPCU
1/13 Vendor mail: +3V VDD must power up after VCC/AVCC
Dedicate cap for AVCC MBCLK R448 4.7K_4
MBDATA R438 4.7K_4
L51 BLM18AG601SN1 +A3VPCU MXM_CLK R544 4.7K_4
1/13 Comfirm by vendor mail: MXM_DATA R535 4.7K_4
C600 C384 C387 VBAT for keep PLL power let power up can quick.
C406 C402
.1U_4 .1U_4 10U_8 If no VBAT will switch to VCCpower.
.1U_4 10U_8 If PLL no power will cause boot time delay. +3V

8769AGND 08/10 FAE: CRT_SENSE# R223 4.7K_4

115

102
C569 C568 C608 C609 C567 C404

19
46
76
88

80
0.1UF

4
D U10 DIGVOL_UP C634 .1U_4 D
10U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 11/23 Reduce switch
On/Off noise

AVCC

VDD
VCC1
VCC2
VCC3
VCC4
VCC5

VBAT
I/O ADDRESS SETTING
DIGVOL_DN C636 .1U_4

<12,22,30> LFRAME# 3 LFRAME AD0/GPI90 97 MTEMP <32> I/O Address

126 98 TEMP_ABAT T56
<12,22,30> LAD0 LAD0 AD1/GPI91
<12,22,30> LAD1 127 LAD1 AD2/GPI92 99 BADDR1-0 Index Data
<12,22,30> LAD2 128 LAD2 A/D AD3/GPI93 100
1 108 DIGVOL_UP 00 XOR TREE TEST MODE
<12,22,30> LAD3 LAD3 AD4/GPIO05 DIGVOL_UP <26>
PCLK_591 2 96 DIGVOL_DN
<2> PCLK_591 LCLK AD5/GPIO04 DIGVOL_DN <26>
01 CORE DEFINED
PCLK_591 8
<14,28> CLKRUN# CLKRUN/GPIO11/HGPIO02
DA0/GPI94 101 CC-SET <32> 10 2Eh 2Fh
<12> GATEA20 121 GA20 DA1/GPI95 105 CPUFAN# <30>
D/A DA2/GPI96 106 TV_KEY <22> 11 164Eh 164Fh
R232 122 107 DA3_GPI97 T86
<12> RCIN# KBRST DA3/GPI97
*22_4 SHBM=0: Enable shared memory with host BIOS
D15 BAS316 SCI#_uR 29 LPC
<14> SCI# ECSCI
GPIO01 64 ACIN <17,22,32>
6 95 BADDR0 CCD_POWERON R239 10K_4
<30> CAPSLED# LDRQ/GPIO24/HGPIO01 GPIO03 NBSWON# <22>
GPIO06/HGPIO06 93 LID591# <14,22,23>
C394 124 94 BADDR1 SOUT_CR_DEBUG R237 *10K_4
<22> A_KEY LPCPD/GPIO10/HGPIO00 GPIO07/HGPIP07 SUSB# <7,14>
*10P_4 GPIO23 119 EC_FPBACK# <23>
PLTRST# 7 109 SHBM RF_EN R218 10K_4
<13,14,17,20,22..24,29,30> PLTRST# LREST GPIO30 SUSLED# <30>
GPIO31 120 PWRLED# <30>
<30> NUMLED# 123 PWUREQ GPIO32 65 BATLED0# <30>
GPIO33 66 BATLED1# <30> 1/13 Comfirm by vendor mail :
<14,28,30> SERIRQ 125 SERIRQ GPIO36 15 VRON <34> Disabled ('1') if using FWH device on LPC.
16 MAINON <35..37>
08/10 FAE: SMI DOESN'T NEED DIODE 9
GPIO40
17
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
<14> KBSMI# SMI GPIO42/TCK
C
GPIO GPIO43/TMS 20 AMP_MUTE# <27> C
GPIO44/TDI 21

ACER ID
MX0_E_KEY# 54 22
<22,30> MX0_E_KEY# KBSIN0 GPIO45 SUSON <36,37>
MX1_EMAIL# 55 23 +3VPCU
<22,30> MX1_EMAIL# KBSIN1 GPIO46/TRST U9
MX2_WWW# 56 24
<22,30> MX2_WWW# KBSIN2 GPO47/JEN0
MX3_3G# 57 25 MBCLK 6 1
<22,30> MX3_3G# KBSIN3 GPIO50/TDO D/C# <32> SCL A0
MX4_WL# 58 26 MBDATA 5 2
<22,30> MX4_WL# KBSIN4 GPIO51 S5_ON <33,37> SDA A1
MX5_BT# 59 27 3
<22,30> MX5_BT# KBSIN5 GPIO52/RDY A2
MX6 60 28 HWPG
<30> MX6 KBSIN6 GPIO53
61 91 DNBSWON#_uR D17 BAS316 7 8
<30> MX7 KBSIN7 GPIO81 DNBSWON# <14> WP VCC
GPO82/HGPIO00/TRIS 110 BT_POWERON# <21> GND 4
<22,30> MY0 53 KBSOUT0/JENK GPO84/HGPIO01/BADDR0 112 CCD_POWERON <21>
52 T55 24LC08 C343
<30> MY1 KBSOUT1/TCK CCD_POWERON ACITVE LO => HI
51 08/10 FAE: ADD TP FOR DEBUG .1U_4
<30> MY2 KBSOUT2/TMS
50 31 R419 *0
<30> MY3 KBSOUT3/TDI TA1/GPIO56 PCIE_WAKE# <14,20,22>
<30> MY4 49 KBSOUT4 KB TA2/GPIO20 117
<30> MY5 48 KBSOUT5/TDO TB1/GPIO14/HGPIO4 63 FANSIG <30>
<30> MY6 47 KBSOUT6/RDY
<30> MY7 43 KBSOUT7 TIMER A_PWM0 32 EC_L_BKLT_CTRL <18>
<30>
<30>
MY8
MY9
42
41
KBSOUT8
KBSOUT9
A_PWM1/GPIO21
B_PWM0/GPIO13
118
62
USBON# <25>
3G_ON <22>
SPI FLASH +3VPCU +3VPCU
<30> MY10 40 KBSOUT10
39 U11
<30> MY11 KBSOUT11
38 84 SPI_SDI_uR 2 8
<30> MY12 KBSOUT12/GPIO64 SPI_DI/GPIO77 CRT_SENSE# <13,19> SO VDD
37 SPI 83 RF_EN R233
<30> MY13 KBSOUT13/GPIO63 SPI_DO/GPO76/SHBM RF_EN <22>
36 82 SPI_SDO_uR_R 5 7
<30> MY14 KBSOUT14/GPIO62 SPI_SCK/GPIO75 CELL-SET <32> SI HOLD
35 10K_4 C393
<30> MY15 KBSOUT15/GPIO61/XOR_OUT
MY16 34 SPI_SCK_uR_R 6 3 .1U_4
<30> MY16 KBSOUT16/GPIO60 SCK WP
MY17 33 75 RSMRST#_uR R222 0
<30> MY17 KBSOUT17/GPIO57/HGPIO03 IRRX1/GPIO72 RSMRST# <14>
73 SPI_CS0#_uR 1 4
IRRX2_IRSL0/GPIO70 SUSC# <14> CE VSS
74 PWROK_EC_uR R215 0_4
IRTX/GPIO71 PWROK_EC <14,17>
MBCLK 70 IR 113 W25X80VSSIG
<3,32> MBCLK SCL1 SIN_CR/CIRRX/GPIO87
MBDATA 69 14
B <3,32> MBDATA SDA1 GPIO34/CIRRX2 CIRRX2 <21> B
MXM_CLK 67 SMB 114 1/13 Comfirm by vendor mail :
<17> MXM_CLK SCL2 CIRTX/GPIO16/HGPIO04
MXM_DATA 68 111 SOUT_CR_DEBUG R238 0_4 If the Southbridge enables 'Long Wait Abort' by default, the
<17> MXM_DATA SDA2 SOUT_CR/GPO83/BADDR1 EC_SOUT_CR_DEBUG <30>
flash device should be 50MHz (or faster)
72 86 SPI_SDI_uR
<30> TBCLK PSCLK1 F_SDI
71 87 SPI_SDO_uR R596 22 SPI_SDO_uR_R
<30> TBDATA PSDAT1 F_SDO
BUTTON ON KEYBOARD MATRIX
10 FIU 90 SPI_CS0#_uR 12/4 Add 22 ohm for EMI
<22> TB2CLK PSCLK2/GPIO26 F_CS0
11 PS/2 92 SPI_SCK_uR R597 22 SPI_SCK_uR_R
<22> TB2DATA PSDAT2/GPIO27 F_SCK
12 PSCLK3/GPIO25
13 81 SWD_DEBUG R453 0_4
PSDAT3/GPIO12 SWD/GPIO66 EC_SWD_DEBUG <30>
8768_32KX1 77 30 uR_TP_CLKOUT T46 MX0_E_KEY#
32KX1/32KCLKIN CLKOUT/GPIO55 MX0_E_KEY# <22,30>
MX1_EMAIL#
MX1_EMAIL# <22,30>
85 VCC_POR# R224 4.7K_4 +3VPCU MX2_WWW#
VCC_POR MX2_WWW# <22,30>
MX3_3G#
VCORF

MX3_3G# <22,30>
AGND
GND1
GND2
GND3
GND4
GND5
GND6

R212 20M 8768_32KX2 79 104 VREF_uR R236 0_4 +A3VPCU MX4_WL#

32KX2 VREF MX4_WL# <22,30>
MX5_BT#
MX5_BT# <22,30>
R216 WPC8769LDG 0~AVCC power for DA pin MY0
MY0 <22,30>
5
18
45
78
89
116

103

44

0810 FAE: 33K/F power reference

CHECK X'TAL'S FOOTPRINT
2
1

VCORF_uR

CEECK RESULT: OK 08/10 FAE:

Y2 08/14 FAE:
ADD ONE GAD PAD UNDER X'TAL,
Please connect VREF(uRider pin104) to
C363 AND KEEP CLEANCE. +A3VPCU instead of +3VPCU.
C356 32.768KHZ
3
4

5.6P_4 5.6P_4 C346

+3V L26 1U

GPIO PIN PU INTERNAL KEYBOARD STRIP SET

1/13 Comfirm by vendor mail : HZ0603B601R-00
Connect to AGND
+3VPCU
A 8769AGND R214 +3VPCU A
10K_4
TV_KEY R518 4.7K_4 MY0 R437 10K_4
8769AGND
D12 BAS316 HWPG <OrgName>
<37> HWPG_CPUIO
08/10 FAE:
<33> HWPG_3/5VPCU
D14 BAS316 L83 CAN CHANGE FROM BEAD TO SHORT. <OrgAddr1> PROJECT : ZD1
R521 <OrgAddr2>
D16 BAS316 BUT, PLEASE PUT AGND & 32K CAP & AVCC CAP AT ONE POINT. <OrgAddr3>
<35> HWPG_1.05V
0_4 <OrgAddr4> Quanta Computer Inc.
D13 BAS316 ZS1 STILL USE BEAD FOR SAFE.
<36> HWPG_1.8V
Size Document Number Rev
MPWROK <7,14>
PC8769L & FLASH B

Date: Monday, December 11, 2006 Sheet 31 of 38

5 4 3 2 1
 5 4 3 2 1

0.02_3720 PQ31 PQ32

VA PR82 FDS6675BZ FDS6675BZ
HI0805R800R-00_8 VIN
PJ1 PL10 1 1 8 1 8
4 3 1 2 2 7 2 7
3 2 3 6 PC151 3 6
2 PC152 PC84 PC85 5 2200P/100V_6 5
1 2200P/100V_6 PL13 .1U/X7R-25V_8 .1U/X7R-25V_8 PD9 PR11

1P

2P
PDS1040S PC11 PR9 PC97
33K

4
POWER_JACK 0.1U/X7R-25V_8 220K/F 0.1U/X7R-25V_8
HI0805R800R-00_8
PD3
D modify 1208 RB500V D
PC82
PC87 .1U/X7R-25V_8 1 6 PR6
.1U/X7R-25V_8 modify 1208 10K
PR8 2 5 PR7 0
D/C# <31>
220K/F
PD4 3 4

3
PR12
ACIN_1 2 1 PQ2
<17,22,31> ACIN
IMD2AT108
10K/F CSIN 2
ZD12V
PR10 PQ1
PR13 CSIP 2N7002E
6.8K/F 10K/F 2200P/100V_6
modify 1208 PC153

1
PC12 2.2U/X5R-10V_8 VIN
ISL6251_VDD 1 2 PC90 10U/X6S-25V_1206

PR5
18 PR90 PL12
4.7 PC92 .1U/X7R-25V_8 HI0805R800R-00_8
PC7
0.1U/X7R-50V PC6 4.7U/Y5V-10V_8
CSIN_1 ISL6251_VDDP 1 2

C C
PD10

19

20

15
1
RB500V
PQ29

CSIP

CSIN

VDD

VDDP
PR4 2.2/F FDS6900AS
CSOP CSOP_1 21 PR83 2.7 PC93 .1U/X7R-25V_8
CSOP 6251B_2 6251B_1 G1 VA3
16 8 D1 1
BOOT modify 1208

2
PC8 7 S1/D2 D1 2 PR81
1U/X7R-25V_8 17 ISL6251_UGATE PL11 0.03_3720

1
CSON UGATE G2 3 SIL104R-100PF
22 CSON 6
6251LR
1 2 BAT-V
18 ISL6251_PHASE 5 S2 4
PHASE PC154
2200P/100V_6

1P

2P
14 ISL6251_LGATE
PC9 LGATE PC89
23 ACPRN
0.1U/X7R-50V .01U/X7R-50V
PGND 13

DCIN 24 12 VREF
PC86 DCIN GND PC94 PC91
CSOP 10U/X6S-25V_1206 10U/X6S-25V_1206
MTEMP <31>
11 PR100 PR91
CN15 HI0805R800R-00_8 PR87 6251ACSET 2 VADJ 19.6K/F *514K/F CSON
100P/NPO-50V_4 PL8 130K/F ACSET
1 MBAT+ BAT-V
2 ACLIM 10
TEMP_MBAT 3 VADJ Float = 4.2V / CELL
3 EN

VCOMP
ICOMP
CELLS

CHLIM
B 8 4 B

VRFE
PL9 PR86 ACLIM
9 5

ICM
HI0805R800R-00_8 10K/F
6
1

PC2 PC1 PC83

7 PR102 PR85

6251ICOMP 5

9
SUYIN_BATTERY 47P/NPO-50V_4 47P/NPO-50V_4 PR157 100K/F PU1 33K/F *514K/F
+3VPCU
2

0.1U/X7R-50V ISL6251A
PR1
10mil 100_4 ISL6251_VDD 6251EN VREF

6251VCOMP1
PR2
100_4 MBCLK <3,31> modify 1208 PR15 10K/F CC-SET <31>
LIM = 1/R2(((0.05/VREF=2.39)VACLM)+0.050)
MBDATA MBDATA <3,31> 6251CELLS_1
TEMP_MBAT PC96 CURRNT LIMIT POINT = 3.79A
1

PR14 10K/F 100P/NPO-50V_4

1

PD2 PD1 PR158 3.79A=1/0.02((0.05/2.365)Vaclm+0.05)

3

ZD5.6V PC3 PR110 PC95

ZD5.6V 100K/F .01U/X7R-50V 10K/F 6.8N/X7R-50V
PR16 Vaclm=1.4592V
2
2

6251CELLS_2 2 6251VCOMP2
ICMNT
3

PR92
modify 1208 PQ34 10K/F *100_4
ADP WATT monitor output
2N7002E
1

PR111
<31> CELL-SET 2
100K/F
For 62W setting. Vicm will 1.3V
PQ35 PC101 PC102
PR105 2N7002E 100P/NPO-50V_4 .01U/X7R-50V
100K/F
1

A A

PC13
*3300P/X7R-50V_4

PROJECT : ZD1
Quanta Computer Inc.
CELL-SET = Hi ----> Cells = VDD ---->4S Size Document Number Rev
CELL-SET = Low ----> Cells = GND ---->3S Custom B
ISL6251 CHARGER
Date: Monday, December 11, 2006 Sheet 32 of 38
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

MAIND
MAIND <36,37>

SUSD
SUSD <37>

<3> SYS_SHDN# 1 2

ISL6236_3V
PR146
PL5 0_4 PL18
D VIN VIN D

HI0805R800R-00_8 VL HI0805R800R-00_8

VL

2
PC138
PR142 4.7U/X7R-10V

1
390K_4

1
3V_DL
PR145 PR140 PR139
39K/F_4 0_4 PC135 0_4 PC81 PC144
PC73 PC72 PC74 PC136 1U/10V_6 0.1U/X7R-50V 10U/X6S-25V_1206

1
0.1U/X7R-50V 2200P/X7R-50V_4 10U/X6S-25V_1206 0.1U/X7R-50V PC80 PC145

2
2

D1

D1
S2

G2
PC139 2200P/X7R-50V_4 10U/X6S-25V_1206
.01U/X7R-16V_4 PC140
0.1U/X7R-50V

1
3V5V_EN PQ23
2 1 FDS6900AS

2
8
7
6
5

S1/D2
2
PR138 PR143 3V_DH OCP : 6.25A

G1
*0_4 PR141

8
7
6
5
4
3
2
1
4 5V_DH 150K/F_4 *0_4 +3VPCU

8
PQ25 3V_DH PL6

LDOREFIN
LDO

ONLDO
VIN
RTC

VCC
TON
REF
OCP: 12A 2.5uH_7.5A

1
FDS8884 3VPCU
PR70 3V_LX
+5VPCU +5VPCU
9 32 287K/F_4
PL7 BYP REFIN2
10 31 1 2

1
2
3
1.5uH_10A OUT1 PU7 ILIM2
C 11 FB1 OUT2 30 C
5V_LX 1 2 12 29
PR151 267K/F_4 DDPWRGD_R 13 ILIM1 ISL6236 SKIP# DDPWRGD_R PC65 PC76
PGOOD1 PGOOD2 28
2

8
7
6
5
PR148 3V5V_EN 14 27 3V5V_EN PR147 +
*0_4 EN1 EN2
15 DH1 DH2 26 0
PC78 16 25 0.1U/X7R-50V 330U/6.3V_6X5.7
+ 5V_DL LX1 LX2
4 37 PAD
PC79 36

SECFB
1

PAD

PGND
330U/6.3V_6X5.7 PC143

BST1

BST2
0.1U/X7R-50V

GND
VDD
PAD
PAD
PAD

DL1

DL2
10U/X6S-25V_1206 PC75 PC141
1

0.1U/X7R-50V 0.1U/X7R-50V PR149

PR144 PQ27 PR152 *0

35
34
33

17
18
19
20
21
22
23
24
0_4 PR75 1/F
1
2
3

FDS6690AS 1/F 1 2
Add on 9/27 1 2 3V_DL
2

PD7 VL
PC137 PR78 0 DDPWRGD_R PR150 0
2 HWPG_3/5VPCU <31>
0.1U/X7R-50V
PC66
3 1U/10V_6

3
1
OCP:12A CHN217 PC58
PD6 0.1U/X7R-50V OCP:6.25A
L(ripple current) PC67
0.1U/X7R-50V 2
L(ripple current)

2
=(19-5)*5/(1.5u*0.4M*19)
~6A 3 PD8 =(19-3.3)*3.3/(2.5u*0.5M*19)
B B
BAT54-7-F ~2.18A
1
Iocp=12-(6/2)=9A
CHN217 Iocp=6.25-(2.18/2)=5.16A
Vth=9A*15mOhm=135mV PR68 +3VPCU
R(Ilim)=(135mV*10)/5uA +15V_ALWP 1 2 Vth=5.16A*28mOhm=145mV
15V

1
~270K R(Ilim)=(145mV*10)/5uA
PR69 PR76
22_8 PC68 200K/F_4 39K/F_4 ~294K
0.1U/X7R-50V PC62

1
2
5
6
0.1U/X7R-50V

SUSD 3 PQ16
+5VPCU +5VPCU +3VPCU +3VPCU FDC653N_NL

VIN 15V

4
+3VSUS
PC146 PC70 PC63 PC64
PQ43
5
6
7
8

1
2
5
6

1
2
5
6

1
2
5
6
PR159 PR153 0.1U/X7R-50V 0.1U/X7R-50V 0.1U/X7R-50V 0.1U/X7R-50V PC59
PDTC143TT 1M 1M 0.1U/X7R-50V
MAIND 3 PQ26 MAIND 3 PQ17 S5D 3 PQ18
S5_ON <31,37>
3

4 FDC653N_NL FDC653N_NL FDC653N_NL

3

2 PR160
4

4
1M
2 +5V +3V +3V_S5
PQ41
1

A PQ44 A
3
2
1

2N7002E FDS8884 PC77 PC60 PC61

0.1U/X7R-50V 0.1U/X7R-50V 0.1U/X7R-50V
+5V_S5
1

PC142
0.1U/X7R-50V
PROJECT : ZD1
modify 1208 Quanta Computer Inc.
Size Document Number Rev
Custom B
ISL6251 CHARGER
Date: Monday, December 11, 2006 Sheet 33 of 38
5 4 3 2 1
 5 4 3 2 1

PL2
HI0805R800R-00_8

VIN_6262
modify 1208 PL1
HI0805R800R-00_8
+1.05V
PC155
VIN
2200P/100V_6

1
PR93 PR94 PR95 PR96 PR97 PR98 PR99 +
*0 *0 *0 *0 *0 *0 *0

2
2
PR161
2.2
DELAY_VR_PWRGOOD <3,7,14> Merom: VCC_CORE/ 44A

5
D PQ30 D
AOL1414 PC88 PC10
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 PC4 10U/X6S-25V_1206 PC5 470U/25V 0.1U/X7R-50V
Yonah: VCC_CORE/ 36A

1
6262_UG1 4 PC156 10U/X6S-25V_1206
2200P/100V_6
VCC_CORE

1
2
3
PR22 4.99K/F VIN_6262 +3V
PWR_MON 2 1 PGD_IN modify 1208
PL14 0.36uH
6262_PH1 1 2
1

1
for ISL6262A PR120

1
PC14 10/F PR19 PR21 PR162

4
5
0.1U/X7R-50V 10_4 *2.2 + +
2

+5V_S5 1.91K/F_4

2
6262_LG1 4 PC157

1
1
<3> PSI# PSI#

1
PR121 PC114 PQ33 *2200P/100V_6 PC99 PC98

1
2
3
10/F 0.1U/X7R-50V PC100 0.1U/X7R-50V AOL1412 470u_2V_7343 470u_2V_7343

2
PR88 PR89

22

20

48
2

1
PR114 0_8 PU8
PC21 0 0

VCC

VIN

PGOOD
3V3
1U/X7R-25V_8
1 PR32 3.65K/F
ISL6262A VSUM
21 GND UGATE1 35
PR107 2.2 PR31 10K/F
Close to Phase 1 Inductor 49 GND_T BOOT1 36 1 2

1
Throttling temp. PR30 1/F
+3VSUS PC103
105 degree C 0.22U/X5R-25V_8

2
34 PR29 *0 VIN_6262
C PHASE1 C
PSI# PR106 0_4 PSI#_1 2 ISEN2
PSI#
LGATE1 32
PR108 VR_ON PR23 *0_4 PGD_IN 3 PGD_IN PC158
PGND1 33
*10K/F_4 PR101 147K/F 4 2200P/100V_6
RBIAS

1
24 ISEN1
ISEN1

2
5 PR163
<3> H_PROCHOT# VR_TT# modify 1208

2
PR109 PR24 6 PC116 2.2
470K_4 NTC 4.02K/F_4 NTC
+5V_S5 0.22U/X5R-25V

2
ED8-B -0623-add 2 1 PC17 7 PQ37

1
PC16 1 15N/X7R-50V SOFT PC104 PC118 PC108
2

5
.01U/X7R-16V_4 31 1 2 AOL1414 10U/X6S-25V_1206 PC112 0.1U/X7R-50V
H_VID0 PVCC 10U/X6S-25V_1206
Panasonic 37 VID0
<4> H_VID0 4.7U/X6S-25V_8
ERT-J0EV474J H_VID1 38 27 6262_UG2 4
<4> H_VID1 VID1 UGATE2 PR116 2.2
H_VID2 39 26 1 2 PC159
<4> H_VID2

1
2
3
VID2 BOOT2
modify 1208

1
PSI#_1 H_VID3 40 2200P/100V_6
<4> H_VID3 VID3 PC106
H_VID4 41 0.22U/X5R-25V_8 PL15 0.36uH
<4> H_VID4

2
VID4 6262_PH2
PHASE2 28 1 2
H_VID5 42
<4> H_VID5 VID5

2
PR20 30 6262_LG2 PR164

4
H_VID6 LGATE2
*0 <4> H_VID6 43 VID6

1
29 *2.2
PR17 0_4 VR_ON PGND2 + +
<31> VRON 44 VR_ON 4
23 ISEN2 PC160

1
PR18 499/F_4 DPRSLPVR ISEN2 PQ36
<7,14> PM_DPRSLPVR 45

1
2
3

2
DPRSLPVR

1
DPRSLPVR AOL1412 *2200P/100V_6
PR104 0_4 46 PC115
<3,7,12> ICH_DPRSTP# DPRSTP# 0.22U/X5R-25V PC120 PC119

2
PR103 0_4 CLKEN# 47 PR124 PR125 470u_2V_7343 470u_2V_7343
<14> VR_PWRGD_CK410# CLK_EN# PC105
B 25 2 1 0 0 B
PR117 1K/F_4 NC
1000P/X7R-50V_4
PR115 PC109 8 PR112 13.3K/F_4
OCSET
1 2 13 VDIFF
255/F_4 1000P/X7R-50V 19 VSUM
VSUM
PR118 ED8-B -0623-33nf to 68nf
12 PR28
FB2
1

PR27
1K/F_4 PC22 11K/F_4 2.7K/F_4
11
2

FB
1

68N/X7R-25V PR129 3.65K/F

PC18 PC20 VSUM
PR25 97.6K/F_4 2 1
2

0.22U/X7R-10V PR84 PR128 10K/F

470P/X7R-50V_4 10 Panasonic
PC15 COMP
2 1
ERT-J1VR103J PR127 1/F
VO 18
220P/X7R-50V_4 PR113 6.81K/F_4
DROOP

9 10K _6 NTC
VW
VSEN

ED8-B -0623-390p to330p ISEN1

RTN

DFB

PC107
1

1 2 PR123 PR126 *0
PC19 Close to Phase 1 Inductor
15

14

16

17

1000P/X7R-50V 1K/F_4 0.22U/X5R-25V

2

PR119
PC110 2 1 3.48K/F_4
.01U/X7R-16V_4 ED8-B -0623-3.9k to 3.48k

PC117
180P/NPO-50V_4
2 1 ISL6262_VO
2

A PC113 PC111 A
.01U/X7R-16V_4 .01U/X7R-16V_4
1

Parallel
PR26 0_4
VCCSENSE <4>
PR122 0_4
VSSSENSE <4>

PROJECT : ZD1

Size
Quanta Computer Inc.
Document Number Rev
Custom CPU CORE(ISL6262) B

WWW.AliSaler.Com 5 4 3 2
Date: Monday, December 11, 2006
1
Sheet 34 of 38
 1 2 3 4 5

A A

VIN-1.5V
PL4
VIN
+5V_S5 HI0805R800R-00_8
PR53
PC56 PC55 PC57

5
6
7
8
2
10 .1U/X7R-25V_8 10U/X6S-25V_120610U/X6S-25V_1206
PC50 PD5

1
PR58 PC49 4
*.1U SW1010C PQ45
B 1M 4.7U/Y5V-10V_8 B

2
FDS8884

PU6 PC51
SC411MLTRT .1U/X7R-25V_8

3
2
1
PR57 0 15 13
<31,36,37> MAINON EN/PSV BST
+3V DH-1.5V
16 VIN DH 12
PL3 16A
1 VOUT LX 11 +1.05V
2 10 PR55 6.65K/F 1R5UH-3.8mR
PR136
*10K 3
VCCA ILIM
9
modify 1208
FBK VDDP

5
6
7
8

1
4 8 DL-1.5V PR56
<31> HWPG_1.05V PGOOD DL + PC52
6 7 4 11K/F 33P/NPO-50V
VSSA PGND

2
5 17 1.5V_FB
NC TPAD
14
GND

GND

GND

GND
NC
1

PC48 PC54 PC53 PQ46 PR54

0.1U/X7R-50V PC44 10K/F

3
2
1
1000P/X7R-50V
.01U/X7R-50V FDS6690AS PC47 10U/Y5U-10V_8
2

18

19

20

21

560U/2.5V_6X5.7

VOUT=(1+R2/R3)*0.5
C C

D D

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
+1.5V / +2.5V B

Date: Monday, December 11, 2006 Sheet 35 of 38

1 2 3 4 5
 5 4 3 2 1

D D

PL17
VIN
HI0805R800R-00_8
+1.8VSUS
PC126

5
6
7
8
PR33
PC127 2200P/X7R-50V
*2.2/F
10U/X6S-25V_1206 4
PU9 PQ39
TPS51116 PC24 PC124
1 19 FDS8884 PC25 10U/X6S-25V_120610U/X6S-25V_1206
VLDOIN DRVH *2200P/50V
2 20 PC29 0.1U/X7R-50V
+SMDDR_VTERM VTT VBST PL16

3
2
1
PC131 PC130 4 18 +1.8VSUS
VTTSNS LL

5
6
7
8

5
6
7
8
10U/X6S-25V_1206 5 17 1R5UH-3.8mR
10U/X6S-25V_1206 GND DRVL
PC123 +
MAX Current 10A
3 VTTGND PGND 16
4 4 PR130 PC23
DIS_MODE 6 11 S3_1.8V PR134 0 560U/2.5V_6X5.7 10U/Y5V-10V_8
C MODE S3 MAINON <31,35,37> C
PR135 *2.2/F
7 12 S5_1.8V PR133 0
+SMDDR_VREF VTTREF S5 SUSON <31,37>
0 5VIN 8 14 5VIN
PC129 COMP V5IN PR132 PC121

3
2
1

3
2
1
0.033U/50V 9 13 +3VPCU +3VPCU PQ4 PQ3 *2200P/50V
PR38 VDDSNS PGOOD FDS6690AS *FDS6690AS
GND
GND
GND
GND
GND
GND
5VIN GND 100K/F
10 VDDQSET CS 15

0
21
22
23
24
25
26
27

FOR DDR II PC32 PR35

*1000P/50V 8.25K/F modify 11-29

PR40 *0 DIS_MODE PR37
5VIN
modify 1208
+5VPCU HWPG_1.8V <31>
1

0 PC128

+1.8VSUS PR41 0 4.7U/X5R-6.3V

2

B B

+1.8VSUS
1
2
5
6

<33,37> MAIND PR131 0 3 PQ38

FDC653N_NL
1

PC122
4

*0.47U/10V
+1.8V
2

PC125
0.1U/X7R-50V

MAX Current 3.5A

A A

<OrgName>

<OrgAddr1>
<OrgAddr2>
PROJECT : ZD1
<OrgAddr3>
<OrgAddr4> Quanta Computer Inc.
Size Document Number Rev

WWW.AliSaler.Com DDR 1.8V(TPS51116) B

Date: Monday, December 11, 2006 Sheet 36 of 38

5 4 3 2 1
 5 4 3 2 1

1 GND0 VO1 5
PR34
MAINON 2 6
EN VO2 +2.5V
PQ5 FDS8884 200K/F +3VSUS
+1.8VSUS
3 VIN1 GND1 8 0.5A
8 1 4 VIN2 GND2 9

ADJ
7 2
6 3
+ PC43 PC42 5
modify 11-29

7
PC45 PU2
0.1U/Y5V-16V_4 10U/X5R-6.3V AT814

4
9338DRV
D D
1.24V VTT-ADJ
R1
560U/2.5V_6X5.7
PR52 PC26 PC27 PC37

2
+1.5V PC28 10U/Y5U-10V_8 1U/16V PR44 22U/Y5U-10V_8 PC35
0 3A 0.1U/X7R-50V 10.2K/F_4 0.1U/X7R-50V
+3V PR43 R2
+1.5V <4,10,13,15,22,23,26,29>
PR48 100K_4 10K/F_4 Vout=1.24*[1+(R1/R2)]
REV:3A MODIFY PC46

1
<31> HWPG_CPUIO 3 PGD DRV 6
.01U/X7R-25V_4 PR50
Rg 20K/F
MAINON PR49 0_4 9338EN 4
<31,35,36> MAINON EN +
ADJ 5

GND
+5VPCU
1 VCC Vout1 = (1+Rg/Rh)*0.5 PR51
PC41 10K/F +5V

2
PU5 Rh
0.1U/Y5V-16V_4 G9338 ADJ PC36 PU4
0.1U/Y5V-16V_4 G966
4 VPP PGOOD 1
PC133 PC132 PR45
0.1U/Y5V-16V_4 PC134 560U/2.5V_6X5.7 MAINON 2 6
VEN VO +1.25V
10U/X5R-6.3V
10K/F 3 2A
+1.8VSUS VIN
8 GND

ADJ
9 GND NC 5
PR46
PC40

7
19.6K/F 10U/Y5U-10V_8

C
0.8V C
PC38 PC39
+3VPCU SOT23-5-2_8-95 +1.5V_S5 10U/X5R-6.3V 0.1U/Y5V-16V_4
PU10 *AT5206G-1.5V PR47
200mA
1 5 34K/F
VIN VOUT
2

2
PC148 PC147
Vout =0.8(1+R1/R2)
GND

*1U/X7R-25V_8 3 4 *1U/X7R-25V_8 =1.25V

1

1
SH BP 1
PR154
PC149 *0_4
2

*470P/X7R-50V_4 PC150
2

*10U/X6S-25V_1206
<31,33> S5_ON

PR155
*0_4
+5V

PC31 PU3
0.1U/Y5V-16V_4 G966
4 VPP PGOOD 1
PR39
MAINON 2 6
VEN VO +1.2V
VIN +SMDDR_VREF +1.8VSUS +3VSUS 15V 10K/F
+1.8VSUS 3 VIN 1A
8 GND

ADJ
9 GND NC 5
B PR36 B
PC30

7
PR77 PR74 PR73 PR80 PR71 17.4K/F 10U/Y5U-10V_8
1M 22 22 22 1M
0.8V
SUS_ON_G SUSD
SUSD <33> PC34 PC33
3

10U/X5R-6.3V 0.1U/Y5V-16V_4
3

PR42

2 2 2 2 2 34K/F
<31,36> SUSON PC69
PR79 PQ22 PQ20 PQ24 PQ19 *2200p_4
PQ28 1M 2N7002E 2N7002E 2N7002E 2N7002E
Vout =0.8(1+R1/R2)
1

DTC144EU =1.2V
1

Add by power on 10/19

VIN +1.05V +1.8V +2.5V +3V +5V +SMDDR_VTERM +1.5V +1.25V 15V

PR60 PR65
PR59 PR66 PR62 PR63 PR64 PR137 PR67 PR72
1M 22 22 22 22 22 22 22 22 1M
A RUN_ON_G MAIND A
MAIND <33,36>
3

3
3

2 2 2 2 2 2 2 2 2 2 <OrgName>
<31,35,36> MAINON PC71
PR61 PQ13 PQ8 PQ14 PQ10 PQ11 PQ12 PQ40 PQ15 PQ21 *2200p_4 <OrgAddr1>
<OrgAddr2>
PROJECT : ZD1
PQ9 1M 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E 2N7002E
1

DTC144EU <OrgAddr3>
Quanta Computer Inc.
1

<OrgAddr4>

Size Document Number Rev

Discharge (1.5V/2.5V) B

Date: Monday, December 11, 2006 Sheet 37 of 38

5 4 3 2 1
 5 4 3 2 1

Change list
Schematic
Item Fixed Issue Reason for change Rev. PG# Modify List

1 B 28
R5C833 SD CARD FAIL SD CARD NO FUNCTION SD card can not be detected , U32(ES2) sample will fix this issue.

D D
2 R5C833 MMC CARD FAIL MMC CARD NO FUNCTION B 28 MMC card can not be detected , U32(ES2) sample will fix this issue.

3 TV CARD NO FUNCTION Add +1.5V,Liteon without +1.5V; Avermedia need +1.5V B 22 CN34.6 & .28 & .48 connect +1.5V

4
CAN'T BRING UP power sequence fail B 14 The CLPWROK pin of ICH8 connect with HWPG signal

5
VOLUME CONTROL ISSUE VR switch have On/Off noise B 31 add 2 capacity 0.1uF(C634,C636) in DIGVOL_UP / DIGVOL_DN pins

6
T/P NO FUNCTION the pin definiton is wrong B 22 change CN7 pin definition.

7
MMB NO FUNCTION the pin definiton is wrong B 22 change CN8 pin definition.

8
NONE Modem have different interface which is +3V and +1.5V B 15 reserve +3V and +3V_S5

GPIO10: Reserve PU, 10K => It is GPO and OD

B 14
9 NONE INTEL request to add for AMT function GPIO14: Reserve PD, 10K => It is GPI as AC present and active high

The signal of KBSMI#_ICH add diode , and it PU to +3V_S5

10 ICH8 ELECTRIC LEAKAGE ISSUE INTEL request to add for AMT function , ICH8 have electric leadage from EC B 14 The signal of LID591#_ICH add diode , and it PU to +3V_S5

11

C C
12

13

14

15

16

17

18

19

20
B B

A A

PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
CHANGE LIST B

Date: Friday, December 08, 2006 Sheet 38 of 38

5 4 3 2 1

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