SED1560/1/2

Technical Manual
(Preliminary)

S-MOS Systems, Inc.

October, 1996
Version 3.0 (Preliminary)

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Table of Contents SED1560 Series
TABLE OF CONTENTS

1.0 Overview ................................................................................................................................................... 5

1.1 Description .................................................................................................................................... 7
1.2 Features ........................................................................................................................................ 7
1.3 System Block Diagrams ................................................................................................................ 7
1.4 Block Diagram ............................................................................................................................... 9

2.0 Pin Description ....................................................................................................................................... 11

2.1 Power Supply .............................................................................................................................. 13
2.2 LCD Driver Power Supplies ......................................................................................................... 13
2.3 Microprocessor Interface ............................................................................................................. 14
2.4 Oscillator and Display Timing Control ......................................................................................... 15
2.5 LCD Driver Outputs ..................................................................................................................... 16

3.0 Electrical Characteristics ...................................................................................................................... 17

3.1 Absolute Maximum Ratings ......................................................................................................... 19
3.2 DC Characteristics ...................................................................................................................... 20
3.3 AC Characteristics........................................................................................................................ 24
3.3.1 Reset ............................................................................................................................ 24
3.4 Display Control Timing ................................................................................................................ 25
3.5 System Buses: Read/Write Characteristics I (80-Series MPU) ................................................... 27
3.6 System Buses: Read/Write Characteristics II (68-Series MPU) .................................................. 28
3.7 Serial Interface ............................................................................................................................ 30

4.0 Functional Description .......................................................................................................................... 33

4.1 Microprocessor Interface ............................................................................................................. 35
4.1.1 Parallel/Serial Interface ................................................................................................ 35
4.1.2 Parallel Interface ........................................................................................................... 35
4.1.3 Serial Interface ............................................................................................................. 35
4.1.4 Chip Select Inputs ........................................................................................................ 36
4.2 Data Transfer .............................................................................................................................. 36
4.3 Status Flag .................................................................................................................................. 38
4.4 Display Data RAM ....................................................................................................................... 38
4.5 Column Address Counter ............................................................................................................ 38
4.6 Page Address Register ............................................................................................................... 38
4.7 Initial Display Line Register ......................................................................................................... 40
4.8 Output Selection Circuit............................................................................................................... 40
4.9 SED1560 Output Status .............................................................................................................. 42
4.10 SED1561 Output Status ............................................................................................................ 42
4.11 SED1562 Output Status ............................................................................................................ 43
4.12 Display Timers ........................................................................................................................... 43
4.12.1 Line Counter and Display Data Latch Timing ............................................................. 43
4.12.2 FR and SYNC ............................................................................................................. 43
4.12.3 Common Timing Signals ............................................................................................ 43
4.13 Two-frame AC Driver Waveform (SED1561, 1/32 duty) ............................................................ 44
4.14 n Line Inverse Driver Waveform (n-5, line inverse register 4) .................................................. 45
4.15 Display Data Latch .................................................................................................................... 46

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SED1560 Series Table of Contents
4.16 LCD Driver ................................................................................................................................. 46
4.17 Display Data Latch Circuit ......................................................................................................... 46
4.18 LCD Driver Circuit ..................................................................................................................... 46
4.19 Oscillator Circuit ........................................................................................................................ 46
4.20 FR Control Circuit ...................................................................................................................... 46
4.21 Power Supply Circuit ................................................................................................................. 48
4.22 Tripler Boosting Circuit .............................................................................................................. 48
4.23 Voltage Regulation Circuit (Software Contrast Adjustment Function is Not Used) ................... 49
4.24 Voltage Regulation Circuit Using Software Contrast Adjustment Control Function .................. 50
4.25 Precautions on Using the SED1560 Series Software Contrast Adjustment Control Function .. 51
4.26 Liquid Crystal Voltage Generating Circuit ................................................................................. 54
4.27 Reset ......................................................................................................................................... 56

5.0 Commands .............................................................................................................................................. 57

5.1 Command Summary .................................................................................................................. 59
5.2 Command Definitions ................................................................................................................. 60
5.3 Software Contrast Control Register............................................................................................. 67
5.4 Microprocessor Interface ............................................................................................................. 69
5.5 LCD Panel Interface Examples ................................................................................................... 70
5.6 Special Common Driver Configurations ...................................................................................... 72

6.0 Packaging ............................................................................................................................................... 73

6.1 Pad Layout .................................................................................................................................. 75
6.2 SED1560/1/2 TAB Pin Layout ..................................................................................................... 77
6.3 TCP Dimensions (2-sided) .......................................................................................................... 78
6.4 TCP Dimensions (4-sided) .......................................................................................................... 79
6.5 TCP Dimensions (D1561TOC) .................................................................................................... 80
6.6 Pad Profile ................................................................................................................................... 81
6.7 BGA Package Dimensions .......................................................................................................... 82
6.8 BGA Pin Assignment ................................................................................................................... 83
6.9 SED1560TQA OL Dimensions .................................................................................................... 84

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 1.0
Overview

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1.0 Overview 1.0 – 1.3
1.1 DESCRIPTION 1.2 FEATURES
The SED1560 Series are intelligent CMOS LCD driver- • Low-power operation: 8 µA @ 1 kHz, 6V LCD
controllers with the ability to drive alphanumeric and • 350 µA current consumption during CPU access
graphic displays. The SED1560 Series communicates @ 200 kHz
with a high-speed microprocessor, such as the Intel
• Direct interface to both 80XX and 68XX, 5 MHz,
80XX family or the Motorola 68XX family, through
zero wait-state
either a serial or an 8-bit parallel interface. It stores the
data sent from the microprocessor in the built-in display • On-chip display data RAM (166 × 65 bits)
data RAM (166 × 65 bits) and generates an LCD drive • On-chip DC/DC converter for LCD voltage
signal. These devices incorporate an internal DC/DC • On-chip voltage regulator and low-power volt-
converter to generate the negative voltage needed for age follower
LCD contrast. The controllers feature software contrast
• –.17% / °C temperature gradient
adjustment by command setting.
• On-chip oscillator with external resistor
The three different versions of the SED1560 Series • 32 levels of contrast adjustment by software
support the following duty ratios and display sizes: • Supports master/slave operation
• Selectable output configuration
Model Duty Ratio SEG × COM
• 2.4V to 6.0V supply voltage
SED1560 1/65, 1/64, 1/49, 1/48 102 × 65
• 3.5V to 16V LCD voltage
SED1561 1/33, 1/32, 1/25, 1/24 134 × 33
• Package: TAB 2 side T0B
SED1562 1/17, 1/16 150 × 17 TAB 4 side TQA
Al pad D*A
Au bump D*B
BGA 225 pad B0A
1.3 SYSTEM BLOCK DIAGRAMS

20 CHAR × 8 LINES

RES

CPU CS SED1560
D0 ~ D7

80xx
68xx

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1.3 1.0 Overview
1.3 SYSTEM BLOCK DIAGRAMS (cont.)

COM0~COM32
26 CHAR × 4 LINES

SEG0~SEG133

RES

CPU CS SED1561
D0 ~ D7

80xx
68xx

30 CHAR × 2 LINES

RES

CPU CS SED1562
D0 ~ D7

80xx
68xx

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1.0 Overview
1.4 BLOCK DIAGRAM

VSS

VDD
V1
V2
V3
V4
V5

CAP1+
CAP1–
CAP2+
CAP2–
VR
T1, T2

174-3.0
LCD
supply
voltage
generator

Output
status
select

Page
address
register

Bus holder
O00 to O31 O32

Common
and
segment
drivers

Shift
register

I/O
buffer

Command
to

Segment
driver
O101 O102 to O165 COM1

166-bit display data latch

166 x 65-bit display

data RAM

166-bit column address decoder

8-bit column address counter

8-bit column address register

decoder

MPU interface

CS1 CS2 A0 RD WR C86 SI SCL P/S RES

Common
and
segment
drivers

Shift
register

Line
address
decoder

Status flag
Commons
only

Line
counter

Display
timing
generator
Frame
control

Display
initial line
register

Oscillator

I/O buffer

D7 D6 D5 D4 D3 D2 D1 D0

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VDD
V1
V2
V3
V4
V5

FR
SYNC
CL
CLO
DYO
M/S

OSC1
OSC2
1.4

9
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 2.0
Pin Description

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2.0 Pin Description 2.1 – 2.2
2.1 POWER SUPPLY
Number of Pins I/O Name Description
2 Supply VDD Common to MPU power supply pin VCC
2 Supply VSS Ground
11 Supply V1 to V5 LCD driver supply voltages. The voltage determined by the LCD
LCD cell is impedance-converted by a resistive divider or an operational
voltage amplifier for application. Voltage levels are based on VDD. The
voltages must satisfy the following relationship:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
Master mode select: bias voltages are generated on-chip.
SED1560 SED1561 SED1562
V1 1/9 V5 1/7 V5 1/5 V5
V2 2/9 V5 2/7 V5 2/5 V5
V3 7/9 V5 5/7 V5 3/5 V5
V4 8/9 V5 6/7 V5 4/5 V5

2.2 LCD DRIVER POWER SUPPLIES

Number of Pins I/O Name Description
1 O CAP1+ DC/DC voltage converter capacitor 1 positive connection
1 O CAP1– DC/DC voltage converter capacitor 1 negative connection
1 O CAP2+ DC/DC voltage converter capacitor 2 positive connection
1 O CAP2– DC/DC voltage converter capacitor 2 negative connection
1 O VOUT DC/DC voltage converter output
1 I VR Voltage adjustment pin. Applies voltage between VDD and V5 using
a resistive divider.
2 I T1, T2 Liquid crystal power control terminals
Voltage
Boosting
T1 T2 Regulation V/F Circuit
Circuit
Circuit
L L Valid Valid Valid
L H Valid Valid Valid*
H L Invalid Valid Valid
H H Invalid Invalid Valid
* V/F circuit current capacity enhancement

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2.3 2.0 Pin Description
2.3 MICROPROCESSOR INTERFACE
Number of Pins I/O Name Description
8 I/O D0 to D7 Data is transferred between the controller and MPU via these pins
1 I A0 Control/display data flag input. This is connected to the LSB of the
microprocessor address bus.
• When LOW, the data on D0 to D7 is command data
• When HIGH, the data on D0 to D7 is display data
1 I RES Reset input. Setting this pin low initializes the SED156X.
2 I CS1, Chip select inputs. Data input/output is enabled when CS1 is LOW
CS2 and CS2 is HIGH.
1 I RD Read enable input. See note 1.
1 I WR Write enable input. See note 2.
1 I C86 Microprocessor interface select input.
• LOW when interfacing to 8080-series
• HIGH when interfacing to 6800-series
1 I SI Serial data input
1 I SCL Serial clock input. Data is read on the rising edge of SCL and
converted to 8-bit parallel data.
1 I P/S Parallel/serial data input select
Data/
Operating Chip Data Read/ Serial
P/S com-
Mode Select I/O write Clock
mand
D0 to
HIGH Parallel CS1, CS2 A0 RD, WR —
D7
LOW Serial CS1, CS2 A0 SI Write only SCL

In serial mode, data cannot be read from the RAM, and D0 to D7, HZ,
RD and WR must be HIGH or LOW. In parallel mode, SI and SCL
must be HIGH or LOW.
Notes:
1. When interfacing to 8080-series microprocessors, RD is active-LOW. When interfacing to 6800-series microprocessors, they are
active-HIGH.
2. When interfacing to 8080-series microprocessors, WR is active-LOW. When interfacing to 6800-series microprocessors, read
mode is selected when WR is HIGH, and write mode is selected when WR is LOW.

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2.0 Pin Description 2.4
2.4 OSCILLATOR AND DISPLAY TIMING CONTROL
Number of Pins I/O Name Description
2 I OSC1 Using internal oscillator when M/S = “H”, connect resistor Rf to the
OSC1 and OSC2 pins. The OSC2 pin is used for output of the
oscillator amplifier.
2 I/O OSC2 When M/S = “L”: the OSC2 pin is used for input of oscillation signal.
The OSC1 pin should be left open. Fix the CL pin to the VSS level when
using the internal oscillator circuit as the display clock.
1 I CL Display clock input. The line counter increments on the rising edge of
CL, and the display pattern is output on the falling edge. When using
the external display clock, OSC1 = “H”, OSC2 = “L”, and reset this LSI
by RES pin.
1 O CLO Display clock output. When using the internal oscillator, the clock
signal is output on this pin. Connect CLO to YSCL on the common
driver.
1 I M/S Master/slave select input. Master produces signals for display, and
slave receives them. This is for display synchronization.
Operating Internal Power
Device M/S FR SYNC OSC1 OSC2 DYO
Mode Oscillator Supply
LOW Slave OFF OFF I I Open I O
156X
HIGH Master ON ON O O I O O
Note:
I = input mode
O = output mode
1 I/O FR LCD AC drive signal input/output. Output is selected when M/S is
HIGH, and input is selected when M/S is LOW.
1 I/O SYNC Display sync input/output. Output is selected when M/S is HIGH, and
input is selected when M/S is LOW.
1 O DYO Start-up output for common driver. Connect to DIO of the common
driver, such as the SED1630.
* SED1630 has a DIO input.

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2.5 2.0 Pin Description
2.5 LCD DRIVER OUTPUTS
Number of Pins I/O Name Description
166 O O0 to LCD driver outputs. O0 to O31 and O102 to O165 are selectable
O165 segment or common outputs, determined by a selection command.
O32 to O101 are segment outputs only.
For segment outputs, the ON voltage level is given as shown in the
following table:
LCD ON Voltage
RAM Data FR
Normal Display Inverse Display
LOW V3 V5
LOW
HIGH V2 VDD
LOW V5 V3
HIGH
HIGH VDD V2

For common outputs, the ON voltage is given as shown in the follow-

ing table:
Scan Data FR LCD ON Voltage
LOW V4
LOW
HIGH V1
LOW VDD
HIGH
HIGH V5

1 O COM1 LCD driver common output. Common outputs when the “DUTY + 1”
command is executed are as follows:
Device “DUTY + 1” ON “DUTY + 1” OFF
SED1560 COM64, COM48 V1 or V4
SED1561 COM32, COM24 V1 or V4
SED1562 COM16 V1 or V4

Common output special for the indicator.

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 3.0
Electrical Characteristics

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3.0 Electrical Characteristics 3.1
3.1 ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Unit

–7.0 to 0.03
Supply voltage range VSS –6.0 to 0.3 V
(when triple voltage conversion)
Driver supply voltage range (1) V5 –18.0 to 0.3 V
Driver supply voltage range (2) V1, V2, V3, V4 V5 to 0.3 V
Input voltage range VIN VSS–0.3 to 0.3 V
Output voltage range V0 VSS–0.3 to 0.3 V
Operating temperature range Topr –30 to 85 °C
Storage temperature range (TCP) Tstr –55 to 125 °C
Notes:
1. The voltages shown are based on VDD = 0V.
2. Always keep the condition VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 for voltages V1, V2, V3 and V4.
3. If devices are used over the absolute maximum rating, the LSIs may be destroyed permanently. It is desirable to use them under
the electrical characteristic conditions for general operation. Otherwise, a malfunction of the LSI may be caused and LSI reliability
may be affected.
4. For operating temperatures below –30°C, please consult an S-MOS engineer.

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3.2 3.0 Electrical Characteristics
3.2 DC CHARACTERISTICS
VDD = 0V, VSS = –5 ± 10%, Ta = –30 to +85°C unless otherwise noted.
Applicable
Parameter Symbol Condition Min Typ Max Unit
Pin
Recommended
Power –5.5 –5.0 –4.5 VSS
operation VSS V
voltage (1)
Operational –6.0 — –2.4 VSS *1
Operational V5 –16.0 — –3.5 V V5 *2
Operating Operational V1, V2 0.4 × V5 — VDD V V1, V2
voltage (2)
Operational V3, V4 V5 — 0.6 × V5 V V3, V4
VIHC1 0.3 × VSS — VDD V *3
VIHC2 0.15 × VSS — VDD V *4
High-level input voltage
VIHC1 VSS = –2.7V 0.2 × VSS — VDD V *3
VIHC2 VSS = –2.7V 0.15 × VSS — VDD V *4
V ILC1 VSS — 0.7 × VSS V *3
V ILC2 VSS — 0.85 × VSS V *4
Low-level input voltage
V ILC1 VSS = –2.7V VSS — 0.8 × VSS V *3
V ILC2 VSS = –2.7V VSS — 0.85 × VSS V *4
VOHC1 IOH = –1 mA 0.2 × VSS — VDD *5
V
VOHC2 IOH = –120 µA 0.2 × VSS — VDD OSC2
High-level output voltage
VOHC1 VSS = –2.7V IOH = –0.5 mA 0.2 × VSS — VDD *5
V
VOHC2 VSS = –2.7V IOH = –50 µA 0.2 × VSS — VDD OSC2
V OLC1 IOL = 1 mA VSS — 0.8 × VSS *5
V
V OLC2 IOL = 120 µA VSS — 0.8 × VSS OSC2
Low-level output voltage
V OLC1 VSS = –2.7V IOL = 0.5 mA VSS — 0.8 × VSS *5
V
V OLC2 VSS = –2.7V IOL = 50 µA VSS — 0.8 × VSS OSC2
Input leakage current ILI VIN = VDD or VSS –1.0 — 1.0 µA *6
Output leakage current ILO –3.0 — 3.0 µA *7
V5 = –14.0V — 2.0 3.0 O0 ~ O166
LCD driver ON resistance RON Ta = 25°C kΩ
V5 = –8.0V — 3.0 4.5 *8
ISSQ — 0.00 5.0 µA VSS
Static power consumption
I5Q V5 = –18.0V — 0.01 15.0 µA V5
Input terminal capacity CIN Ta = 25°C f = 1 MHz — 5.0 8.0 pF *3 *4
Rf = 1 MΩ VSS = –5V 15 18 22
Oscillator frequency fOSC kHz *9
±2% VSS = –2.7V 11 16 21

Reset time tR 1.0 — — µs *10

Reset “L” pulse width tRW 10 — — µs *11
(continued)

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3.0 Electrical Characteristics 3.2
(continued) VDD = 0V, VSS = –5 ± 10%, Ta = –30 to +85°C unless otherwise noted.
Applicable
Parameter Symbol Condition Min Typ Max Unit
Pin
Input voltage VSS –6.0 — –2.4 V *12
Built-in power circuit

Amplified output voltage V OUT If amplified 3 times –18.0 — — V V OUT

Voltage regulator
V OUT –18.0 — –6.0 V V OUT
circuit operation voltage
V5 1 Supplied to SED1560 –16.0 — –6.0 V
Voltage follower
V5 2 Supplied to SED1561 –16.0 — –5.0 V *13
operation voltage
V5 3 Supplied to SED1562 –16.0 — –4.5 V
Reference voltage VREG Ta = 25°C –2.35 –2.5 –2.65 V

Notes: * See Notes on page 22.

When dynamic current consumption (I) is displayed; the built-in power supply is on and T1 = T2 = Low.
Test conditions, unless otherwise specified: VDD = 0V, VSS = –5V ±10%, T a = –30 to 85°C
Parameter Symbol Condition Min Typ Max Unit Remarks
SED1560 V5 = –12.5V; 3 times amplified 169 340 µA
SED1561 V5 = –8.0V; 3 times amplified 124 250 µA
SED1562 IDD (1) V5 = –6.0V; 2 times amplified 53 110 µA *16

VSS = –2.7V; 3 times amplified 66 130 µA

V5 = –6.0V

Typical current consumption characteristics

• Dynamic current consumption (I), if an external clock and an external power supply are used.
Conditions: The built-in power supply is off but
(µA) 40 the external one is used.
SED1560
SED1560 ......... V5 = –12.5V
IDD (1) 30 SED1561 ......... V5 = –8.0V
(ISS +I5)
SED1561 SED1562 ......... V5 = –6.0V
20
External clock:
10 SED1562 SED1560 ......... fCL = 4 kHz
SED1561 ......... fCL = 2 kHz
0 SED1562 ......... fCL = 1 kHz
–1 –2 –3 –4 –5 –6 –7
VSS (V) Remarks: *14

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3.2 3.0 Electrical Characteristics

• Dynamic current consumption (I), if the built-in oscillator and the external power supply are used.
Conditions: The built-in power supply is off but the
external one is used.
(µA) 80
SED1560 SED1560 ......... V5 = –12.5V
SED1561 ......... V5 = –8.0V
IDD (1) 60 SED1562 ......... V5 = –6.0V
(ISS +I5) SED1561
40 Internal oscillation:
SED1562
SED1560 ......... Rf = 1 MΩ
20 SED1561 ......... Rf = 1 MΩ
SED1562 ......... Rf = 1 MΩ
0
–1 –2 –3 –4 –5 –6 –7 Remarks: *15
VSS (V)

• Dynamic current consumption (I), if the built-in power supply is used.

Conditions: The built-in power supply is on and
T1 = T2 = Low.
200 SED1560 ......... V5 = –12.5V;
(µA) SED1560
3 times amplified
150 SED1561 SED1561 ......... V5 = –8.0V;
IDD (1)
3 times amplified
100
SED1562 ......... V5 = –6.0V;
SED1562 2 times amplified
50
Internal oscillation:
0 SED1560 ......... Rf = 1 MΩ
–1 –2 –3 –4 –5 –6 –7
VSS (V) SED1561 ......... Rf = 1 MΩ
SED1562 ......... Rf = 1 MΩ
Remarks: *16

Notes:
*1. A wide range of operating voltage is possible, but considerable the SED156* is usually operable after “tr” time.
voltage variation during MPU access is not guaranteed. *11. Specifies the minimum pulse width of RES signal. The Low pulse
*2. The operating voltage range of the VSS and V5 systems (see Figure greater than “tRW” must be entered for reset.
3.3). The operating voltage range is applied if an external power *12. If the voltage is amplified three times by the built-in power circuit,
supply is used. the primary power VSS must be used within the input voltage range.
*3. Pins A0, D0 to D7, RD (E),WR (R/W), CS1, CS2, FR, SYNC, M/S, *13. The V5 voltage can be adjusted within the voltage follower operat-
C86, SI, P/S, T1 AND T2. ing range by the voltage regulator circuit.
*4. Pins CL, SCL, and RES. *14, 15, 16. Indicates the current consumed by the separate IC. The
*5. Pins D0 to D7, FR, SYNC, CL0, and DY0 current consumption due to the LCD panel capacity and wiring
*6. Pins A0, RD (E), WR (R/W), CS1, CS2, CL, M/S, RES, C86, SI, capacity is not included.
SCL, P/S, T1, and T2. The current consumption is shown if the checker is used, the
*7. Applied if pins D0 to D7, FR, and SYNC are high impedance. display is turned on, the output status of Case 6 is selected, and the
SED1560 is set to 1/64 duty, the SED1561 is set to 1/32 duty, and
*8. The resistance when the 0.1 -volt voltage is applied between the the SED1562 is set to 1/64 duty.
“On” output terminal and each power terminal (V1, V2, V3 or V4).
It must be within the operating voltage (2). *14. Applied if an external clock is used and if not accessed by the MPU.
*9. The relationship between the oscillation frequency, frame and Rf *15. Applied if the built-in oscillation circuit is used and if not accessed
value (see Figure 3.2). by the MPU.
*10. “tr” (reset time) indicates the period between the time when the RES *16. Applied if the built-in oscillation circuit and the built-in power circuit
signal rises and when the internal circuit has been reset. Therefore, are used (T1 = T2 = Low) and if not accessed by the MPU.

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3.0 Electrical Characteristics 3.2
The relationship between oscillator frequency fOSC
Ta = 25°C VSS = –5V and LCD frame frequency fF is obtained from the
40
following expression:
30
Table 3.1
[KHz]
20 Device Duty fF
fOSC

10 1/64 fOSC/256
SED1560
1/48 fOSC/192
0 0.5 1.0 1.5 2.0 2.5
1/32 fOSC/256
Rf [MΩ] SED1561
1/24 fOSC/192
SED1562 1/16 fOSC/256
Figure 3.1
(fF indicates not fF signal cycle but cycle of LCD AC.)
Oscillator frequency vs. frame vs. Rf
[SED1560 Series]

200

duty 1/64 SED1560

duty 1/48

[Hz] duty 1/32 SED1561

100
fF
duty 1/24

duty 1/16 SED1562

0 2 4 6 8
fCL [KHz]

Figure 3.2 External clock (fCL) vs. frame frequency [SED1560 Series]

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3.2 – 3.3.1 3.0 Electrical Characteristics

10
–20
5.0V
–16 1
–15
–13 2.7V
[V] [mA]
–10 0.1
V5 IDD (2)

–5
0.01

0 –2 –4 –6 –8
–2.4 –3.0
0 0.01 0.1 1 10
VSS [V]
fcyc [MHz]

Figure 3.3 Figure 3.4

Operating voltage range for VSS and V5 Power consumption during CPU access cycle
(IDD [2])

3.3 AC CHARACTERISTICS
3.3.1 Reset
Table 3.5 Reset

Rating
Parameter Symbol Condition Unit
Min Typ Max
tR is measured from the rising edge
Reset time tR of RES. The SED156X resumes 1.0 — — µs
normal operating mode after a reset.
Reset LOW-level
tRW 1.0 — — µs
pulsewidth

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3.0 Electrical Characteristics 3.4
3.4 DISPLAY CONTROL TIMING

CL
tWLCL tWHCL tf tr
tDFR
FR

tDSNC
SYNC

tDOH tDOL
DYO

tCDH tCDL
CLO

Figure 3.5 Display control timing

Display Control Input Timing VSS = –5.5 to –4.5V, Ta = –30 to 85°C

Rating
Parameter Symbol Condition Unit
Min Typ Max
CL LOW-level pulsewidth tWLCL 35 — — µs
CL HIGH-level pulsewidth t WHCL 35 — — µs
CL rise time tr — 30 — ns
CL fall time tf — 30 — ns
FR delay time t DFR –1.0 — 1.0 µs
SYNC delay time t DSNC –1.0 — 1.0 µs

VSS = –4.5 to –2.7V, Ta = –30 to 85°C

Rating
Parameter Symbol Condition Unit
Min Typ Max
CL LOW-level pulsewidth tWLCL 35 — — µs
CL HIGH-level pulsewidth t WHCL 35 — — µs
CL rise time tr — 40 — ns
CL fall time tf — 40 — ns
FR delay time t DFR –1.0 — 1.0 µs
SYNC delay time t DSNC –1.0 — 1.0 µs

1. Effective only when the SED156X is in the master mode. The FR/SYNC delay time output timing is provided in the
2. The FR/SYNC delay time input timing is provided in the master operation.
slave operation. 3. Each timing is based on 20% and 80% of VSS.

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3.4 3.0 Electrical Characteristics
Display Control Output Timing VSS = –5.5 to –4.5V, Ta = –30 to 85°C
Rating
Parameter Symbol Condition Unit
Min Typ Max
FR delay time tDFR CL = 50 pF — 60 150 ns
SYNC delay time tDSNC CL = 100 pF — 60 150 ns
DYO LOW-level delay time tDOL — 70 160 ns
DYO HIGH-level delay time tDOH — 70 160 ns
CLO to DYO LOW-level SED156X operating in
tCDL — 40 100 ns
delay time master mode only
CLO to DYO HIGH-level SED156X operating in
tCDH — 40 100 ns
delay time master mode only

VSS = –4.5 to –2.7V, Ta = –30 to 85°C

Rating
Parameter Symbol Condition Unit
Min Typ Max
FR delay time tDFR CL = 50 pF — 120 240 ns
SYNC delay time tDSNC CL = 100 pF — 120 240 ns
DYO LOW-level delay time tDOL — 140 250 ns
DYO HIGH-level delay time tDOH — 140 250 ns
CLO to DYO LOW-level SED156X operating in
tCDL — 100 200 ns
delay time master mode only
CLO to DYO HIGH-level SED156X operating in
tCDH — 100 200 ns
delay time master mode only

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3.0 Electrical Characteristics 3.5
3.5 SYSTEM BUSES: READ/WRITE CHARACTERISTICS I (80-SERIES MPU)

tAH8
A0

tAW8 tCYC8
tr
tCCLR tCCHR
WR, RD, (CS) tCCLW tCCHW
tf tDS8 tDH8
D0 to D7
(Write)
tACC8 tCH8
D0 to D7
(Read)

VSS = –5.0 ± 10%, Ta = –30 to 85°C

Parameter Signal Symbol Condition Min Max Unit
Address hold time A0, CS t AH8 10 — ns
Address setup time t AW8 10 — ns
System cycle time tCYC8 200 — ns
Control L pulse width (WR) WR t CCLW 22 — ns
Control L pulse width (RD) RD t CCLR 77 — ns
Control H pulse width (WR) WR tCCHW 172 — ns
Control H pulse width (RD) RD tCCHR 117 — ns
Data setup time t DS8 20 — ns
Data hold time tDH8 10 — ns
RD access time D0 ~ D7 tACC8 CL = 100pF — 70 ns
Output disable time tCH8 10 50 ns
Input signal change time tr, t f — 15 ns

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3.5 – 3.6 3.0 Electrical Characteristics
VSS = –2.7 to –4.5V, Ta = –30 to 85°C
Parameter Signal Symbol Condition Min Max Unit
Address hold time A0, CS tAH8 25 — ns
Address setup time tAW8 25 — ns
System cycle time tCYC8 450 — ns
Control L pulse width (WR) WR tCCLW 44 — ns
Control L pulse width (RD) RD tCCLR 194 — ns
Control H pulse width (WR) WR tCCHW 394 — ns
Control H pulse width (RD) RD tCCHR 244 — ns
Data setup time tDS8 40 — ns
Data hold time tDH8 20 — ns
RD access time D0 ~ D7 tACC8 CL = 100pF — 140 ns
Output disable time tCH8 10 100 ns
Input signal change time tr, t f — 15 ns

Notes: 1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC8 – tCCLW – t CCHW) or tr + tf ≤ (tCYC8 –
tCCLR – tCCHR)
2. All signal timings are limited based on 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the RD or WR signal is in the low level.
If read/write operation is performed by the RD or WR signal while CS is active, it is determined by the RD or WR signal timing.
If read/write operation is performed by CS while the RD or WR signal is in the low level, it is determined by the CS active
timing.

3.6 SYSTEM BUSES: READ/WRITE CHARACTERISTICS II (68-SERIES MPU)

tCYC6
tEWLR
tEWLW
E
tr tEWHR
tAW6 tEWHW tAH6
tf

A0, RW

tAH6
tDS6 tDH6
D0 ~ D7
(WRITE)

tACC6 tOH6
D0 ~ D7
(READ)

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3.0 Electrical Characteristics 3.6

VSS = –5.0 ± 10%, Ta = –30 to 85°C

Parameter Signal Symbol Condition Min Max Unit
System cycle time tCYC6 200 — ns
Address setup time (A0) t AW6 10 — ns
Address hold time R/W t AH6 10 — ns
Data setup time t DS6 20 — ns
Data hold time tDH6 10 — ns
D0 ~ D7
Output disable time t OH6 CL = 100pF 10 50 ns
Access time tACC6 — 70 ns
Enable H pulse READ t EWHR 77 — ns
E
width WRITE t EWHW 22 — ns
Enable L pulse READ tEWLR 117 — ns
E
width WRITE tEWLW 172 — ns
Input signal change time tr, t f — 15 ns

VSS = –2.7 to +4.5V, T a = –30 to 85°C

Parameter Signal Symbol Condition Min Max Unit
System cycle time A0, CS tCYC6 450 — ns
Address setup time (CS1, CS2) t AW6 25 — ns
Address hold time R/W t AH6 25 — ns
Data setup time t DS6 40 — ns
Data hold time tDH6 20 — ns
D0 ~ D7
Output disable time t OH6 CL = 100pF 20 100 ns
Access time tACC5 — 140 ns
Enable H pulse READ t EWHR 154 — ns
E
width WRITE t EWHW 44 — ns
Enable L pulse READ tEWLR 244 — ns
E
width WRITE tEWLW 394 — ns
Input signal change time tr, t f — 15 ns

Notes: 1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC6 – tEWLW – tEWHW) or tr + tf ≤ (tCYC6
– tEWLR – tEWHR)
2. All signal timings are limited based on 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the E signal is in the high level.
If read/write operation is performed by the E signal while CS is active, it is determined by the E signal timing.
If read/write operation is performed by CS while the E signal is in the high level, it is determined by the CS active timing.

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3.7 3.0 Electrical Characteristics
3.7 SERIAL INTERFACE

tCSS tCSH

CS

tSAS tSAH

A0

tSCYC
tSLW
SCL
tf tr tSHW
tSDS tSDH

SI

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3.0 Electrical Characteristics 3.7

VSS = –5.0 ± 10%, Ta = –30 to 85°C

Parameter Signal Symbol Condition Min Max Unit
Serial clock cycle tSCYC 500 — ns
SCL high pulse width SCL tSHW 150 — ns
SCL low pulse width t SLW 150 — ns
Address setup time tSAS 120 — ns
A0
Address hold time t SAH 200 — ns
Data setup time t SDS 120 — ns
SI
Data hold time tSDH 50 — ns
t CSS 30 — ns
CS-SCL time CS
tCSH 400 — ns
Input signal change time tr, t f — 50 ns

VSS = –2.7 to –4.5V, Ta = –30 to 85°C

Parameter Signal Symbol Condition Min Max Unit
Serial clock cycle tSCYC 1000 — ns
SCL high pulse width SCL tSHW 300 — ns
SCL low pulse width t SLW 300 — ns
Address setup time tSAS 250 — ns
A0
Address hold time t SAH 400 — ns
Data setup time t SDS 250 — ns
SI
Data hold time tSDH 100 — ns
t CSS 60 — ns
CS-SCL time CS
tCSH 800 — ns
Input signal change time tr, t f — 50 ns

Note: *2. All signal timings are limited based on 20% and 80% of VSS voltage.

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 THIS PAGE INTENTIONALLY BLANK

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 4.0
Functional
Description

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 THIS PAGE INTENTIONALLY BLANK

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4.0 Functional Description 4.0 – 4.1.3
4.1 MICROPROCESSOR INTERFACE
4.1.1 Parallel/Serial Interface
Table 4.1 Parallel/serial Interface Selection

P/S Input Type CS1 CS2 A0 RD WR C86 SI SCL D0 to D7

HIGH Parallel CS1 CS2 A0 RD WR C86 × × D0 to D7
LOW Serial CS1 CS2 A0 × × × SI SCL (Hi-Z)
× = don’t care

Parallel data can be transferred in either direction Table 4.3 Parallel Data Transfer
between the controlling microprocessor and the
Com- 6800
SED1560 Series via an 8-bit I/O buffer (D0 to D7). mon Series
8080 Series
Description
Serial data can be sent from the microprocessor to the
A0 R/W RD WR
SED1560 Series through the serial data input (SI), but
1 1 0 1 Display data read out
not from the SED1560 Series to the microprocessor.
1 0 1 0 Display data write
The parallel or serial interface is selected by
0 1 0 1 Status read
setting P/S as shown in Table 4.1.
Write to internal register
0 0 1 0
(command)
For the parallel interface, the type of microprocessor
is selected by C86 as shown in Table 4.2.

Table 4.2 Microprocessor Selection for Parallel 4.1.3 Serial Interface

Interface
The serial interface consists of an 8-bit shift register and
C86
MPU
CS1 CS2 A0 RD WR D0 to D7
a 3-bit counter. These are reset when CS1 is HIGH and
Bus Type CS2 is LOW. When these states are reversed, serial
HIGH 6800-series CS1 CS2 A0 E R/W D0 to D7 data and clock pulses can be received from the micro-
LOW 8080-series CS1 CS2 A0 RD WR D0 to D7 processor on SI and SCL respectively.

Serial data is read on the rising edge of SCL and must

be input at SI in the sequence D7 to D0. On every
4.1.2 Parallel Interface eighth clock pulse, the data is transferred from the
A0, WR (or R/W) and RD (or E) determine the type of shift register and processed as 8-bit parallel data.
parallel data transfer. See Table 4.3.
Input data is display data when A0 is HIGH and com-
mand data when A0 is LOW. A0 is read on the rising
edge of every eighth clock signal. See Figure 4.1.

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4.1.3 – 4.2 4.0 Functional Description

CS1
CS2

SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6

SCL 1 2 3 4 5 6 7 8 9 10

A0

Figure 4.1 Serial interface timing

4.1.4 Chip Select Inputs

Likewise, when the microprocessor writes data to dis-
Data transfer between the microprocessor and the
play data RAM, the data is first stored in the bus buffer
SED1560 Series is enabled when CS1 is LOW and
before being written to RAM at the next write cycle.
CS2 is HIGH. If these pins are set to any other values,
D0 to D7 are in high impedance state and will not
When writing data from the microprocessor to RAM,
accept data.
there is no delay since data is automatically trans-
ferred from the bus buffer to the display data RAM. If
the data rate is required to slow down, the micropro-
4.2 DATA TRANSFER cessor can insert a NOP instruction which has the
To match the timing of the display data RAM and same effect as executing a wait procedure.
registers to that of the controlling microprocessor, the
SED1560 Series uses an internal data bus and bus When a sequence of address sets is executed, a
buffer. When the microprocessor reads the contents dummy read cycle must be inserted between each
of RAM, the data for the initial read cycle is first stored pair of address sets. This is necessary because the
in the bus buffer (dummy read cycle). On the next read addressed data from the RAM is delayed one cycle by
cycle, the data is read from the bus buffer onto the the bus buffer, before it is sent to the microprocessor.
microprocessor bus. At the same time, the next block A dummy read cycle is thus necessary after an
of data is transferred from RAM to the bus buffer. address set and after a write cycle.

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4.0 Functional Description 4.2

WR

MPU

DATA N N+1 N+2 N+3

Bus
N N+1 N+2 N+3
holder
Internal
timing
WR

Figure 4.2 Write timing

WR

RD
MPU

DATA N N n n+1

Address set Dummy read Data read n Data read (n+1)

WR

RD

Internal
timing
Column
N N+1 N+2
address

Bus
N n N+1 N+2
holder

Figure 4.3 Read timing

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4.3 – 4.6 4.0 Functional Description
4.3 STATUS FLAG 4.5 COLUMN ADDRESS COUNTER
The SED1560 Series has a single bit status flag, D7. The column address counter is an 8-bit presettable
When D7 is HIGH, the device is busy and will accept counter that provides the column address to display
only a Status Read command. It is not necessary for data RAM. See Figure 4.4. It is incremented by 1 each
the microprocessor to check the status of this bit time a read or write command is received. The counter
before each command, if enough time is allowed for automatically stops at the highest address, A6H. The
the last cycle to be completed. contents of the column address counter are changed
by the Column Address Set command. This counter is
independent of the page address register.
4.4 DISPLAY DATA RAM When the Select ADC command is used to select
The SED1560 Series stores the display data sent inverse display operation, the column address de-
from the microcomputer in the built-in display data coder inverts the relationship between the RAM col-
RAM (166 × 65 bits) and generates the LCD drive umn data and the display segment outputs.
signals. It is a 166-column × 65-row addressable array
as shown in Figure 4.4.

The 65 rows are divided into 8 pages of 8 lines and a 4.6 PAGE ADDRESS REGISTER
ninth page with a single line (D0 only). Data is read The 4-bit page address register provides the page
from or written to the 8 lines of each page directly address to display data RAM. The contents of the
through D0 to D7. register are changed by the Page Address Set com-
mand.
The microprocessor reads from and writes to RAM
through the I/O buffer. Since the LCD controller oper- Page address 8 (1000) is a special use RAM area for
ates independently, data can be written to RAM at the the indicator.
same time as data is being displayed, without causing
the LCD to flicker.

The time taken to transfer data is very short, because

the microprocessor inputs D0 to D7 correspond to the
LCD common lines as shown in Figure 4.5. Large
display configuration can thus be created using mul-
tiple SED1560 Series devices.

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4.0 Functional Description 4.6

Page Line Common

DATA Column address
address address address
D0 00H COM 0
D1 01 COM 1
D2 02 COM 2
0 0 0 0 D3 03 COM 3
D4 04 COM 4
Page 0
D5 05 COM 5
D6 06 COM 6
D7 07 COM 7
D0 08 COM 8
D1 09 COM 9
D2 0A COM10
0 0 0 1 D3 0B COM11
Page 1
D4 0C COM12
D5 0D COM13
D6 0E COM14
D7 0F COM15
D0 10 COM16
D1 11 COM17
D2 12 COM18
0 0 1 0 D3 13 COM19
Page 2
D4 14 COM20
D5 15 COM21
D6 16 COM22
D7 17 COM23
D0 18 1/64 COM24
D1 19 COM25
D2 1A COM26
0 0 1 1 D3 1B Start COM27
Page 3
D4 1C COM28
D5 1D COM29
D6 1E COM30
D7 1F COM31
D0 20 COM32
D1 21 COM33
D2 22 COM34
0 1 0 0 D3 23 COM35
Page 4
D4 24 COM36
D5 25 COM37
D6 26 COM38
D7 27 1/32 COM39
D0 28 COM40
D1 29 COM41
D2 2A COM42
0 1 0 1 D3 2B COM43
Page 5
D4 2C COM44
D5 2D COM45
D6 2E COM46
D7 2F COM47
D0 30 COM48
D1 31 COM49
D2 32 COM50
0 1 1 0 D3 33 COM51
Page 6
D4 34 COM52
D5
D6
35 COM53
COM54
Note: For 1/65
36
D7 37 COM55 and 1/33 display
D0 38 COM56
D1 39 COM57 duty cycles, page 9
D2 3A COM58
0 1 1 1 D3
Page 7
3B COM59 is accessed follow-
D4 3C COM60
D5 3D COM61 ing 1BH and 3BH,
D6 3E COM62
D7 3F COM63 respectively.
1 0 0 0 D0 Page 8 COM 1
OUT DO DO

O0 A5 O0
O1 A4 O1
O2 A3 O2
O3 A2 O3
O4 A1 O4
O5 A0 O5
O6 9F O6
O7 9E O7

A2
A3
A4
A5
=1 =0

to
ADC

O3
O2
O1
O0

to
O162
O163
O164
O165
LCD

to

Figure 4.4 Display data RAM addressing

D0 1 COM0
D1 0 COM1
D2 1 COM2
D3 0 COM3
D4 0 COM4

Figure 4.5 RAM-to-LCD data transfer

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4.7 – 4.8 4.0 Functional Description
4.7 INITIAL DISPLAY LINE REGISTER
The Initial Display Line register stores the address of the six different LCD driver arrangements.
the RAM line that corresponds to the first (normally
the top) line (COM0) of the display. See Figure 4.4. The necessary LCD driver voltage is automatically
The contents of this 6-bit register are changed by the allocated to the COM/SEG dual outputs when their
Initial Display Line command. At the start of each LCD function is determined by the output selection circuit.
frame, synchronized with SYNC, the initial line is
copied to the line counter. The line counter is then The SED1560 selects Case 1, 2 or 6 while the
incremented on the CL clock signal once for every SED1561 selects Case 3, 4, 5 or 6. The COM/SEG
display line. This generates the line addresses for the output status for the SED1562 is fixed and so cannot
transfer of the 166 bits of RAM data to the LCD drivers. be selected.

If a 1/65 or 1/33 display duty cycle is selected by the When COM outputs are assigned to the output driv-
DUTY+1 command, the line address corresponding ers, the unused RAM area is not available. However,
to the 65th or 33rd SYNC signal is changed and the all RAM column addresses can still be accessed by
indicator special-use line address is selected. If the the microprocessor.
DUTY+1 command is not used, the indicator special-
use line address is not selected. Since duty setting and output selection are inde-
pendent, the appropriate duty must be selected for
each case.

4.8 OUTPUT SELECTION CIRCUIT Cases 1 to 6 are determined according to the three
lowest bits in the output status register in the output
The number of common (COM) and segment (SEG)
selection circuit. The COM output scanning direction
driver outputs can be selected to fit different LCD
can be selected by setting bit D3 in the output status
panel configurations by the output selection circuit.
register to “H” or “L”.
There are 70 segment-only outputs (O32 to O101)
When the DUTY+1 command is executed, pin
and 96 common or segment dual outputs (O0 to O31
COM1 becomes as shown in Figure 4.4 irrel-
and O102 to O165). A command selects the status of
evant to output selection.
the dual common/segment outputs. Figure 4.6 shows

ADC L 0 165
(D0) H 165 Column address 0

Display data RAM

Case 1 102 segments 64 commons

Case 2 32 commons 102 segments 32 commons
Case 3 32 commons 134 segments
Case 4 134 segments 32 commons
Case 5 16 commons 134 segments 16 commons
Case 6 166 segments
SED1562 150 segments 16 commons

O0 O15 O31 O101 O133 O149 O165

Figure 4.6 Output configuration selection

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4.0 Functional Description 4.8
Since master/slave operation and the output selec- The LCD driver outputs shown in Table 4.5 become
tion circuit are completely independent in the ineffective when the SED1560 or SED1561 is used
SED1560 Series, a chip on either the master or with 1/48 or 1/24 duty, respectively. In this case,
slave side can be allocated to the COM output ineffective outputs are used in the open state.
function in multi-chip configuration.

Table 4.4

SED1560 SED1561 SED1562

Duty 1/64 1/48 1/32 1/24 1/16
COMI function COM64 COM48 COM32 COM24 COM16

Table 4.5

Output Status Register

Ineffective Output
D3 D2 D1 D0
0 1 0 1 O150 ~ O165
Case 1
1 1 0 1 O102 ~ O117
SED1560
0 1 1 0 O150 ~ O165
Case 2
1 1 1 0 O16 ~ O31
0 0 1 1 O0 ~ O7
Case 3
1 0 1 1 O23 ~ O31
0 0 1 0 O158 ~ O165
SED1561 Case 4
1 0 1 0 O134 ~ O141
0 0 0 1 O158 ~ O165
Case 5
1 0 0 1 O8 ~ O15

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4.9 – 4.10 4.0 Functional Description
4.9 SED1560 OUTPUT STATUS
The SED1560 selects any output status from Cases 1, 2 and 6.

1/64 Duty (Display Area 102 × 64)

Status Register LCD Driver Output
Case
D3 D2 D1 D0 O0 O31 O32 O101 O102 O133 O134 O165
0 1 0 1 COM0 COM63
1
1 1 0 1 COM63 COM0
0 1 0 0 COM31 COM0 SEG102 COM32 COM63
2
1 1 0 0 COM32 COM63 SEG102 COM31 COM0
6 — 0 0 0 SEG166

1/48 Duty (Display Area 102 × 48)

Status Register LCD Driver Output
Case
D3 D2 D1 D0 O0 O31 O32 O101 O102 O133 O134 O165
0 1 0 1 COM0 COM47
1
1 1 0 1 COM47 COM0
0 1 0 0 COM31 COM0 SEG102 COM32 47
2
1 1 0 0 COM32 47 SEG102 COM31 COM0
6 — 0 0 0 SEG166

4.10 SED1561 OUTPUT STATUS

The SED1561 selects any output status from Cases 3, 4, 5 and 6.

1/32 Duty (Display Area 134 × 32)

Status Register LCD Driver Output
Case
D3 D2 D1 D0 O0 O15 O16 O31 O32 O133 O134 149 150 O165
0 0 1 1 COM31 COM0 SEG134
3
1 0 1 1 COM0 COM31 SEG134
0 0 1 0 SEG134 COM0 COM31
4
1 0 1 0 SEG134 COM31 COM0
0 0 0 1 15 COM0 SEG134 COM16 31
5
1 0 0 1 COM16 31 SEG134 15 COM0
6 — 0 0 0 SEG166

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4.0 Functional Description 4.10 – 4.12.3
1/24 Duty (Display Area 134 × 24)
Status Register LCD Driver Output
Case
D3 D2 D1 D0 O0 O15 O16 O31 O32 O133 O134 149 150 O165
0 0 1 1 COM23 COM0 SEG134
3
1 0 1 1 COM0 COM23 SEG134
0 0 1 0 SEG134 COM0 COM23
4
1 0 1 0 SEG134 COM23 COM0
0 0 0 1 15 COM0 SEG134 16 23
5
1 0 0 1 16 23 SEG134 15 COM0
6 — 0 0 0 SEG166

4.11 SED1562 OUTPUT STATUS

COM/SEG output status of the SED1562 is fixed.
1/16 Duty (Display Area 150 × 16)
LCD Driver Output
O0 O149 O150 O165
SEG150 15 COM0

4.12 DISPLAY TIMERS

4.12.1 Line Counter and Display Data Latch SYNC synchronizes the timing of the line counter and
Timing common timers. It is also needed to synchronize the
frame period and a 50% duty clock.
The display clock, CL, provides the timing signals for
the line counter and the display data latch. The RAM
In a multiple-chip configuration, FR and SYNC are
line address is generated synchronously using the
inputs. The SYNC signal from the master synchro-
display clock. The display data latch synchronizes the
nizes the line counter and common timing of the slave.
166-bit display data with the display clock.
4.12.3 Common Timing Signals
The timing of the LCD panel driver outputs is
independent of the timing of the input data from The internal common timing and the special-use
the microprocessor. common driver start signal, DYO, are generated from
CL. As shown in Figures 4.7 and 4.8, DYO outputs a
4.12.2 FR and SYNC HIGH-level pulse on the rising edge of the CL clock
pulse that precedes a change on SYNC. DYO is
The LCD AC signal, FR, and the synchronization
generated by both the SED1560 Series devices,
signal, SYNC, are generated from the display clock.
regardless of whether the device is in master or slave
The FR controller generates the timing for the LCD
mode. However, when operating in slave mode, the
panel driver outputs. Normally, 2-frame wave pat-
device duty and the external SYNC signal must be the
terns are generated, but n-line inverse wave patterns
same as that of the master. In a multiple-chip configu-
can also be generated. These produce a high-quality
ration, FR and SYNC must be supplied to the slave
display if n is based on the LCD panel being used.
from the master.

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4.13 4.0 Functional Description
Table 4.6 Master and Slave Timing Signal Status
Part Number Mode FR SYNC CLO DYO
CL
Master Output Output Output
Output
SED1560
Series High
Slave Input Input Imped- Output
ance

4.13 TWO-FRAME AC DRIVER WAVEFORM (SED1561, 1/32 DUTY)

31 32 1 2 3 4 5 6 27 28 29 30 31 32 1 2 3 4 5
CL

SYNC

FR

DYO

VDD
V1
COM0 V2
V3

VDD
V1
COM1
V2
V3

RAM
data

VDD
V2
SEG n
V3
V5

Figure 4.7 Frame driver timing for duty 1/32

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4.0 Functional Description 4.14
4.14 n LINE INVERSE DRIVER WAVEFORM (n=5, LINE INVERSE REGISTER 4)

31 32 1 2 3 4 5 6 27 28 29 30 31 32 1 2 3 4 5
CL

SYNC

FR

DYO

VDD
V1
COM0 V4
V5

VDD
V1
COM1 V4
V5

RAM
data

VDD
V2
SEG n V3
V5

Note: When n = 5, the line inversion register is set to 4.

Figure 4.8 Line inverse driver timing

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4.15 – 4.20 4.0 Functional Description
4.15 DISPLAY DATA LATCH 4.19 OSCILLATOR CIRCUIT
Display data is transferred from RAM to the LCD The low power consumption type CR oscillator
drivers through the display data latch. This latch is adjusting the oscillator frequency by use of only
controlled by the Display ON/OFF, Display All Points oscillator resistor Rf is used as a display timing
ON/OFF and Normal/Inverse Display commands. signal source or clock for the voltage raising circuit
of the LCD power supply.
These commands do not alter the data.
The oscillator circuit is available only in the master
operation mode. When a signal from the oscillator circuit
is used for display clock, fix the CL pin to the VSS level.
4.16 LCD DRIVER
When the oscillator circuit is not used, fix the OSC1 or
The LCD driver converts RAM data into the 167 OSC2 pin to the VDD or VSS level, respectively.
outputs that drive the LCD panel. There are 70 seg-
ment outputs, 96 segment or common dual outputs, The oscillator signal frequency is divided and output
and a COM1 output for the indicator display. from the CL0 pin as display clock. The frequency is
divided to one-fourth, one-eighth, or one-sixteenth in
Two shift registers for the common/segment drivers the SED1560, SED1561, or SED1562, respectively.
are used to ensure that the common outputs are out-
put in the correct sequence. The driver output volt-
ages depend on the display data, the common scan-
ning signal and FR. 4.20 FR CONTROL CIRCUIT
The LCD driver voltage supplied to the LCD driver
outputs is selected using FR signal.
4.17 DISPLAY DATA LATCH CIRCUIT
The display data latch circuit temporarily stores the
output display data from the display data RAM to
the LCD driver circuit in each common period.
Since the Normal/Inverse Display, Display ON/
OFF and Display All Points ON/OFF commands
control the data in this latch, the data in the display
data RAM remains unchanged.

4.18 LCD DRIVER CIRCUIT

This multiplexer generates 4-value levels for the LCD
driver, having 167 outputs of 70 SEG outputs, 96
SEG/COM dual outputs and a COM output for the
indicator display. The SEG/COM dual outputs have a
shift register and sequentially transmit COM scan-
ning signals. The LCD driver voltage is output accord-
ing to the combination of display data, COM scanning
signal and FR signal. Figure 4.9 shows a typical SEG/
COM output waveform.

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4.0 Functional Description 4.20

FR VDD
(SYNC) VSS
COM0 VDD
V1
COM1 V2
COM0 V3
COM2
V4
COM3 V5
COM4 VDD
V1
COM5 V2
COM6 COM1 V3
V4
COM7 V5
VDD
COM8 V1
V2
COM9 COM2 V3
COM10 V4
V5
COM11
VDD
COM12 V1
V2
COM13 SEG0 V3
COM14 V4
COM15 V5
VDD
SEG0 SEG1 SEG2 SEG3 SEG4 V1
V2
SEG1 V3
V4
V5
V5
V4
V3
V2
COM0 V1
to VDD
SEG0 –V1
–V2
–V3
–V4
–V5
V5
V4
V3
V2
COM0
V1
to
SEG1 VDD
–V1
–V2
–V3
–V4
–V5

Figure 4.9 Example of segment and common timing

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4.21 – 4.22 4.0 Functional Description
4.21 POWER SUPPLY CIRCUIT When (T1, T2) = (H, L), the boosting circuit does not
The SED1560 Series has an internal DC/DC con- work and open the boosting circuit terminals (CAP1+,
verter to generate LCD bias voltages. The internal CAP1–, CAP2+ and CAP2–) and apply liquid crystal
power supply circuit can be used only when the driving voltage to the VOUT terminals from outside.
controller operates in master mode. The power circuit
consists of a triple boosting circuit, a voltage regula- When (T1, T2) = (H, H), the boosting circuit and
tion circuit and a low power voltage follower circuit. voltage regulation circuit do not work and open the
boosting circuit terminals and the VR terminals and
The power circuit built into SED1560 Series is set for apply liquid crystal driving voltage to the V5, and leave
smaller scale liquid crystal panels and it is not suit- the VOUT pin open.
able when the picture element is larger or to drive a
liquid crystal panel with larger indication capacity
using multiple chips. It is recommended that an exter-
nal power supply is used when using a liquid crystal 4.22 TRIPLER BOOSTING CIRCUIT
panel with a larger load capacity. By connecting capacitors C1 between CAP1+ and
CAP1–, CAP2+ and CAP2– and VSS – VOUT, the
The power supply circuit can be controlled by the built- electric potential between VDD – VSS is boosted to the
in power ON/OFF command. When the built-in power triple toward negative side and outputted from the
is turned off, the boosting circuit, voltage regulation VOUT terminal. When a double boosting is required,
circuit and voltage follower circuit all go open. In this disconnect the capacitor between CAP2+ and CAP2–
case, the liquid crystal driving voltage V1, V2, V3, V4 and short-circuit the CAP2– and VOUT terminals to
and V5 should be supplied from outside and the obtain output boosted to the double out of the VOUT (or
terminals CAP1+, CAP1–, CAP2+, CAP2–, VOUT and CAP2–) terminal.
VR should be kept opened.
Signals from the oscillation circuit are used in the
Various functions of the power circuit can be selected boosting circuit and it then is necessary that the
by combinations of the setting of the T1 and T2. It is oscillation circuit is in operation.
also possible to make a combined use of the external
power supply and a portion of the functions of the built- Electric potentials by the boosting functions are shown
in power supply. in Figure 4.10 and 4.11.

Table 4.7

Voltage
Voltage Voltage External Voltage
V/F Converter
T1 T2 Converter Regulation Voltage Regulation
Circuit Circuit
Circuit Circuit Input Terminals
Terminals
L L O O O —
L H O O O —
H L X O O VOUT OPEN
H H X X O V5 OPEN OPEN

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4.0 Functional Description 4.22 – 4.23

VDD = 0V
(VCC = +5V) VDD = 0V
VSS = –5V
(GND) VSS = –5V

VOUT = 2vss = –10V

VOUT = 3vss = –15V

Figure 4.10 Figure 4.11

Electric potentials of double boosting Electric potentials of triple boosting

4.23 VOLTAGE REGULATION CIRCUIT (SOFTWARE CONTRAST ADJUSTMENT FUNCTION IS

NOT USED)
The boosted voltage coming out from VOUT is ad- The voltage regulation circuit renders a temperature
justed to become the liquid crystal driving voltage V5 gradient, after VREG output, of about –0.17% / °C, but
via the voltage regulation circuit. V5 voltage can be when any other temperature gradient is needed,
regulated within a range of |V5| < |VOUT| by adjust- connect a thermistor in series with the output voltage
ment of resistors Ra and Rb and it may be calculated regulating resistors.
by the following equation:
Since the VR terminal has a high input impedance, it
Rb
V5 = (1 + ) VREG Equation 4.1 is necessary to take some noise suppression mea-
Ra
sures, such as using the shortest length wiring or
wherein VREG is the constant voltage source inside shielded wiring.
the IC and the voltage is constant at VREG ≈ 2.5V.

Voltage regulation of the V5 output is made by con-

necting variable resistors between VR, VDD and V5. VDD
For fine adjustment of the V5 voltage, a combination
of fixed resistors R1 and R3 and a variable resistor R2 VREG
is needed. Ra
+
Examples of settings of R1, R2, and R3: V5
VR –
• R1 + R2 + R3 = 5 MΩ (determined by the
current required to flow between VDD and V5)
• Voltage variation range by R2: –11V ~ –13V
(determined based on the characteristics of
the liquid crystal being used) Rb

Using the above conditions and Equation 4.1, the Figure 4.12
following calculations can be made: Voltage regulation circuit

R1 = 0.947 MΩ
R2 = 0.174 MΩ
R3 = 3.879 MΩ

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4.24 4.0 Functional Description

4.24 VOLTAGE REGULATION CIRCUIT USING SOFTWARE CONTRAST ADJUSTMENT

CONTROL FUNCTION
By using software contrast adjustment control function, it is possible to control the liquid crystal driving
voltage V5 by inputting corresponding commands to adjust the contrast of the liquid crystal display.

With such an electronic contrast control function, setting 5-bit data to the electronic contrast control
register will make available 32 states of voltages from which one voltage level can be selected for the
liquid crystal driving voltage V5.

When using the software contrast control function, it is necessary to execute built-in power supply on
command after one of (T1, T2) = (L, L), (T1, T2) = (L, H), or (T1, T2) = (H, L) is set.

Example of Constant Setting When Using the Software Contrast Adjustment Control Function
(1) Determine a V5 voltage setting range by the electronic contrast control.

Liquid crystal driving voltage ...........................V5 – 10V max. to –15V min.

V5 variable voltage width ................................ 4V

(2) Determine Rb.

Rb = V5 variable voltage width / IREF (32 states IREF ≈ 6.5µA constant-current value)
Rb = 4V / 6.5µA (16 states IREF ≈ 3.2µA constant-current value)
= 615 kΩ

(3) Determine Ra.

VREG (For VREG and V5 set voltage, absolute values are used.)
Ra =
(V5 set voltage max – VREG) / Rb

2.5V
Ra =
(10V – 2.5V) / 615Ω

= 205 kΩ

(4) Adjust Ra.

Set the electronic contrast control register value to (D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0) or (0, 1, 1,
1, 1), and adjust the Ra value to the optimum contrast.

To set the voltage value by the software contrast adjustment control to the 16 states, fix the data D4 of
the electronic contrast control register to L and set data in D3 to D0. At this time, set IREF ≈ 3.2µA and
determine Ra and Rb according to the above steps (1) to (4).
Because IREF is a simplified constant-current source, it is necessary to consider the variation of
maximum ±40% as manufacturing dispersion. The temperature dependency of IREF becomes ∆IREF ≈
–0.0525 µA/°C (in the variable voltage 32 states) or ∆IREF ≈ –0.0234 µA/°C (variable voltage 16 states).
Determine Ra and Rb for the LCD to be used, by taking the above dispersion and variations due to
temperatures into consideration.

When using the software contrast adjustment control function, Ra must be a variable resistance and the
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4.0 Functional Description 4.24 – 4.25
optimum contrast adjustment described in (4) must be made for each IC chip in order to compensate
the V5 voltage value due to the dispersion of VREG and IREF.

When the contrast control function is not used, set the register value to (D4, D3, D2, D1, D0) = (0, 0,
0, 0, 0) by the RES signal or electronic contrast control register set command.

4.25 PRECAUTIONS ON USING THE SED1560 SERIES SOFTWARE CONTRAST ADJUSTMENT

CONTROL FUNCTION
The SED1560 Series is provided with a software contrast adjustment control function having up to 32
levels to control the regulator. The V5 voltage, when the software contrast control function is used, is
represented by the following expression:

V5 = (1 + Rb / Ra). VREG + Rb × ∆IREF

By this expression, the software contrast control function controls an increment of V5 voltage by means
of the current source IREF built into the IC. (In the case of 32 levels, ∆IREF = IREF / 32).
The V5 minimum voltage is set by the resistance ratio of the externally-installed Ra and Rb, and the
voltage step width by the software contrast control is determined by the resistance value of Rb.

The reference voltage VREG and current source IREF built into the SED1560 Series are kept constant
against voltage variations.

However, IC manufacturing dispersion and variations due to temperatures are caused as shown below.

VREG = 2.5V ± 0.15V VREG = –0.17%/°C

IREF = 3.2µA ± 40% (for 16 levels) IREF = –0.0234 µA/°C
6.5µA ± 40% (for 32 levels) IREF = –0.0525 µA/°C

Example of Constant Setting

Conditions: Center value ............................. VDD – V5 = 8.5V
Variable voltage width ............... 3.2V
Variable voltage level................ 32 levels

(1) Determination of Rb.

VDD
Rb = V5 variable voltage width / IREF
= 3.2V / 6.5µA VREG
= 492 kΩ Ra
+
V5

VR –

Rb

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4.25 4.0 Functional Description
(2) Determination of Ra.
VREG
Ra =
(V5 minimum set voltage – VREG) / Rb

2.5V
=
{(8.5V – 3.2V/2) – 2.5V} / 492kΩ

= 280 kΩ

(3) Temperature dependency of V5 when VREG = 2.5V and IREF = 6.5µA (32 levels).
V5 minimum set voltage (V5 min) = 8.5V – 3.2V/2 = 6.9V

Ta = 25°C

V5 max = V5 minimum set voltage + Rb × IREF

= 6.9V + 492kΩ × 6.5 µA
= 10.1V ....................................... 1

V5 typ = (V5 max + V5 min) / 2

= (10.1V + 6.9V) / 2
= 8.5V ......................................... 2

Ta = –10°C

V5 min = (1 + Rb / R a) × VREG (Ta = –10°C)

= (1 + 492kΩ / 280kΩ) × 2.5V × {1 + (–0.17%/°C) × (–10°C – 25°C)}
= 7.3V ......................................... 3

V5 max = V5 min + Rb × IREF (Ta = –10°C)

= 7.3V + 492kΩ × {6.5µA + (–0.0525 µA/°C) × (–10°C – 25°C)}
= 11.4V ....................................... 4

V5 typ = (V5 max + V5 min) / 2

= (11.4V + 7.3V) / 2
= 9.35V ....................................... 5

Ta = 50°C

V5 min = (1 + Rb / R a) × VREG (Ta = 50°C)

= (1 + 492kΩ / 280kΩ) × 2.5V × {1 + (–0.17%/°C) × (50°C – 25°C)}
= 6.6V ......................................... 6

V5 max = V5 min + Rb × IREF (Ta = 50°C)

= 6.6V + 492kΩ × {6.5µA + (–0.0525 µA/°C) × (50°C – 25°C)}
= 9.15V ....................................... 7

V5 typ = (V5 max + V5 min) / 2

= (9.15V + 6.6V) / 2
= 7.9V ......................................... 8

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4.0 Functional Description 4.25

• To set the number of variable voltage levels to 16, specify IREF = 3.2µA.
• Margin calculation is performed by considering the dispersion of VREG and VREF according to the
same procedure as (3). From this margin calculation, it is made clear that the center value of V5 is
affected by variations of VREG and IREF.
• Accordingly, it is necessary to set the electronic contrast control register value to (D4, D3, D2, D1,
D0) = (1, 0, 0, 0, 0) or (0, 1, 1, 1, 1) and adjust the Ra value to the optimum contrast.
• The voltage step width by the electronic contrast control is changed by the dispersion of IREF. It is
necessary to consider that supposing that 0.2V/STEP is set by TYP value, the maximum variation
of 0.12V to 0.28V occurs.

SED 1560 Series

14

(V)

12
• 4

1
10
5 •
° 2 •
8

8 ° 7

∗ °
V5 3
∗ ∗
6

• V5 max
4
V5 typ
°
2 ∗ V5 min

0
–20 –10 0 10 20 30 40 50 60
Ta (°C)

Example of V5 voltage when using SED1560 Series electronic contrast control

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4.25 – 4.26 4.0 Functional Description
Since the IREF is a simplified constant current source, Table 4.8
when using the electronic contrast control function, it
becomes necessary to make adjustment to the opti- Type Liquid Crystal Driving Voltage
mum contrast as given in the above item (4), with each SED1560 1/9 of the bias voltage
of the IC chips, using the R a as a variable resistor. SED1561 1/7 of the bias voltage
SED1562 1/5 of the bias voltage
When not using the software contrast adjustment
control function, set the register to (D3, D2, D1, D0)
= (0, 0, 0, 0) using the RES signal or by means of the Table 4.9 Reference Setting Value
software contrast adjustment control register set-
Reference set values:
ting command.
SED1560 ..... V5 ≈ –11 ~ –13V
4.26 LIQUID CRYSTAL VOLTAGE SED1561 ..... V5 ≈ –7 ~ –9V
GENERATING CIRCUIT SED1562 ..... V5 ≈ –5 ~ –7V (Variable)
A V5 potential is resistively divided within the IC to SED1560 SED1561 SED1562
cause V1, V2, V3 and V4 potentials needed for driving C1 0.47µF~ 0.47µF~ 0.47µF~
of liquid crystals. The V1, V2, V3 and V4 potentials are
C2 1.0µF~ 0.47µF~ 0.47µF~
further converted in the impedance by the voltage
1.0µF~ 0.47µF~ 0.47µF~
follower before being supplied to the liquid crystal
R1 1MΩ 700KΩ 500KΩ
driving circuit.
R2 200KΩ 200KΩ 200KΩ
R3 4MΩ 1.6MΩ 700KΩ
The liquid crystal driving voltage is fixed with each
LCD 32 × 51 16 × 67 8 × 75
type (see Table 4.8). SIZE mm mm mm
DOT 64 × 102 32 × 134 16 × 150
As shown in Figure 4.13, it needs to connect, exter-
nally, 5 units of voltage stabilizing capacitors C2 to the
liquid crystal power terminals. When selecting such
capacitor C2, make actual liquid crystal displays
matching to the display capacity of the liquid crystal
display panel, before determining the capacitance as
the constant value for voltage stabilization.

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4.0 Functional Description 4.26

Rf *1 Rf
VDD
VDD

OSC1 OSC2 M/S

OSC1 OSC2 M/S

VSS
VSS CL
CAP1+
CAP1+
C1 CAP1–
CAP1– VSS
C1 CAP2+
CAP2+
C1 CAP2–
CAP2–
VOUT
VOUT
R3 V5
V5
VR SED156X
R2 VR SED156X
*2
R1 VDD
VDD
V1
V1 External V2
V2 supply V3
C2 V3 voltage
V4
V4 V5
V5

Figure 4.13 Figure 4.14

When the built-in power supply is used When external LCD power supply is used
*1 Connect oscillator feedback resistor Rf as
short as possible and place it close to the
IC for preventing a malfunction.
*2 Use short wiring or shielded cables for the
VR pin due to high input impedance.
*3 Determine C1 and C2 depending on the
size of the LCD panel driven. You must set
these values so that the LCD driving volt-
age becomes stable. Set (T1, T2) = (H, L)
and supply an external voltage to VOUT.
Display the LCD heavy load pattern and
determine C2 so that the LCD driving
voltages (V1 to V5) become stable. How-
ever, it is necessary to make every C2
capacitance value equal. Then, set (T1,
T2) = (L, L) and determine C1.
*4 The “LCD SIZE” indicates the vertical
and horizontal length of the LCD panel
display area.

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4.27 4.0 Functional Description
4.27 RESET
When power is turned ON, the SED1560 Series is
initialized on the rising edge of RES. Initial settings are
as follows:
1. Display : OFF
2. Display mode : Normal
3. n-line inversion : OFF
4. Duty cycle : 1/64
5. ADC select : Normal
6. Read/write modify : OFF
7. On-chip power supply : OFF
8. Serial interface register : Cleared
9. Display initial line register : Line 1
10. Column address counter : 0
11. Page address register : Page 0
12. Output selection circuit : Case 6
13. n-line inversion register : 16
14. Software contrast setting : zero

The RES pin should be connected to the microproces-

sor reset terminal so that both devices are reset at the
same time. RES must be LOW for at least 1 µs to
correctly reset the SED1560 Series. Normal opera-
tion starts 1 µs after the rising edge on RES.

If the SED1560 Series is not properly initialized when

power is turned ON, it can lock itself into a state that
cannot be cancelled.

When the Reset command is used, only initial set-

tings 9 to 14 are active.

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 5.0
Commands

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 THIS PAGE INTENTIONALLY BLANK

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5.0 Commands 5.1
5.1 COMMAND SUMMARY
A0, RD and WR identify the data bus commands. normally not needed, commands can be processed at
Interpretation and execution of commands are syn- high speed. When the serial interface is used, the
chronized to the internal clock. Since a busy check is order of data entry is D7 to D0.
Table 5.1
Code
Command Description
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Turns the display ON and OFF.
Display ON/OFF 0 1 0 1 0 1 0 1 1 1 D D = 0 OFF
D = 1 ON
Sets the display RAM line address for
Initial display line 0 1 0 0 1 Display line address
COM0.
Page address set 0 1 0 1 0 1 1 Page address Sets the RAM page address register.
Column address set Column address Sets the column address register upper
0 1 0 0 0 0 1
(upper four bits) upper four bits four bits.
Column address set Column address Sets the column address register lower
0 1 0 0 0 0 0
(lower four bits) lower four bits four bits.
Read status 0 0 1 Status 0 0 0 0 Reads out status information.
Write display data 1 1 0 Write data Writes to display RAM.
Read display data 1 0 1 Read data Reads from display RAM.
Sets the display RAM segment output.
Select ADC 0 1 0 1 0 1 0 0 0 0 D
D = 0 Normal D = 1 Inverse
Normal/inverse Sets the LCD display mode.
0 1 0 1 0 1 0 0 1 1 D
display D = 0 Normal D = 1 Inverse
Sets the segments display mode.
Display all points
0 1 0 1 0 1 0 0 1 0 D D = 0 Normal
ON/OFF
D = 1 All display segments ON
Sets the LCD controller duty (1).
Select duty 0 1 0 1 0 1 0 1 0 0 D
D = 0, D=1 See Table 5.3
Sets the LCD controller duty (2).
Duty + 1 0 1 0 1 0 1 0 1 0 1 D
D = 0 Normal D = 1 Duty + 1
Number of Sets the number of inverted lines in the in-
Set n-line inversion 0 1 0 0 0 1 1
inverted items version register for the inversion controller.
Cancel n-line inversion 0 1 0 0 0 1 0 0 0 0 0 Cancels line inversion display mode.
Sets modified read mode. The column
Read Modify Write 0 1 0 1 1 1 0 0 0 0 0 address counter is not incremented when
reading.
End 0 1 0 1 1 1 0 1 1 1 0 Cancels modified read mode.
Power-on 0 1 0 1 1 1 0 1 1 0 1 Completes the turn-on sequence of built-
completion in power supply
Reset 0 1 0 1 1 1 0 0 0 1 0 Resets the internal registers.
Sets the common and segment output
Output status set 0 1 0 1 1 0 0 Output status
status register.
LCD power supply Turns the power supply ON and OFF.
0 1 0 0 0 1 0 0 1 0 D
ON/OFF D = 0 OFF D = 1 ON

Software contrast Electronic contrast control Setting the V5 output voltage to the elec-
0 1 0 1 0 0
setting resistance value tronic contrast control register.

A complex command to turn off the display

Power save
and light all indicators.

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5.2 – 5.2.4 5.2 Command Definitions
5.2 COMMAND DEFINITIONS
5.2.1 Display ON/OFF
A3 A2 A1 A0 Page
Alternately turns the display ON and OFF.
0 0 0 0 0
R/W
0 0 0 1 1
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 2
0 1 0 1 0 1 0 1 1 1 D
0 0 1 1 3
Note: 0 1 0 0 4
D=0 Display OFF
D=1 Display ON 0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
5.2.2 Initial Display Line 1 0 0 0 8
Loads the RAM line address of the initial display line,
COM0, into the initial display line register. The RAM
display data becomes the top line of the LCD screen. 5.2.4 Column Address Set
It is followed by the higher number lines in ascending Loads the RAM column address from the micropro-
order, corresponding to the duty cycle. The screen cessor into the column address register. The column
can be scrolled using this command by incrementing address is divided into two parts—4 high-order bits
the line address. and 4 low-order bits.
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 When the microprocessor reads or writes display
0 1 0 0 1 A5 A4 A3 A2 A1 A0 data to or from RAM, column addresses are auto-
matically incremented, starting with the address
stored in the column address register and ending
A5 A4 A3 A2 A1 A0 Line Address
with address 166.
0 0 0 0 0 0 0
0 0 0 0 0 1 1 The page address is not incremented automatically.
0 0 0 0 1 0 2 R/W
↓ ↓ A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 0 62 0 1 0 0 0 0 1 A7 A6 A5 A4
1 1 1 1 1 1 63
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
5.2.3 Page Address Set
0 1 0 0 0 0 0 A3 A2 A1 A0
Loads the RAM page address from the microproces-
sor into the page address register. A page address,
along with a column address, defines a RAM location Column
A7 A6 A5 A4 A3 A2 A1 A0
Address
for writing or reading display data. When the page
address is changed, the display status is not affected. 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1
Page address 8 is a special use RAM area for the ↓ ↓
indicator. Only D0 is available for data exchange. 1 0 1 0 0 1 0 1 165
R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 0 1 1 A3 A2 A1 A0

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5.2 Command Definitions 5.2.5 – 5.2.9
5.2.5 Read Status 5.2.7 Read Display Data
Indicates to the microprocessor the SED1560 Series Sends bytes of display data to the microprocessor
status conditions. from the RAM location specified by the column ad-
R/W dress and page address registers. The column ad-
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 dress is incremented automatically so that the micro-
processor can continuously read data from the ad-
ON/ RE-
0 0 1 BUSY ADC
OFF SET 0 0 0 0 dressed page. A dummy read is required after loading
an address into the column address register.
• BUSY - Indicates whether or not the SED1560
Series will accept a command. If BUSY is 1, Display data cannot be read through the serial interface.
the device is currently executing a command R/W
or is resetting, and no new commands can A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
be accepted. If BUSY is 0, a new command 1 0 1 Read data
can be accepted. It is not necessary for the
microprocessor to check the status of this bit
if enough time is allowed for the last cycle to 5.2.8 Select ADC
be completed.
Selects the relationship between the RAM column
• ADC - Indicates the relationship between RAM addresses and the segment drivers. When reading or
column addresses and the segment drivers. writing display data, the column address is incremented
If ADC is 1, the relationship is normal and as shown in Figure 5.4.
column address n corresponds to segment
R/W
driver n . If ADC is 0, the relationship is
inverted and column address (165 – n) cor- A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
responds to segment driver n. 0 1 0 1 0 1 0 0 0 0 D
• ON/OFF - Indicates whether the display is Note:
ON or OFF. If ON/OFF is 1, the display is D = 0 Rotate right (normal direction)
OFF. If ON/OFF is 0, the display is ON. D = 1 Rotate left (reverse direction)
Note that this is the opposite of the Display
ON/OFF command. The output pin relationship can also be changed by the
• RESET - Indicates whether initialization is microprocessor. There are very few restrictions on pin
in process as the result of RES or the assignments when constructing an LCD module.
Reset command.

5.2.9 Normal/Inverse Display

5.2.6 Write Display Data Determines whether the data in RAM is displayed
normally or inverted.
Writes bytes of display data from the microproces-
R/W
sor to the RAM location specified by the column
address and page address registers. The column A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
address is incremented automatically so that the 0 1 0 1 0 1 0 0 1 1 D
microprocessor can continuously write data to the Note:
addressed page. D = 0 LCD segment is ON when RAM data is 1 (normal).
R/W D = 1 LCD segment is ON when RAM data is 0 (inverse).
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 Write data

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5.2.10 – 5.2.14 5.2 Command Definitions
5.2.10 Display All Points ON/OFF the RAM area corresponding to page address 8, D0.
Turns all LCD points ON independently of the display (Refer to Figure 5.4.)
data in RAM. The RAM contents are not changed.
In multi-chip configuration, the Duty + 1 command
This command has priority over the normal/inverse must be executed to both the master and slave sides.
display command. R/W
R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 0 1 D
0 1 0 1 0 1 0 0 1 0 D
Note:
Table 5.3
D = 0 Normal display status Model D Duty
D = 1 All display segments ON 0 1/48 or 1/64
SED1560
1 1/49 or 1/65
If this command is received when the display status is
OFF, the Power Save command is executed. 0 1/24 or 1/32
SED1561
1 1/25 or 1/33
0 1/16
SED1562
5.2.11 Select Duty 1 1/17
Selects the LCD driver duty.

Since this is independent from the contents of the 5.2.13 Set n-line Inversion
output status register, the duty must be selected Selects the number of inverse lines for the LCD AC
according to the LCD output status. controller. The value of n is set between 2 and 16 and
is stored in the n-line inversion register.
In multi-chip configuration, the master and slave de- R/W
vices must have the same duty.
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
R/W
0 1 0 0 0 1 1 A3 A2 A1 A0
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 0 1 0 1 0 0 D A3 A2 A1 A0 Number of Inverted Lines
0 0 0 0 —
Table 5.2 0 0 0 1 2
Model D Duty 0 0 1 0 3
0 1/48 ↓ ↓
SED1560
1 1/64 1 1 1 0 15
0 1/24 1 1 1 1 16
SED1561
1 1/32
0 1/16
SED1562 5.2.14 Cancel n-line Inversion
1 1/16
Cancels n -line inversion and restores the normal 2-
frame AC control. The contents of the n-line inversion
5.2.12 Duty + 1 register are not changed.
Increases the duty by 1. If 1/48 or 1/64 duty is selected R/W
in the SED1560, for example, 1/49 or 1/65 is set, A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
respectively, and COM1 functions as either the COM48 0 1 0 0 0 1 0 0 0 0 0
or COM64 output. The display line always accesses

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5.2 Command Definitions 5.2.15 – 5.2.17
5.2.15 Modify Read
Following this command, the column address is no
longer incremented automatically by a Read Display Page address set
Data command. The column address is still
incremented by the Write Display Data command.
This mode is cancelled by the End command. The Column address set
column address is then returned to its value prior to
the Modify Read command. This command makes it
easy to manage the duplication of data from a particu-
lar display area for features such as cursor blinking.
R/W Read–modify–write cycle
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 0 0 0 0
Note: the Column Address Set command cannot be used in Dummy read
modify-read mode.

5.2.16 End Data read

Cancels the modify read mode. The column address
prior to the Modify Read command is restored.
R/W Data write
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 1 1 1 0

No Changes
5.2.17 Reset
finished?
Resets the initial display line, column address, page
address, and n-line inversion registers to their initial
values. This command does not affect the display Yes
data in RAM.
R/W END
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1 0 0 0 1 0
Figure 5.1
The reset command does not initialize the LCD power Command sequence for cursor blinking
supply. Only hardware RES can be used to initialize
the power supplies.

Return
Column
N N+1 N+2 N+3 N+m N
address
Read–modify–write mode set End

Figure 5.2

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5.2.18 – 5.2.20 5.2 Command Definitions
5.2.18 Output Status Set 5.2.20 LCD Power Supply ON/OFF
Selects the common or segment output state of the Turns the SED1560 Series LCD power supply ON or
LCD driver dual outputs. The A3 bit selects the scan OFF. When the power supply is ON, the voltage
direction of the outputs. converter, the voltage regulator circuit and the volt-
R/W age followers are operating. In order for the converter
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 to function, the oscillator must also be operating.
0 1 0 1 1 0 0 A3 A2 A1 A0 R/W
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 0 1 0 0 1 0 0
5.2.19 Output Status Register 2 4 OFF
Available only in the SED1560 and SED1561. Note:
D = 0 Supply OFF (24H)
This command selects the role of the COM/SEG dual D = 1 Supply ON (25H)
pins and determines the LCD driver output status.
When an external power supply is used with the
The COM output scanning direction can be selected SED1560 Series, the internal supply must be OFF.
by setting A3 to “H” or “L”. For details, refer to the
Output Status Circuit in each function description. If the SED1560 Series is used in a multiple-chip
R/W configuration, an external power supply that meets
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 the specifications of the LCD panel must be used. An
SED1560 Series operating as a slave must have its
0 1 0 1 1 0 0 A3 A2 A1 A0
internal power supply turned OFF.
A3: Selection of the COM output scanning direction

Table 5.4 Sequence in the Built-In Power ON/OFF Status

Number of To turn on internal power supply, execute the follow-
Output
A2 A1 A0 COM/SEG Remarks
Status ing built-in power supply ON sequence. To turn off
Output Pins
internal power supply, execute the power save se-
Applies to the
0 0 0 Case 6 SEG 166 SED1560/61 quence as shown in the following power supply OFF
0 0 1 Case 5 SEG 134, COM 32
status.
Applies to the
0 1 0 Case 4 SEG 134, COM 32
SED1561 Accordingly, to turn on internal power supply again
0 1 1 Case 3 SEG 134, COM 32
after turn it off (power save), execute the “Power Save
1 0 0 Case 2 SEG 102, COM 64 Applies to the
Clear Sequence” that is described below.
1 0 1 Case 1 SEG 102, COM 64 SED1560
1 1 0 Case 6 SEG 166 Applies to the
1 1 1 Case 6 SEG 166 SED1560/61

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5.2 Command Definitions 5.2.20
Sequence in the Power Save Status
Power Save and Power Save Clear must be executed When using an external power supply, likewise, its
according to the following sequence. function must be stopped before or concurrently
with putting the SED1560 Series into the power
To give a liquid crystal driving voltage level by the save status so that it may be fixed to the floating or
externally-installed resistance dividing circuit, the VDD level. In a configuration in which an exclusive
current flowing in this resistance must be cut before common driver such as SED1630 is combined with
or concurrently with putting the SED1560 Series the SED1560 Series, it is necessary to stop the
into the power save status so that it may be fixed to external power supply function after putting all the
the floating or VDD level. common output into non-selection level.

Power Save Sequence Power Save Clear Sequence

*3 Output Status Select command C*(H)

Display OFF command AE(H)

*2 *DUTY+1 command AB(H)

*3 Output Status case 6 command CF(H) Internal Power Supply ON command 25(H)

*2 *DUTY+1 Clear command AA(H) *1 Display All ON Status OFF

*1 Display all ON command A5(H) *6 (Waiting time)

*5 Power Supply Startup End command ED(H)

*1. In the power save sequence, the power *5. When internal power supply startup end
save status is provided after the display all command is not executed, current is con-
ON command. In the power save clear se- sumed stationarily. Internal power supply
quence, the power save status is cleared startup end command must always be used
after the display all ON status OFF com- in a pair with internal power supply ON
mand. command.
*2. When the COMI pin is not used, it is not *6. The waiting time depends on the externally-
necessary to enter the DUTY + 1 command installed capacitance C2 (refer to Table 5.9).
and DUTY + 1 clear command. After the waiting time shown in the graph
*3. In the SED1562, it is not necessary to ex- above (see bottom of previous page), the
ecute a command to decide an output sta- power supply can be started surely.
tus.
*4. The display ON command can be executed
anywhere if it is later than the display all ON
status OFF command.

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5.2.20 5.2 Command Definitions
Internal Power Supply ON Status Internal Power Supply OFF Status

Reset by RES signal

*1 Output Status Select command A*(H) Display OFF command AE(H)

*2 *DUTY+1 command AB(H) Output Status case 6 command CF(H)

Internal Power Supply ON command 25(H) *2 *DUTY+1 Clear command AA(H)

*4,5 (Waiting time) Display all ON command A5(H)

*3 Power Supply Startup End command ED(H)

*1. Regarding the SED1562, it is not neces- After the waiting time shown in the graph
sary to execute a command to decide an below, the power supply can be started surely.
output status. *5. Within the waiting time in internal power
*2. When the COMI pin is not used, it is not supply ON status, any command other than
necessary to enter the DUTY + 1 and DUTY internal power supply control commands
+ 1 Clear commands. such as Power Save, and display ON/OFF
*3. When the built-in power supply startup command, display normal rotation/reverse
end command is not executed, current is command, display all ON command, output
consumed stationarily. Internal power sup- status select command and DUTY + 1 clear
ply startup end command must always be command can accept another command
used in a pair with internal power supply without any problem. RAM read and write
ON command. operations can be freely performed.
*4. The waiting time depends on the externally-
installed capacitance C2 (refer to Table 5.9).

120
(mS)
100
80 V5 voltage conditions
Waiting
1/9 bias 1/9 bias V5 = –6.0 to –16.0 V
time 60 1/7 bias V5 = –5.0 to –12.0 V
1/7 bias
40 1/5 bias V5 = –4.5 to –8.0 V

20
1/5 bias
0 0.5 1.0
Capacitance C2 (µF)

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5.3 Software Contrast Control Register 5.3 – 5.3.2
5.3 SOFTWARE CONTRAST CONTROL (a) The oscillator and power supply circuits are
REGISTER stopped.
Through these commands, the liquid crystal driving (b) The LCD driver is stopped and segment and
voltage V5 is output from the voltage regulation circuit common driver outputs output the VDD level.
of the built-in liquid crystal power supply, in order to (c) An input of an external clock is inhibited and
adjust the contrast of the liquid crystal display. OSC2 enters the high-impedance state.
(d) The display data and operation mode be-
By setting data to the 5-bit register, one of the 32 fore execution of the power save com-
voltage statuses may be selected for the liquid crystal mand are held.
driving voltage V5. External resistors are used for
(e) All LCD driver voltages are fixed to the
setting the voltage regulation range of the V5. For
VDD level.
details refer to the paragraph of the voltage regulation
circuit in the clause for the explanation of functions.
The power save mode is cancelled by entering either
R/W
the Display ON command or the Display All Points
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
OFF command (display operation state). When exter-
0 1 0 1 0 0 A4 A3 A2 A1 A0 nal voltage driver resistors are used to supply the LCD
driver voltage level, the current through them must be
A4 A3 A2 A1 A0 | V5 | cut off by the power save signal.
0 0 0 0 0 Small (as the absolute value)
↓ ↓ If an external power supply is used, it must be
1 1 1 1 1 Large (as the absolute value)
turned OFF using the power save signal in the
same manner, and voltage levels must be fixed to
When not using the electronic contrast control func- the floating or VDD level.
tion, set to (0, 0, 0, 0).

5.3.2 Connection between LCD Drivers

5.3.1 Power Save (Complex Command) The LCD display area can be increased by using
If the Display All Points ON command is specified in the SED1560 Series in a multiple-chip configura-
the display OFF state, the system enters the power tion or with the SED1560 Series special common
save status, reducing the power consumption to ap- driver (SED1630).
proximate the static power consumption value. The
internal state in the power save status is as follows:

VDD
SED1630 FR FR SED156X M/S
SYNC (Master)
DIO YSCL OSC1 OSC2 CL CLO DYO
Rf
VSS

Figure 5.3 Application with external driver: SED156X – SED1630

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5.3.2 5.3 Electronic Contrast Control Register

VDD
M/S SED156X FR FR SED156X M/S
(Master) SYNC SYNC (Slave) VSS
OSC1 OSC2 CL CLO DYO OSC1 OSC2 CL CLO DYO
Rf VSS VSS

VDD
M/S SED156X FR FR SED156X M/S
(Master) SYNC SYNC (Slave)
OSC1 OSC2 CL CLO DYO VDD OSC1 OSC2 CL CLO DYO
VSS VSS
Rf

Figure 5.4 SED156X – SED156X (when oscillator circuit is used)

VDD
M/S SED156X FR FR SED156X M/S
(Master) SYNC SYNC (Slave) VSS
OSC1 OSC2 CL CLO DYO VDD OSC1 OSC2 CL CLO DYO
VSS VSS

External clock

Figure 5.5 SED156X – SED156X (External clock)

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5.4 Microprocessor Interface 5.4
5.4 MICROPROCESSOR INTERFACE
The SED1560 Series communicates with a high- microprocessor can be minimized by using a serial
speed microprocessor, such as the Intel 80XX family interface. When used in a multiple-chip configuration,
or the Motorola 68XX family, through 8-bit parallel the SED1560 Series is controlled by the chip select
data transfer. The number of connections to the signals from the microprocessor.

VCC A0 A0 VDD
C86
A0 to A7 CS1
Decoder
MPU CS2 SED156X
IORQ

D0 to D7 D0 to D7

RD RD
WR WR P/S
RES RES
GND VSS

RESET

Figure 5.6 8080-series microprocessors

VCC A0 A0 VDD
C86
A0 to A15 CS1
Decoder
MPU CS2 SED156X
VMA

D0 to D7 D0 to D7

E E
R/W R/W P/S
RES RES
GND VSS

RESET

Figure 5.7 6800-series microprocessors

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5.4 – 5.5 5.4 Microprocessor Interface

VCC A0 A0 VDD
C86
A0 to A7 CS1
Decoder
MPU CS2 SED156X VDD
or
GND
PORT1 SI
PORT2 SCL
P/S
RES RES
GND VSS

RESET

Figure 5.8 Serial interface

5.5 LCD PANEL INTERFACE EXAMPLES

65 × 102

Segments

SED1560
Commons
(Master)

Case 1

33 × 134 17 × 150

Segments Segments

SED1561
Commons Commons SED1562
(Master)

Case 4

Figure 5.9 Single-chip configurations

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5.5 LCD Panel Interface Examples 5.5

65 × 268

Segments Segments

SED1560 SED1560
Commons
(Master) (Slave)

Case 1 Case 6

33 × 300

Segments Segments

SED1561 SED1561
Commons
(Master) (Slave)

Case 4 Case 6

Figure 5.10 Multiple-chip combinations

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5.6 5.6 Special Common Driver Configurations
5.6 SPECIAL COMMON DRIVER CONFIGURATIONS

SED1630 Commons 65 × 166

Segments

SED1560
(Master)

Case 6

Case 6

SED1560
(Master)

Segments

Commons

SED1631 128 × 166

Commons

Segments

SED1560
(Slave)

Case 6

Figure 5.11 Special common driver configurations

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 6.0
Packaging

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 THIS PAGE INTENTIONALLY BLANK

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6.0 Pad Layout 6.1
6.1 PAD LAYOUT

O45

O0
O46 V5
V4
V3
V2
V1
VDD
VR
V5
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
SED156X D7
D6
D5
D4
D3
D2
D1
D0
VSS
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
VDD
V1
V2
V3
V4
O120 V5
O121

O165
COM1

Chip Size : 8.08 × 5.28 mm

Pad Pitch : 100 µm (min)
Chip thickness : 625 µm ± 25 µm

Figure 6.1 Pad layout

174-3.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 75
6.1 6.0 Pad Layout
Table 6.1 SED1560 Series Pad Center Coordinates
Pad Pin Pad Pin Pad Pin Pad Pin
X Y X Y X Y X Y
No. Name No. Name No. Name No. Name
1 V5 3640 2487 55 O5 –3887 1794 109 O59 –2411 –2487 163 O113 2989 –2487
2 V4 3489 2487 56 O6 –3887 1694 110 O60 –2311 –2487 164 O114 3089 –2487
3 V3 3339 2487 57 O7 –3887 1594 111 O61 –2211 –2487 165 O115 3189 –2487
4 V2 3188 2487 58 O8 –3887 1494 112 O62 –2111 –2487 166 O116 3289 –2487
5 V1 3037 2487 59 O9 –3887 1394 113 O63 –2011 –2487 167 O117 3389 –2487
6 VDD 2889 2487 60 O10 –3887 1294 114 O64 –1911 –2487 168 O118 3489 –2487
7 M/S 2755 2487 61 O11 –3887 1194 115 O65 –1811 –2487 169 O119 3589 –2487
8 RES 2604 2487 62 O12 –3887 1094 116 O66 –1711 –2487 170 O120 3689 –2487
9 SCL 2453 2487 63 O13 –3887 994 117 O67 –1611 –2487 171 O121 3887 –2206
10 SI 2302 2487 64 O14 –3887 894 118 O68 –1511 –2487 172 O122 3887 –2106
11 P/S 2151 2487 65 O15 –3887 794 119 O69 –1411 –2487 173 O123 3887 –2006
12 CS1 2001 2487 66 O16 –3887 694 120 O70 –1311 –2487 174 O124 3887 –1906
13 CS2 1850 2487 67 O17 –3887 594 121 O71 –1211 –2487 175 O125 3887 –1806
14 C86 1699 2487 68 O18 –3887 494 122 O72 –1111 –2487 176 O126 3887 –1706
15 A0 1548 2487 69 O19 –3887 394 123 O73 –1011 –2487 177 O127 3887 –1606
16 WR 1397 2487 70 O20 –3887 294 124 O74 –911 –2487 178 O128 3887 –1506
17 RD 1247 2487 71 O21 –3887 194 125 O75 –811 –2487 179 O129 3887 –1406
18 VSS 1077 2487 72 O22 –3887 94 126 O76 –711 –2487 180 O130 3887 –1306
19 D0 945 2487 73 O23 –3887 –6 127 O77 –611 –2487 181 O131 3887 –1206
20 D1 794 2487 74 O24 –3887 –106 128 O78 –511 –2487 182 O132 3887 –1106
21 D2 643 2487 75 O25 –3887 –206 129 O79 –411 –2487 183 O133 3887 –1006
22 D3 493 2487 76 O26 –3887 –306 130 O80 –311 –2487 184 O134 3887 –906
23 D4 342 2487 77 O27 –3887 –406 131 O81 –211 –2487 185 O135 3887 –806
24 D5 191 2487 78 O28 –3887 –506 132 O82 –111 –2487 186 O136 3887 –706
25 D6 40 2487 79 O29 –3887 –606 133 O83 –11 –2487 187 O137 3887 –606
26 D7 –111 2487 80 O30 –3887 –706 134 O84 89 –2487 188 O138 3887 –506
27 DYO –261 2487 81 O31 –3887 –806 135 O85 189 –2487 189 O139 3887 –406
28 CLO –412 2487 82 O32 –3887 –906 136 O86 289 –2487 190 O140 3887 –306
29 SYNC –563 2487 83 O33 –3887 –1006 137 O87 389 –2487 191 O141 3887 –206
30 FR –714 2487 84 O34 –3887 –1106 138 O88 489 –2487 192 O142 3887 –106
31 CL –865 2487 85 O35 –3887 –1206 139 O89 589 –2487 193 O143 3887 –6
32 OSC2 –1015 2487 86 O36 –3887 –1306 140 O90 689 –2487 194 O144 3887 94
33 OSC1 –1166 2487 87 O37 –3887 –1406 141 O91 789 –2487 195 O145 3887 194
34 T2 –1317 2487 88 O38 –3887 –1506 142 O92 889 –2487 196 O146 3887 294
35 T1 –1468 2487 89 O39 –3887 –1606 143 O93 989 –2487 197 O147 3887 394
36 VSS –1638 2487 90 O40 –3887 –1706 144 O94 1089 –2487 198 O148 3887 494
37 CAP1+ –1789 2487 91 O41 –3887 –1806 145 O95 1189 –2487 199 O149 3887 594
38 CAP1– –1939 2487 92 O42 –3887 –1906 146 O96 1289 –2487 200 O150 3887 694
39 CAP2+ –2090 2487 93 O43 –3887 –2006 147 O97 1389 –2487 201 O151 3887 794
40 CAP2– –2241 2487 94 O44 –3887 –2106 148 O98 1489 –2487 202 O152 3887 894
41 VOUT –2392 2487 95 O45 –3887 –2206 149 O99 1589 –2487 203 O153 3887 994
42 V5* –2543 2487 96 O46 –3711 –2487 150 O100 1689 –2487 204 O154 3887 1094
43 VR –2674 2487 97 O47 –3611 –2487 151 O101 1789 –2487 205 O155 3887 1194
44 VDD –2844 2487 98 O48 –3511 –2487 152 O102 1889 –2487 206 O156 3887 1294
45 V1 –2995 2487 99 O49 –3411 –2487 153 O103 1989 –2487 207 O157 3887 1394
46 V2 –3146 2487 100 O50 –3311 –2487 154 O104 2089 –2487 208 O158 3887 1494
47 V3 –3297 2487 101 O51 –3211 –2487 155 O105 2189 –2487 209 O159 3887 1594
48 V4 –3447 2487 102 O52 –3111 –2487 156 O106 2289 –2487 210 O160 3887 1694
49 V5 –3598 2487 103 O53 –3011 –2487 157 O107 2389 –2487 211 O161 3887 1794
50 O0 –3887 2294 104 O54 –2911 –2487 158 O108 2489 –2487 212 O162 3887 1894
51 O1 –3887 2194 105 O55 –2811 –2487 159 O109 2589 –2487 213 O163 3887 1994
52 O2 –3887 2094 106 O56 –2711 –2487 160 O110 2689 –2487 214 O164 3887 2094
53 O3 –3887 1994 107 O57 –2611 –2487 161 O111 2789 –2487 215 O165 3887 2194
54 O4 –3887 1894 108 O58 –2511 –2487 162 O112 2889 –2487 216 COMI 3887 2294
* One V5 output is used for the LCD driver supply voltage; the other is used for the electronic volume control.

76 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 174-3.0
6.2 SED1560 Series TAB Pin Layout 6.2
6.2 SED1560/1/2 TAB PIN LAYOUT

This drawing is not for specifying the TAB outline shape.

O0

V5
V4
V3
V2
V1
VDD
VR
V5
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
SED156X D7
TOP D6
VIEW D5
D4
D3
D2
D1
D0
VSS
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
VDD
V1
V2
V3
V4
V5
O165
COMI

Figure 6.2 SED1560 Series TAB pin layout

174-3.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 77
6.3 6.3 TCP Dimensions (2-sided)
6.3 TCP DIMENSIONS (2-SIDED) SED156XT0B

SED1560T0B
MAX 0.15
MAX 1.0
MAX 0.8

X(+)
NC x 2
00
8.8

NC

ø1.7
V5
V4

V3

V2

60
V1
1.5
VDD

5 VR

D1 V5
VOUT

CAP2–
CAP2+

CAP1–
CAP1+

Note 1: Resist position tolerance: ±0.3

VSS

T1
T2

OSC1

2: Product pitch: 52.25mm

OSC2

CL
FR

SYNC
CLO
DYO

D7
Y(+)

36.00
40.00
44.00
47.5

D6
D5

D4
0.28

D3
0.80

D2
D1
D0

VSS

RD
WR
A0

C86

CS2
CS1

P/S

SI

SCL

RES
M/S

VDD
ø2.10 SR
ø1.50 PI

V1

V2

V3
V4

V5

NC

4.40
NC x 2
0.5
COM1
0165

5.34 15.16 2.70

28.98 ± 0.04

Figure 6.3 TCP dimensions (2-sided)

78 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 174-3.0
6.4 TCP Dimensions (4-sided) 6.4
6.4 TCP DIMENSIONS (4-SIDED) SED156XT0A

MAX 0.15
MAX 0.8
MAX 1.0

4 – RO. 2

4 – RO. 2
X(+)
0.30

0
56
D1
Y (+)

18.00

22.50
26.95
0.30
60
15
D

D1560 0.60

25.95
31.82
34.9750

Figure 6.4 TCP dimensions (4-sided)

174-3.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 79
6.5 6.5 TCP Dimensions (D1561TOC)
6.5 TCP DIMENSIONS (SED1561TOC)

0.01
28.98±0.07

8.50 (SR) 6.66 (SR) 5.34

10.23 (SR) 2.54 2.39

(SR) (SR)
NCX2
0.11±0.02
0.14±0.02

4.40 COM1
0165
•
•
•
NC
0.14

V5
V4
V3

ø 2.10 SR
V2

ø 1.50 PI
V1
VDD
M/S
RES
SCL
SI
P/S
CS1
CS2
C86
A0

PO. 28 x 171 – 1 = 47.60±0.06 (W 0.14, G 0.14)

WR
RD
PO. 80 x 51 – 1 = 40.00 (W 0.4, G 0.4)

VSS
D0
D1
D2
D3 5.28 (IC)

0.14
0.28
0.80
0.40

D4
MAX 11.08
8.08 (IC)

D5
36.00

48.34 (SR)
41.00 (SR)

Y (+)
D6
D7
DYO MAX 8.28
CLO 1.98±0.01
SYNC
FR
CL

4.75 ± 0.01
OSC2
OSC1
T2
T1
VSS
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
V5
VR
VDD
V1
1.5
V2
V3
V4
V5
ø 1.7

NC

•
•
•
00
NCX2
X (+)

ø 2.0

MAX 1.50 MAX 1.50

MAX 0.8
MAX 1.0

MAX 1.50 MAX 1.50

IC : SED1561DOB

Figure 6.5 TCP dimensions (D1561TOC)

80 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 174-3.0
6.6 Pad Profile 6.6
6.6 PAD PROFILE

TBD

174-3.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 81
6.7 6.7 BGA Package Dimensions
6.7 BGA PACKAGE DIMENSIONS

D1

15
14
13
12
11
10
9

E1

E
SED1560BOA 8
7
6
5
INDEX
4
4–C2 3
2
1

4–C1 Q P N M L K J H G F E D C B A

Ø2
A2
A

e øb A1

Figure 6.7 Plastic BGA 225pin

Table 6.2 BGA 225pin package dimensions

Dimension in Millimeters Dimension in inches*

Symbol
Min. Nom. Max. Min. Nom. Max.
øb 0.6 0.75 0.90 (0.024) (0.030) (0.035)
A 2.13 (0.084)
A1 0.5 0.6 0.7 (0.020) (0.024) (0.027)
A2 1.43 1.53 1.63 (0.057) (0.060) (0.064)
θ2 25° (25°)
C1 1.5 (0.059)
C2 1.2 (0.047)
e 1.5 (0.059)
D1 23.9 24 24.1 (0.941) (0.945) (0.948)
E1 23.9 24 24.1 (0.941) (0.945) (0.948)
D 27 (1.063)
E 27 (1.063)
* for reference

82 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 174-3.0
6.8 BGA Pin Assignment 6.8
6.8 BGA PIN ASSIGNMENT
SED1560 SED1560 BGA225 SED1560 SED1560 BGA225 SED1560 SED1560 BGA225 SED1560 SED1560 BGA225 N/C
pad# pin name pin# pad# pin name pin# pad# pin name pin# pad# pin name pin#
1 V5 B-2 55 05 R-2 109 059 K-10 163 0113 D-12 J-7
2 V4 D-4 56 06 P-3 110 060 M-13 164 0114 B-14 H-7
3 V3 B-1 57 07 K-6 111 061 N-15 165 0115 A-15 G-7
4 V2 C-2 58 08 N-4 112 062 M-14 166 0116 C-13 J-8
5 V1 F-6 59 09 R-3 113 063 J-10 167 0117 A-14 H-8
6 VDD D-3 60 010 P-4 114 064 L-12 168 0118 B-13 G-8
7 M/S C-1 61 011 K-7 115 065 M-15 169 0119 E-11 J-9
8 /RES D-2 62 012 M-5 116 066 L-13 170 0120 C-12 H-9
9 SCL G-6 63 013 R-4 117 067 L-14 171 0121 A-13 G-9
10 SI E-4 64 014 N-5 118 068 K-11 172 0122 B-12
11 P/S D-1 65 015 P-5 119 069 L-15 173 0123 F-9
12 /CS1 E-3 66 016 L-6 120 070 K-12 174 0124 D-11
13 CS2 E-2 67 017 R-5 121 071 K-13 175 0125 A-12
14 C86 F-5 68 018 M-6 122 072 K-14 176 0126 C-11
15 A0 E-1 69 019 N-6 123 073 K-15 177 0127 B-11
16 /WR F-4 70 020 P-6 124 074 J-12 178 0128 E-10
17 /RD F-3 71 021 R-6 125 075 J-13 179 0129 A-11
18 VSS F-2 72 022 M-7 126 076 J-14 180 0130 D-10
19 D0 F-1 73 023 N-7 127 077 J-15 181 0131 C-10
20 D1 G-4 74 024 P-7 128 078 J-11 182 0132 B-10
21 D2 G-3 75 025 R-7 129 079 L-8 183 0133 A-10
22 D3 G-2 76 026 L-7 130 080 K-8 184 0134 D-9
23 D4 G-1 77 027 M-8 131 081 H-10 185 0135 C-9
24 D5 G-5 78 028 P-8 132 082 H-11 186 0136 B-9
25 D6 H-3 79 029 R-8 133 083 H-6 187 0137 A-9
26 D7 H-1 80 030 N-8 134 084 H-5 188 0138 E-9
27 DYO H-2 81 031 L-9 135 085 F-8 189 0139 D-8
28 CLO H-4 82 032 R-9 136 086 E-8 190 0140 B-8
29 SYNC J-5 83 033 P-9 137 087 H-12 191 0141 A-8
30 FR J-1 84 034 N-9 138 088 H-14 192 0142 C-8
31 CL J-2 85 035 M-9 139 089 H-15 193 0143 E-7
32 OSC2 J-3 86 036 R-10 140 090 H-13 194 0144 A-7
33 OSC1 J-4 87 037 P-10 141 091 G-11 195 0145 B-7
34 T2 K-1 88 038 N-10 142 092 G-15 196 0146 C-7
35 T1 K-2 89 039 M-10 143 093 G-14 197 0147 D-7
36 VSS K-3 90 040 R-11 144 094 G-13 198 0148 A-6
37 CAP1+ K-4 91 041 L-10 145 095 G-12 199 0149 B-6
38 CAP1− L-1 92 042 P-11 146 096 F-15 200 0150 C-6
39 CAP2+ K-5 93 043 N-11 147 097 F-14 201 0151 D-6
40 CAP2− L-2 94 044 R-12 148 098 F-13 202 0152 A-5
41 VOUT L-3 95 045 M-11 149 099 F-12 203 0153 E-6
42 V5 M-1 96 046 K-9 150 0100 E-15 204 0154 B-5
43 VR L-4 97 047 P-12 151 0101 F-11 205 0155 C-5
44 VDD J-6 98 048 R-13 152 0102 E-14 206 0156 A-4
45 V1 M-2 99 049 N-12 153 0103 E-13 207 0157 D-5
46 V2 N-1 100 050 L-11 154 0104 D-15 208 0158 F-7
47 V3 M-3 101 051 P-13 155 0105 E-12 209 0159 B-4
48 V4 L-5 102 052 R-14 156 0106 G-10 210 0160 A-3
49 V5 N-2 103 053 N-13 157 0107 D-14 211 0161 C-4
50 00 P-1 104 054 R-15 158 0108 C-15 212 0162 E-5
51 01 N-3 105 055 P-14 159 0109 D-13 213 0163 B-3
52 02 R-1 106 056 M-12 160 0110 F-10 214 0164 A-2
53 03 P-2 107 057 P-15 161 0111 C-14 215 0165 C-3
54 04 M-4 108 058 N-14 162 0112 B-15 216 COMI A-1

174-3.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 83
6.9 6.9 SED1560TQA OL Dimensions
6.9 SED1560TQA OL DIMENSIONS

100% Sn
110 +/– 15uM

[90(+10,–20uM)] 190uM 0.5 +/–0.1uM

CU CU 25 +/–1uM

300uM Adhesive

Polymide Film

Figure 6.8 SED1560TQA OL Dimensions

S-MOS assumes no responsibility or liability for (1) any errors or inaccuracies contained in the
information herein and (2) the use of the information or a portion thereof in any application,
including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The
information herein is subject to change without notice from S-MOS.
October 1996 © Copyright 1996 S-MOS Systems, Inc. Printed in U.S.A. 174-3.0

84 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 174-3.0