Machine Translated by Google

Chapter 1. General description

1.1 The process of processing information from a

computer: a. CPU -> h×nh b. Receive information
-> Process information -> Export information c. CPU ->
KEYS -> Mn h×nh d. Menu h×nh -> Printer -> a mÒm

1.2. The basic requirements of the computer:

a. Data storage, Movement, Support for employees, Access to children. b. Data
Transfer, Acceptance, Command Execution, Data Handling. c. Data Storage, Data
Processing, Data Transfer, Consent. d. Control, Save data, Full implementation, Internet
connection.

1.3. Members of the staff of the computer:

a. RAM, CPU, Ü ®Ütogether, Link bus b.
Children, Link Bus, ROM, Keypad c. Child's family,
Child's treatment, Man's name xnh's, Good's d.
Children, Children handle, They can enter and exit, Bus connection

1.4. The child handles the components (without the bus inside): a.
Whistle ®, Registers, Also I/O b. Driver ®, ALU, Registers
c. Registers, DAC, Whistle ®i, d. ALU, Registers, Also I/O.

1.5. The child's family includes: a. Cache,

Baby b. Baby, ROM c. §Üa Quang,
Baby in d. Baby inside, Baby outside

1.6. The PC I/O device does not include the following additional settings:
a. Cartridge, Speakers, Three
CD-ROMs b. Display, RAM,
Printer c. CPU, Computer,
Computer d. ROM, RAM,
Registers 1.7. In the computer, the bus types are connected as
follows: a. , , , , b. Keyboard, Data, Text c. Data, Specimen,
Table of Contents d. Data, Consent, Support

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1.8. The computer activities include: a.

Shutdown, Hold command, I/O b. Data
Handling, Interrupts, Process Execution c. Implement
process, interrupt, I/O d. Calculation of results, Data
storage, I/O

1.9. Children ®prevent the use of computers that do not have to: a.
Register not ®redirect instruction b. The instruction register
is about to execute c. The instruction register is about to
be executed d. Registers

1.10. The following types of interrupts are available in the computer:

a. Terminate, mundane, intermediate b. Interrupt,

terminating, INTR c. Shut off, shut down NMI, shut
down d. stalemate, stalemate, stalemate

1.11. In a computer, the NMI switch is: a.

Unselected interrupt ®îc b. Shutdown
does not select ®ac c. Stop and don't
choose ®î d. ®îc . selector switch

1.12. When the child is handling the process, if it is difficult (do not refuse) send a message, please:

a. When the task is done, the execution will stop b. I can't play
it, don't put it on c. The cycle stops immediately, then stops
working. d. The execution of the current command is done, the
output will stop, and then return to the continuous execution.

1.13. COMPUTER Von Newmann is a COMPUTER:

a. Only 1 child handled and executed prison orders b. Can
execute multiple commands at the same time (parallel) c. Follow the
routines in the baby d. OLD AND COFFEE

1.14. COMPUTER ENIAC is a COMPUTER:

a. The child's education is always b.
Calculation for the years 1970 c. Use a magnifying
glass and martial arts d. The world's most advanced
computer system

1.15. For the messages that are displayed, the following statements are wrong:

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a. MEMR is a small command (data) message b.

MEMW is a baby command understanding c. IOR is
also input data output d. IOW is an output and input
signal

1.16. Notice the following:

a. INTR is the same as select ®ac b.
INTR is a SUMMARY TERMINAL c.
INTR is also a non-selective signal d. INTR is out of
order

1.17. Which of the following statements is

incorrect: a. INTA stands for Understanding CPU åagree to accept
interrupts b. INTA is a signal that sends the child to the outside of the
processor c. INTA is an external signal from the CPU interrupt d. A
and B ®Òu ®ong

1.18. Which of the following is true: a.

HOLD is an external CPU output signal b. HOLD
DOESN'T RECEIVE SIGNIFICANT ®while Paying
c. HOLD REGULATIONS IF ANNOUNCEMENTS
d. HOLD is an external signal from the CPU but the bus

1.19. Which of the following is true: a.

HLDA is a signal that the CPU accepts busses b.
HLDA is a signal that the CPU does not accept the bus c.
HLDA is a signal of the CPU but bus d. HLDA is 1.20 meter
short. For this ®Õ, the ®· calculator must pass through: a. 5
thÕ hÖ b. 4 months c. 3 thÕ hÖ d. 2 months

1.21. In the payment stages of the computer, the following statements are made: a. You
can use transistors b. Can be used with three transistors c. You can use the ®see
®nable option d. Can be used with SSI and MSI micros

1.22. In the payment stages of the computer, any of the following statements are wrong:
a. Can be used with two transistors b. Can be used with three transistors c. You
can use the ®see ®nable option d. You can use the micrometer

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1.23. According to Moore's law, the number of transistors will increase ®«i after
mçi: a. 22 months c. 18 months b. 20 months
d. 16 months

1.24. SIGNALS IF MEMR OUTSIDES: a. Small

command/data b. Short instruction/data output
c. Employee command d. Write the command
to TBNV

1.25. SIGNALS IF MEMW SHOULD BE UNDERSTANDED:

a. Small command/data b. Short instruction/data
output c. Write out short d. Record the data
briefly

1.26. SIGNIFICANT SIGNS IF AN IOR ANNOUNCED

IOR SIGNIFICANTS: a. Small command/
data b. Short instruction/data output c. Data
collection of employees d. Write data to
TBNV 1.27. Understanding ®Understanding
IOW Understanding: a. Employee command/data b.
Write/data to TBNV c. Data collection of
employees d. Write data to TBNV

1.28. SIGNALS IF INTR IS ANNOUNCED SIGNALS:

a. An external user calls the CPU to turn off b.
Plug the CPU out to interrupt c. The child has
called the CPU to turn off d. Call the CPU to send
the baby Chinh to stop

1.29. SIGNALS IF INTA IS ANNOUNCED SIGNALS:

a. The above CPU does not accept interrupts
b. CPU bounces interrupt c. An external caller
asks the CPU to turn off d. Shut off

1.30. SIGNIFICANT SIGNS IF HOLD HOLDING

SIGNALS: a. CPU error interrupts b. CPU
sends out using bus c. Calling an external
CPU, please use the bus d. Calling an external CPU
to turn on the bus without using the bus

1.31. SIGNIFICATIONS When Receiving HLDA SIGNIFICATIONS:

a. The above CPU does not 'not accept interrupts'

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b. CPU bounces interrupt c. An external

caller asks the CPU to turn off d. Upper CPU
®Agree to busses

1.32. For the Understanding when the MEMR is taken, the following ®ell error:
a. Signals emitted by the CPU b.
KNOW IF YOU ENJOY YOUR CHILD c. GET
INFORMATION ®when Recording d. Understanding
Understanding Acc

1.33. For Understanding Signals when Opping MEMW, say the following ®Error: a.
SIGNATURE ® outputted by the CPU b. Signals sent by an outside party to the
CPU c. Does not require the same input/output signal d. KNOWLEDGE ®when
Recording

1.34. If the message is displayed when I VOLUME, the following error will occur: a.
Understanding Signals when I/O b. ERROR ®Understanding on emitted
by the CPU c. ANNOUNCEMENT Understanding ®Acceptance d.
Understanding Using CPU Access

1.35. For ®Understanding IOW, the following statements ®e error: a. LEARNING

OUTSIDE INTERNAL INTERNATIONAL IN/OUT b. ERROR ®Understanding
on emitted by the CPU c. Understanding message when îsend is also in/
out d. LEARNING LEARNING WHEN LOOKING DATA

1.36. If the message is displayed when INTR is pressed, say the following error: a.
Understanding Signals When An External Input Calls CPU b. ERROR
®Understanding on emitted by the CPU c. DISCUSSION LEARNING d. ®î

1.37. If the message is displayed when INTA is pressed, the following error occurs:
a. Short-term acceptance notice b.
ERROR ®Understanding on emitted by the CPU c.
Understanding Signals When Recording Also I/O d.
LEARNING LEARNING WHEN ANSWER HANDLING

1.38. For the error message when receiving NMI, say the following error: a. External
Signals Signaling CPU b. ®Effective Signal ®îc. Unsolicited
ANNOUNCEMENT îAccept d. The CPU does not «cannot input this signal»

1.39. If the message is displayed when HOLD, the following error occurs:
a. Signals emitted by the CPU

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b. CPUUnderstanding Signals
c. I would like to do the bus
d. "No need for input/output signal"

1.40. For Understanding when Receiving HLDA, the following error ®©e error:
a. CPU PERFORMANCE LEARNING
b. Understanding åagreeing to the bus
c. INTERNAL TERMS SIGNED CPU to stop
d. No need to understand to disconnect from outside

1.41. According to the method of internet transmission, the following types of computers are available:
a. Children with Tablets, PCs, PCs, Supercomputers, PCs
b. Laptops, PCs, PCs, PCs, Microcomputers
c. Laptops, Mini PCs, Soldier PCs, Supercomputers, PCs
d. Microcomputers, computers, mini computers, minicomputers, supercomputers

1.42. According to the method displayed, the following types of computers are available:
a. PC
b. ® Computers, PCs, PCs
c. Computers, mini calculators, mini calculators
d. Mini PC, Mini PC, Super PC

Chapter 2. Computer data table

2.1. For example, it is an 8-bit integer, keeping the value 261 times:
a. 1001 0001 b. 1010
1011
c. 1000 0111 d. No «ng
Billionaire ®îc

2.2. For example, it is an 8-bit integer, keeping the value 132 times:
a. 1001 0001 b. 1000
0100
c. 1000 0111 d. No «ng
Billionaire ®îc

2.3. For example, it is 8 bits, keeping the value 129 times:

a. 1001 0001 b. 1010
1011
c. 1000 0111 d. No «ng
Billionaire ®îc

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2.4. For example, it is an 8-bit integer, keeping the value 124 times:
a. 0111 1100 b. 0101
1011
c. 0100 0111 d. No «ng
BiOu Dion ®îc

2.5. DISPLAY NUMBER DIGITAL NUMBERS, n bits in a computer:

a. 0 -> 2.n b. 0 -> 2.n -
first

c. 0 -> 2n - 1 d. 0 -> 2n

2.6. MONITORING will be all integers, n bits in a computer:

a. - 2(n - 1) -> 2 (n - 1) c. b. - 2.n - 1 -> 2.n +1
- 2n - 1 - 1-> 2n - 1 - 1 d. - 2n - 1 -1 -> 2n - first

2.7. WILL ALSO ®Collect the full implementation:

Start

C:=0; A:=0; Baby ®Õm:=n

I won't give up
Q can't remember

ball
Q0 = 1?
Wrong

C,A:=A+M

Shift right C, A, Q
Dec(Baby ®Õm)

Wrong
ball
Baby ®Õm = 0? End

a. PDP shares Nguyen's name

b. No
c. Licensed
d. PhDp shares the original source

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2.8. WILL ALSO ®Collect the full implementation:

Start

A:=0; Q-1:=0; Baby ®Õm:=n

I won't give up
Q can't remember

= 10 = 01
Q0 , Q-1

= 11
A := A - CODE A := A + CODE
= 00

Shift right A, Q, Q-1

Dec(Baby ®Õm)
Note: An-1 ®required

Wrong ball
Baby ®Õm = 0? End

a. No
b. Licensed
c. PDP shares Nguyen's name
d. PhDp shares his raw materials

2.9. For example, 8 bits, using the "Low doodle" method, keeping the value
- 60 times:
a. 0000 1101 b. 0000 1010
c. 1011 1100 d.
1100 1101

2.10. For example, 8 bits, using the "Low doodle" method, keeping the
value - 256 times:
a. 1100 1110 b.
1010 1110
c. 1100 1100 d.
No «Non-Persons'

2.11. For example, 8 bits, using the “M 2” method, keeping the value 101
times:
a. 0110 0101 b.
0000 1100
c. 0000 1110 d.
0100 1010

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2.12. For example, 8 bits, using the "M 2" method, keeping the value - 29 times:

a. 1000 0000 b.
1110 0011
c. 1111 0000 d.
1000 1111

2.13. The expression "1110 0010" ®is for the original, 8-bit, using the "Short-Earlier" method,
keeping the enabled:
a. 136
b. 30
c. - 30
d. - 136

2.14. The expression “1100 1000” ®is for the integer, 8 bit, using the “M · b 2” method,
keeping the output:
a. Don't die c. 56 b. - 56

d. 200

2.15. By clicking ®©ym« for the actual performance measure:

AQ Q-1 US
0000 0011 0 1001 SUPPORT on initialization
0111 0011 0 1001 Aÿ A - US
0011 1001 1 1001 SHR A, Q, Q-1
0001 1100 1 1001 SHR A, Q, Q-1
1010 1100 1 1001 Aÿ A + M
1101 0110 0 1001 SHR A, Q, Q-1
1110 1011 1 1001 SHR A, Q, Q-1

a. 3 ÿ 9 = 27 c. (-7) 3 = -21
b. 15 9 = 135 d. 5 27 = 135

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2.16. Irradiation “0000 0000 0010 0101” (use m· ï 2, ), for quick help:

a. -37 b. 37
c. - 21 d. 21

2.17. By clicking ®©ym« for the implementation of the calculation method:

AQ M = 0011
1111 0101 Initiate babysitting (differentiated and split)
1110 1010 Shift beyond 1 bit A, Q
0001 M is different from A ÿ A := A + M
1110 1010 A is different after Q0 = 0 and A
1101 0100 Shift beyond 1 bit A, Q
0000 M is different from A ÿ A := A + M
1101 0100 A is different after Q0 = 0 and A
1010 1000 Shift 1 bit A, Q
1101 M is different from A ÿ A := A + M
1101 1001 A is the same after Q0 = 1
1011 0010 Shift beyond 1 bit A, Q
1110 M is different from A ÿ A := A + M
1110 0011 A is the same after ÿ Q0=1.

a. 245 : 3 = 81, d 2 b. 59 : 15 = 3, d 14
c. 11: 3 = 3, d 2 2.18. d. (-11) : 3 = (-3), d (-2)
WILL ALSO ®Collect the full implementation:
Baby ®Õm := n
Start M to divide (n bits)
A,Q will not be divisible (2n bits)

Shift A,Q ®i 1 bit

B := A

ball Wrong

M, A are the same?

A := A - CODE A := A + CODE

ball A and B are the same Wrong

or A = Q = 0?

Q0 = 1 Q0 = 0; A := OVER

Dec(Baby ®Õm)

Wrong ball End

Baby ®Õm = 0?

a. No

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b. Licensed
c. PDP shares Nguyen's name
d. PhDp shares his raw materials

2.19. By clicking ®©ym« for the implementation of the calculation method:

CA 0 0000 Q USA

0 1100 0 1011 1100 CREATE HELP

0110 1 0010
0 1011 1100 C, Aÿ A+M
1001 0 0100 0101 1100 SHR C, A, Q
1 0000 1000
0 0101 1100 C, Aÿ A+M
0010 1100 SHR C, A, Q
1001 1100 SHR C, A, Q
1001 1100 C, Aÿ A+M
0100 1100 SHR C, A, Q

a. 4 ÿ 19 = 76 b. c. -4 31 = -124
11 12 = 132 d. 6 22 = 132

2.20. For example, 8-bit numbers, no numbers. Please let me know the results when doing the same:
0100 0111 + 0101 1111:
a. 146 b.
166
c. 176 d.
156
2.21. For the wrong results, the same method on the computer gives the wrong result when:
a. Same two will be used, for the result ©m
b. Also two sem ©m, for the end result
c. You've come up with the highest bit
d. OLD A & B

2.22. For all of the above, the same method on the computer gives false results when:
a. Same two will be used, for the result ©m
b. Also two sem ©m, for the end result
c. You've come up with the highest bit
d. OLD A & B

2.23. For example, if any of the following statements are incorrect:

a. The two will be the same, the same is the same as the number "n ®hot"

b. The two will be different from each other, the total amount is «n ®hot .

c. The two numbers are the same, if the number is the same, the number is the same.
d. Also two numbers will be the same, if the number is different then it is the same.

2.24. If not, say the following:

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a. When the execution is done, the sum «n ®hot

b. When the same two will be the same number, let the number be different.
c. When you find the highest bit, the increment is not wrong
d. When it does not produce the highest bit, increase ®g

2.25. For example, zero, 8 bits, xPyptic: 240 + 27. The following statements ®©y ®b:

a. Free 267
b. Free 11
c. Do not give results, v× above sè
d. A and B ®u is wrong

2.26. For example, it is 8 bits, and is also valid: (-39) + (-42). Notice the following:

a. Do not give results, v× above sè

b. Do not give results, v× do not specify the highest bit
c. Bonus -81
d. Free gift 81

2.27. For example, 8 bits, xDepend: (-73) + (-86). Notice the following:

a. Do not give results, v× above sè

b. Do not give results, v× do not specify the highest bit
c. Free 97
d. Bonus -159

2.28. For example, 8 bits, xPyptic: 91 + 63. The following statements are displayed:

a. Do not give results, v× above sè

b. The result is wrong, v× can only get the highest bit
c. Free 154
d. Total -102

2.29. Meters will be X-beku, and the total number of ions used is as follows:
a. X = (-1).S . M . RE
b. X = (-1)S . M . RE
c. X = (-1)S . USA . RE
d. X = (-1)S . . RE
USA

2.30. Given two elements X1 and X2, the values of the total number of ions used for the fan are given.
The following statements are for reference (X1 . X2):
. X2 E2
(M1.M2) . = (-1)S1. S2 RE1 . a. X1 .
b. X1 . X2 = (-1)S1ÿ S2 RE1 E2
. (M1.M2)
. .
c. X1 . X2 = (-1)S1+ S2 RE1
. (M1.M2)
+ E2 .

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d. X1 . X2 = (-1)S1ÿ S2 RE1 + E2
. (M1.M2) .

2.31. . Given two elements X1 and X2, the values of the total number of ions used for the fan are given.
The following statements are for division (X1 / X2):
X2 = (-1)S1/
a. X1 . .(M1/M2) . S2 RE1 - E2
b. X1 . X2 = (-1)S1ÿ S2 RE1 - E2
. (M1/M2) .
c. X1 . X2 = (-1)S1ÿ S2 RE1 + E2
. (M1/M2) .
d. X1 . X2 = (-1)S1/ S2 RE1 + E2
. (M1/M2) .

2.32. For the IEEE 754/85 standard and the specifics, the following statements are wrong:

a. Name 3 using the symbology

b. Uses of 2 . dielectrics
c. Uses 10 . dielectrics
d. 64 bit usage meter ®Operator

2.33. For an example of IEEE 754/85 with specific specifications, the following are used:
a. Single, Double, Real
b. Single, Double-Extended, Comp
c. Single, Double-Extended, Double
d. Double-Extended, Comp, Double
2.34. In the IEEE 754/85 standard, the ®¬n (single) use stands for:
a. 16 bits b.
128 bits
c. 32 bits d. sixty four

bit

2.35. In the IEEE 754/85 standard, the use of kDP (double) stands for:
a. 64 bit b. 80
bit
c. 32 bit d.
128 bit

2.36. In the IEEE 754/85 standard, the use of double-extended kP stands for:
a. 128 bits b. 80
bit
c. 32 bits d. sixty four

bit

2.37. Using ®¬n (in the IEEE 754/85) standard, the bits for the above terminals (S + E + M) are:

a. 1 + 9 + 22 b. 1 + 8 +
23

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c. 1 + 10 + 21 d. 1 + 11 +
20

2.38. For the kDP example (in the IEEE 754/85 standard), the bits for the above terminals (S + E + M)
are:
a. 1 + 10 + 52 b. 1 + 11 +
sixty four

c. 1 + 11 + 52 d. 1 + 15 +
48

2.39. For example, using the high frequency signal (in the IEEE 754/85 standard), the bits for the
above terminals (S + E + M) are:
a. 1 + 15 + 64 b. 1 + 17 +
62
c. 1 + 10 + 64 d. 1 + 14 +
65

2.40. Using the IEEE 754/85 terminal, the number is 73,625:

a. 42 39 40 00 H c. b. 42 93 40 00
24 93 40 00 d. 42 39 04 00

2.41. Using the IEEE 754/85 voltmeter, the number is - 53,125 volts:
a. 2C E0 A0 00 H c. b. C2 00 A0 00 H
C2 54 80 00H 2.42. d. C2 00 80 00 H
Using the IEEE 754/85 voltmeter, the number is 101.25:
a. 42 CA 80 00 H b. 42 CA 00 00 HOUSE
c. 24 AC 00 00 H d. 24 00 80 00

2.43. Using the IEEE 754/85 voltmeter, the number is - 119.5 times:
a. 2C 00 00 00 H b. 2C EF 00 00 H
c. C2 E0 00 00 H d. C2 EF 00 00 H
2.44. Give the following IEEE 754/85 reference: C2 82 80 00 H. Support for the best possible solution:

a. - 65.25 b. - 56.25
c. - 65.52 d. - 56.52

2.45. Give the following IEEE 754/85 reference: C2 BF 00 00 H.

a.- 95.25 b. - 95.5

c. - 59.5 d. - 59.25

2.46. Please refer to IEEE 754/85 as the following: 42 15 00 00 H. Help for maximum support:

a. 37.52 b. 73.25
c. 37.25 d. 73.52

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2.47. Please refer to IEEE 754/85 as the following: 42 22 80 00 H. Help for maximum support:

a. - 40.25 b. 40.25
c. - 40.625 d. 40.625

2.48. If m· Unicode ®O m· or letters, say any of the following ®©y errors:

a. LOTS m· 16 bits
b. Baby Feast
c. Only m· or ®î 256 characters
d. Vietnamese language support

2.49. If m· ASCII ®O m· or prison, say any of the following ®©y errors:

a. Designed by ANSI
b. LOTS m· 8 bits
c. Not yet signed when the message was received
d. Do not support the prisoner's signature when picking up the printer

2.50. For ASCII, the following statements ®© are incorrect:

a. Fixes the prison's signatures when receiving the h×nh
b. M· have the characters “&”, “%”, “@”, “#” in the m· më réng part
c. M · 30 H -> 39 H is a number of orders
d. I have not signed the prison term

2.51. According to IEEE 754/85, the single (single) format is:

a. X = (-1).S . 1,M . b. RE
X = (-1)S . 1,M . R.(E - 127)
c. X = (-1)S . 1,M . RE - 127
d. X = (-1)S . 1,M. ER - 127

2.52. According to the IEEE 754/85 standard, the number of double digits is:
a. X = (-1).S . 1,M . b. RE
X = (-1)S . 1,M . R.(E - 1023)
c. X = (-1)S . 1,M. ER - 1023
d. X = (-1)S . 1,M . RE - 1023

2.53. According to the IEEE 754/85 standard, the double extended parameter X is:

a. X = (-1)S . 1,M . RE - 16383

b. X = (-1).S . 1,M . c. RE
X = (-1)S . 1,M . R.(E - 16383)
d. X = (-1)S . 1,M. ER - 16383

2.54. Using the IEEE 754/85 terminal, the number is 31/64:

a. E3 F8 00 00 H b. 3E F8 00 00 H

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c. 3E 8F 00 00 H d. E3 8F 00 00 H

2.55. Using the IEEE 754/85 terminal, the number is - 79/32:

a. C0 1E 00 00 H b. 0C 1E 00 00 H
c. C0 E1 00 00 H d. 0C E1 00 00 H

2.56. Give the score 81.25. KEEP AN ANNOUNCEMENT :

a. 100101.10 b.
1010001.01
c. 100011,101 d.
100010.011

2.57. For item 99,3125. KEEP AN ANNOUNCEMENT :

a. 111011,1010 b.
111011,0011
c. 111010.0101 d. 1100011.0101

2.58. For the number 51/32. KEEP AN ANNOUNCEMENT :

a. 1.01011 b. first,
01110
c. 1.10011 d. 1.00111

2.59. For the number 33/128. KEEP AN ANNOUNCEMENT :

a. 0.0100001 b.
0.110101
c. 0.1001100 d.
0.0100011

Chapter 3. Baby treats

3.1. Notice of error ®©y error:

a. Baby handles computer operations
b. The baby handles the activities according to the ready-made processes in the baby.
c. The child handles the request with two components
d. The child handles the request with three components

3.2. To execute 1 command, the child must go through:

a. 8 c«ng ®o¹n c. b. 7 c«ng ®o¹n
6 c«ng ®o¹n d. 5 c«ng ®o¹n

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3.3. In order to solve the problem, the child should be able to

handle the problem: a. Hold command -> label data -> handle data -> write data -> label

command b. Command -> hold command -> receive data -> handle data -> write
material

c. Command -> receive data -> hold command -> data handling -> write
material

d. Label data -> handle data -> give command -> hold command -> write
material

3.4. For example, when receiving the instruction from the CPU, the
execution mode is: a. Baby ®prevention -> Baby -> instruction
register b. Baby -> Baby ®Center -> instruction register c.
Baby -> command register -> baby ®indicator d. Baby
®prevention -> command register -> baby

3.5. For the CPU instruction time delay, the displayed error:
a. Command register -> hold down -> cue ®while ®r -> signal ®while ®while b.
Command register -> ®while On -> Signal ®on -> hold c. Whistle ®pump ->
command register -> hold -> Signal ®while d. Command register -> knob when
On -> hold -> Signal ®on

3.6. For example, when you receive data from the CPU, the following
are displayed: a. Index -> register file -> small number b. Index
-> child -> register set c. Register file -> ®redirect -> small d.
Short -> register file -> ®Þa only

3.7. For processing data from the CPU, the execution mode is: a. Full
execution -> ALU -> data register b. Full execution -> data
register -> ALU c. ALU -> full implementation -> data register d.
ALU -> data register -> full implementation 3.8. As for CPU data
logging , the execution mode is: a. Index -> register file -> small
number b. Index -> child -> register set c. Register file -> ®redirect ->
small d. Register file -> short -> ®Þa only

3.9. The child handles the

receipt of: a. Children studying abroad

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b. Baby c.
External settings d. CPU

3.10. The child processes the data in:

a. Children or children outside b. Baby
c. External settings d. CPU

3.11. If there are many buttons on the keyboard while playing (in the CPU), any of the following
commands will give an error: a. When receiving the next instruction according to the child's name,
®a enters instruction register b. Add the contents of the PC ®O to the next command c.
CONVERT TRANSFER the register to the child d. Emissions Signals when a command is
executed

3.12. If the button is pressed (in the CPU), any of the following commands are incorrect: a.
When receiving internal signals from the outside, the child handles b. §while the ALU
registers c. §Using the child and the input module d. ONLY when LOADING the
registers and ALU

3.13. For the ALU (in CPU), the following commands should be fired:
a. Full implementation of the training b.
Implement all logic operations c. A and b d.
No "bit rotational display mode"

3.14. For the registers (in the CPU), which of the following statements ®© is false: a. No
further information is available b. Pre-school children's money c. N»m in baby
reason d. The variable setting replaces the contents of each 3.15 register. For the
®redirect registers (in the CPU), the following output ®represents: a. Name 2
types b. The most controversial of 3 types c. Controversy of more than 4 types d. Only 1
type

3.16. For the ®address registers (in the CPU), any of the following statements ®© is incorrect:

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a. Children ®retrieve management ®restrictive command

b. The data area is managed by the data sub-register c. The
instruction loop does not have a management register d. The short-
haired child is not ®Þa only xp

3.17. For the short stack (stack), which of the following statements is
wrong: a. Childish Oblivion Teasing FIFO b. LIFO childish
squabbles c. The short head is nng n n n n ng d. When you
learn more about nxp, the n o n n n op decreases.

3.18. Which of the following statements

is incorrect: a. The time register is also called the cb
register. The execution register does not contain the
handlers c. Both types d. Only the type of meter

3.19. When playing in the CPU, the following button will fire:
a. Continue reading CPU nn b. Do not
continue to receive the employee's ID c.
Hold the ®transfer instruction to the ®input d. Hold the command
®convert to the instruction register ®Õn

3.20. To check the signals when you are inside the CPU, the following button will sound: a.
§ §iOw Moves the register data to the ALU c. §When you move the ALU data to a small
child d. Option Move CPU data to ALU

3.21. To check the signals when you are inside the CPU, any of the following statements
are wrong: a. §while Move CPU data to register b. Transfers the register data to the
ALU c. §while Move ALU data to register d. When the ALU button is displayed,

3.22. To detect signals when outputting the CPU to the system bus, say the following: a.
®Using ®data from the ALU b. Swallowing/small recording c. Move the ALU data into the
register

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d. §Iu when recorded in alu

3.23. To check the signals when the CPU outputs the system bus, the following statements are wrong: a. Â Â Â
                                                key is
played on/off button b. Swallowing/small recording c. §www writes data to registers d. Handling
messages from outsiders

3.24. To check the signals when you turn on the system bus to the CPU, say the following: a.
Signals when short recording b. Understanding when receiving a small amount c. Please stop
understanding d. ANNOUNCEMENT

3.25. To check the signals when you turn on the CPU system bus, say the following error: a.
PLEASE understand the bus b. No need to understand when you receive a small amount c.
Please stop understanding d. Agreement to the bus

3.26. For the ALU (in CPU), which of the following statements ®© is incorrect: a.
Bit shift execution b. Implementation of the method of comparing two
volumes c. Implement the second step d. The implementation of the law
also supports the

3.27. For the registers (in the CPU), the following statements ®©e ®near: a. Types of
registers that are not pre-installed b. Each of the program-installed registers c.
Martial arts treatment is completed d. No contests for all employees

3.28. For the time register (in the CPU), the following statements ®recoil: a. Not fully approved
b. Fully approved only c. Cure when d. There are no complaints about 3.29. In the case of carry
(CF), the following shall occur:

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a. Implemented when the whole code has reached the highest bit
concept b. Implemented when PHP cannot detect the highest bit c. Not
set when the algorithm has the highest bit output d. ©cementation of the
above emotion of love

3.30. For the carry case (CF), which of the following statements is incorrect:
a. Implemented when the whole code has reached the highest bit
concept b. Not set when the code does not detect the highest bit c. d
©cementation of the above emotion of love

3.31. For overflow (OF), do the following: a. Implemented when the

same two will be different for the result ©m b. Implemented when
the two together will give different results c. Implemented when the two
will be the same for the same result d. ©receive the above report ®ei vii
will not be

3.32. For overflow (OF), any of the following statements are incorrect:
a. Do not set up when the two other things are different for the same
result. ©m b. Implemented when the two together will give different results
c. Implemented when the two will be the same for the same result d.
©cementation of the above emotion of love

Chapter 4. Explosion

4.1. CATEGORY:
a. 9 mode ®a only
b. 8 modes ®repair
c. 7 mode ®a only
d. 6 modes ®Þa cha

4.2. The ®repair mode is the following non-confrontational

mode: a. Full range of meters and parts of orders b.
The whole store is right in the top ®Þ only c. ®Identity
d. The whole company has only received the full
amount of raw materials

4.3. For assembly command: ADD BX, 10. Full resource: a.

Mode ® Direct Mode b. Mode ®receive time

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c. No command loss d.
Mode ®Resolve th×

4.4. For assembly command: SUB 100, CX. Full range of drugs: a.
Mode ® Direct Mode b. Don't lose the command c. Mode ®repair
only d. Mode ®Resolve th×

4.5. Mode ® is directly connected to the full-line mode:

a. Short meter ®Þ îindicated in order b. Shortage of
children ®Þ only ë of other children c. Meter register d.
Short meter ®Þindication meter in register meter

4.6. For assembly command: MOV DX, [20]. Full range of drugs:
a. Mode ® Direct Mode b.
Don't lose the command c.
Mode ®repair only d. Mode
®Resolve th×

4.7. For assembly command: SUB BX, [30]. Full range of drugs: a. Don't
lose the command b. Mode ®Continuing time b. Mode ®Resolve
th× d. Mode ® Direct mode only 4.8. Mode ® Change the time
to continue with the full-time mode:

a. Short meter ®Þ îindicated in order b. The smallest

child ®reigns in the other small child c. Meters of
®Þindicated registers in short meters d. Short meter
®Þindication meter in register meter

4.9. Mode ®modifies the registers as full-line mode:

a. The content of the short text is indicated in command b. The
content of the child's short text is ®selected in the other short c.
Contents of the register d. The content of the ®Þindicator m in the
register meter

4.10. For assembly commands: ADD AX, CX. Mode ®remove the entire source:
a. th × b.
Directly c.
Continue through register d.
Registers

4.11. For assembly command: SUB CX, [90]. Which of the following statements is incorrect:

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a. Full line ®Id mode ®modify registers b. Full

mode ®resources are only direct c. All natural
resources are short-lived d. The full line of time
mode resources goes through the register

4.12. In case of ® mode, which directs the time through the register, the following
statements ® are false: a. Entire array of register meters can be specified in sub-
meters b. The entire array of small ®indicated meters in register meters c. The
entire series of content is small d. The join register is the left child register

4.13. For assembly command: MOV DX, [BP]. Mode ® covers only the entire source line:
a. Register b. Continuity c. Continue through register d. first

4.14. In the ®Transfer only mode, select the following error: a. Matching error:
register-forward mode and thx-b mode. You can join the ®redirect
mode only. List of full arrays: register contents + list d. Used to
participate in ® mode, directing through registers

4.15. For assembly command: SUB AX, [CX] + 50. Mode ® edits the entire source line:

a. TRANSLATION
b. Don't die c.
Register d.
Continue through registers

4.16. Mode ®Prepares the prompts for the

mode: a. Entire Group ®Evaluated
b. The entire number of young children ®inh
nxp c. DISCLAIMER d. A and B ®Òu ®ong

4.17. For assembly command: POP BX. Which of the following is true: a.
§©y is mode ®Þonly registers b. §©y ®Þ mode directs the time
through the c register. §©yµmode ®Þshort xÕp d. A and B ®Òu
®ong

4.18. Mode ®reduces thx mode: a. The

entire system is immediately available in command
b. The entire series is in short supply

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c. The full line of energy in the meter register d. B and C

®u ®ong

4.19. In the case of ®direct mode only, the following statements are incorrect:
a. The full range of short-form content is indicated in command b. The full range of
content is short c. t × m ® is a full line, must be specified ® short d. t × m ®ovariable,
must specify ®redirect register

4.20. In case of ®redirect mode, say the following ®Error: a. The full range of
content is short b. Full list of contents of register c. A lot of time d. Téc
®removal of cymbal

4.21. In case of ®only register mode, say any of the following ®© error:
a. The full array of small contents are specified in register b. Full list of contents
of register c. Do not refer to children d. B and C ®u ®ong

4.22. In ® mode, which directs the time through the register, the following statements
®representation: a. Entire array of register meters can be specified in sub-meters b. The
entire array of small ®indicated meters in register meters c. Entire store does not have to
be small in size d. Small call join register

4.23. In the ®Transfer only mode, perform the following operations ®representation:
a. Matching error: register-forward mode and direct mode b. Everyone who
participates in cña mode ®Þ is only thx c. Unnecessary full array instruction:
register contents + list d. Can join cña mode ®Þregister only

4.24. In case of ®preparation mode, do any of the following ®Collect errors:

a. Entire Group ®Evaluated b. The
entire number of young children ®inh nxp c.
DISCLAIMER d. A and B ®Òu ®ong

4.25. For the machine command, say which of the following is

wrong: a. There are 2 components: m· orders for total
goods b. M · command for the operation to be performed
c. Full list of operations to be performed d. Full list of data
not yet available

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4.26. In the m· machine, the following statements are made:

a. Dispute m· command b. No
'unloaded' orders for the whole line c. Entire
brand unique d. There is controversy all over the
world

4.27. For the m· machine command, the total output will be:
a. 1, 2, 3 all rows b.
0, 1, 2, full line c. 2, 3,
4 full line d. A and B
®Òu ®ong

4.28. For m· machine orders, the whole company does not

answer: a. Meters b. Contents of the register c. Brief
content d. Contents of the ®Þindication registers in
short meters

4.29. The following picture will be used when the mode is active:

Cold

M· command , Baby

The whole company

a. Directly b.
th × c.
Continue through register d.
Don't give up

4.30. The following picture will be used when the mode is active:

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M· command Command _
Baby

e only t/h

The whole company

a. Don't die b.
Continuity c.
Register d. first

4.31. The following picture will be used when the mode is active:

Cold
M· command Register name
Register set

The whole company

a. Continuity
b. Register c.
Don't lose money
d. Continue through registers

4.32. The following picture will be used when the mode is active:

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Cold
M· command Register name
Baby
Register set

e only t/h The whole company

a. th × b.
TRANSLATION
c. Continue through register
d. Don't give up

4.33. The following picture will be used when the mode is active:

Cold
M· CHEAP Register command Address A
Baby
+
Register set

just short

The whole company

a. Don't die b.
Directly c. Continue
through register d.
TRANSLATION

4.34. The following picture will be used when the mode is active:

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M· command Command _
Register set

e only t/h

The whole company

a. Don't die b.
Concatenate through register
c. Directly d. Simplified

4.35. The following picture will be used when the mode is active:

Cold
M· command Register name
Register set

Baby

e only t/h The whole company

a. Continuity through small

children b. Don't die c.
Continue through register d.
first

4.36. The following picture will be used when the mode is active:

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Cold
M· CHEAP Register command Address A
Register set
+
Baby

just short

The whole company

a. TRANSLATION
b. Concatenate through register
c. Directly d. Don't give up

4.37. For the assembly command: ADD CX, 20. Say the following: a. All resources
are in mode ®representative b. All resources are in direct mode ® only. Full
line ®Ident mode ® directs direct time through register d. Full line ®Import
not in mode ®Register-only

4.38. For the assembly command: SUB CX, 70. Which of the following statements
is incorrect: a. All resources are in mode ®representative b. All resources
are not in direct mode ® only c. Full line ®Id not in mode ®Only register
d. Full ®Indication not in ®Continued only mode

4.39. For assembly command: ADD DX, [40]. Which of the following is true: a. All
resources are in mode ®representative b. All resources are not in direct mode
® only c. Full line ®Id not in mode ®Only register d. Full line ®Identical mode
®register only

4.40. For assembly command: MOV BX, [80]. Which of the following statements is
incorrect: a. The full set of mode ® resources contains only registers b. All
resources are in direct mode ® only. Full ®Translation not in ®Translation
only mode d. Full ®Indication not in ®direct mode only

4.41. For assembly command: SUB AX, [BX]. Which of the following statements is
incorrect: a. The full set of mode ® resources contains only registers b. The
full line of mode ® resources is directed through the registers.

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c. Full ®Translation not in ®Translation only mode d. Full

®Indication not in ®Continued only mode

4.42. For assembly command: ADD AX, [BP]. Which of the following is true: a. The
full set of mode ® resources contains only registers b. The full array of mode
® resources is directed through the c register. Full line ®Id not in mode
®Only register d. Full line ®Ident mode ®indicates direct time through
registers

4.43. For assembly command: MOV AX, [BX]+50. Which of the following statements is
incorrect: a. All resources are in ®modified mode for conversion b. Full
®Translation not in ®Modify mode ®Transfer c. All resources are in mode
®represented only x d. Full ®Indication not in ®Continued only mode

4.44. For assembly command: ADD DX, [SI]+30. Which of the following is true: a. All
resources are in ®modified mode for conversion b. Full product ®Indicates
®direct mode only. All resources are in mode ®represented only x d. Full range
®Indicated mode ®redirected time only

4.45. For assembly command: POP DX. Notice the following:

a. Not all resources b. Full product
®Indicates ®direct mode only. ®Ing ®Essential ®
Group d. Entire source ®reviewed

4.46. For assembly command: PUSH AX. Which of the following statements is incorrect:
a. Not all resources b. Full ®Ing
®Understanding c. Entire source of ®
mode ® registers only d. Full line ®Important mode ®only
stack

4.47. The names of the modes are listed below:

a. thx, sequence, register, short, short, short, short, false b. Sequential, register-forward,
direct, shift, short, fruit, register c. thx, sequence, register, shift, short, direct, time

go through registers
d. th× key, forward through pointer, register, short, shift, switch, short

4.48. Issue the LOAD command. This command:

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a. Academic performance
b. Transfer command Move data
c. Move command ®i ® when Picking
d. Input/output command

4.49. Issue the INTERRUPT command. This order is:

a. Academic performance b. Transfer command
Move data c. Move command ®i ® when
Picking d. Input/output command

4.50. Order ABSOLUTE. This order is: a. Academic

performance b. I/O command c. Give the
command ®i when you receive it d. Logical
command

4.51. Run the ROTATE command. This order is:

a. Switch ®ion when receiving b. Enter the
®i command when you receive it c.
Relationship around d. Logical instructions
4.52. Order JUMP. This order is: a. Switch
®ion when receiving b. Regards c. I/O command
d. Order

Chapter 5. THEY ARE KIND

5.1. For children with ROMs, say the following error: a.

Name 5 types of ROM b. Child error in the sea c.
System software (BIOS) failure d. Claims for
minor violations

5.2. For children with ROMs, please do the following: a.

How to use PROM b. PROM error ROM has deleted
and written too much c. EPROM error ROM has been
erased and written to a large amount d. How to use
®express ®Erase EPROM

5.3. If you have little RAM, say the following error: a.

The child's fault is not "disabled" b. Keeping
track of more information

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c. Both types of RAM d.

Children's Festivities ®äc/remarks

5.4. For a child with RAM, the following should be done: a.

The child's fault is not "disabled" b. RAM
abbreviations: Read Access Memory c. SRAM ® is
only created in the motor ® d. Error keeping the
computer's information in processing

5.5. For children with ROMs, please do the following: a. Only

short circuit b. Battery only transistor c. Diode battery
only d. B&B

5.6. If you have little RAM, say the following error: a.

DRAM ® is only circuit-generated b. DRAM
®indicated in the auto ®c. SRAM ® is only circuit
breaker d. SRAM is no longer required

5.7. For a 64K x 4-bit SRAM chip, perform the following operations: a. According to
®Þindication: A0 -> A15 b. Adjustable segment : D0 -> D15 s of data slant: A0
-> A3 d. Size of data: D1 -> D8 5.8. For a 16K x 8 bit SRAM chip, the following
c. statements are wrong: a. Chapter 14 ®eng ®Þa only b. Table 8 ®data
specific c. According to ®Þindication: A0 -> A13 d. According to ®indication: A0
-> A14

5.9. For the SRAM child chip, the signals: A0 -> A13, D0 -> D15 are, wrong:
RD, WE. Pay the following ®©y

a. Chip capacity: 16K x 16 bits b. WE

SHOW SIGNALS when recording data c.
RD is displayed when recording data d. RD
Understanding Signals When Receiving Data

5.10. For the DRAM chip with the following signals: A0 -> A7, D0 -> ,D7
RD,, the
WE.signal:
Pay the
a. Chip
following
capacity:
®©y
64K x 8 bits b. Chip capacity: 8K x 8 bits c. RD is displayed when recording data d. WE KNOW IF YOU
ARE LOOKING FOR DATA

5.11. Strongly determined, they are very small in their nature:

a. Inside baby processor, RAM, ®disc b. Registers,
Internal, CD-ROM c. Registers, ROM, and d. Registers,
baby inside, baby out

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5.12. For the children of the computer, accept the following instructions: a. Follow me b.
Follow the child's cue of a and b ®Òu ®áng

c.
d. A and B ®u is wrong

5.13. Regarding the access methods in the child system, say the following error:
a. Access to prison for children cache b. Access
the link in the cache c. Accessing young people in
d. Direct access with ®media

5.14. For children, there are the following types of reasons: a.

Baby, RAM, cache baby b. Little baby, little baby, little
baby cache c. Baby Ben Den, Baby Baby, Baby Quang
d. Baby boy, baby boy cache, baby boy

5.15. If you are using a computer, any of the following statements do not have to be physically: a. Sea
children b. Children are not resistant to sea c. Young children ®îc d. Baby just ®äc

5.16. If you will report to the child, the following statements will be incorrect: a.
Set the fastest exchange load register ®i b. Switching error register
®pitch ®cache ® is divided into two levels
c.
d. Set the cache to connect the smallest register

5.17. If the child will be notified, the following announcement will be made: a. Let the
baby cache ®Õn the baby outside, tee ®é quickly b. Input register
®reducer ,reduce instruction ®Earth sub register ,reduced capacity
c.
d. Child in the child's cache, access speed is reduced

5.18. For small chips as shown, ® is the symbol for:

A0 -> A11

Chips D0 -> D7
kid
CS

RD WR
a. 4K x 8 bit SRAM

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b. 4K x 8 bit DRAM c. 2K
x 8 bit SRAM d. 2K x 8 bit
DRAM

5.19. For small chips as shown, ® is the symbol for:

A0 -> A12

RAS Chips D0 -> D15

CAS kid

CS

RD WR
a. SRAM 8K x 16 bit b.
DRAM 8K x 16 bit c. 64M x
16 bit SRAM d. 64M x 16-bit
DRAM

5.20. For the main child (BNC) on a computer, the following statements are wrong:
a. No problems with data using the library b. In principle, the person
who is involved in the argument can affect the whole BNC child. The management
c. of BNC logic depends on the model d. Correction is only directly handled
by the child

5.21. For the Main Child (BNC) on a computer, the following statements should be made: a.
Correction of BNCs in the form of type b. BNC is handled directly by the child.
Different types of computers BNC d. Little children can't wait in bytes

5.22. If you have a cache child, do the following: a. Cache is stored on

the same chip as the CPU b. The child is correct and faster than
the cache c. Children cache ®î ®Æ between the main child and
the other child d. Cache is not on the same chip as the CPU

5.23. If you have a cache child, do the following: a. The child outside can
see the cache data b. Data transfer between CPU and cache
according to commands and commands c. Data transfer between CPU
and cache according to the command and control d. When needed, the
CPU receives data directly from the main child.

5.24. When the CPU accesses the cache, both of the following
actions: a. Clear cache, empty cache

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b. Wrong cache, ®ong

cache c. Over the cache, go
to the cache d. In cache, out of cache

5.25. The active cache is based on the following principle:

a. Operating principles of computers b.
Principle ®i when recording data c.
Principle of ®when receiving ®data d. The
principle of ®

5.26. In the difference between the cache and the main child, say any of the following:
a. Child Chinh divided into small blocks b.
Cache divided into sub-lines c. Child Chinh
divided into several lines d. Line Stimulation By
Block Stimulation

5.27. Baby phone cache, mçi line ®î added Tag lµ ®Ó:

a. Identify the child's main block at ë in line b. Determine how
large the cache is c. Determine how much capacity the line has d.
Determine how many lines to cache

5.28. To fix the cache child, the following definitions are required: a.
Direct, complete linkage, composite linkage b. Complete
connection, direct link, continuous c. Consolidated, partial, and
immediate linkage d. Direct, partial links, short-term links

5.29. In the complete concatenation method, the above elements are: a. Tag
+ Word + Line b. Tag + Word c. Tag + Line + Word d. Tag + Line

5.30. In the direct method, the above elements are: a. Tag + Word
+ Line b. Tag + Word c. Tag + Line + Word d. Tag + Line

5.31. In the synergistic association method, the above elements are

indicated: a. Tag + Word + Set b. Tag + Word c. Tag + Set + Word
d. Tag + Set

5.32. For a computer, the main size: 128MB, cache: 64KB, line: 8 bytes, short length: 1 byte. In the case of the
direct operation, use only the child-processed ® method. ®Cache access is: a. 12 + 10 + 5 c. 14 + 11 + 2

b. 13 + 10 + 4
d. 14 + 10 + 3

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5.33. For a computer, the main size: 256MB, cache: 128KB, line: 16 bytes, short length: 2 bytes. In
the case of direct manipulation, use only the child-processed method to access the cache:

a. 11 + 13 + 3 b. 11 + 14 + 2
c. 12 + 13 + 4 d. 12 + 12 + 3

5.34. For a computer, the main size: 512MB, cache: 128KB, line: 64 bytes, short length: 4 bytes. In
the case of direct manipulation, use only the child-processed method to access the cache:

a. 11 + 11 + 5 b. 12 + 11 + 4
c. 12 + 12 + 3 d. 11 + 12 + 4

5.35. Gives a small amount of space: Main: 256MB, cache: 64KB, line: 16 bytes, short length: 4
bytes. In the case of a fully concatenated image processing algorithm, use only ® processing
generated by the child ®Cache access is: a. 13 + 11 + 2 c. 24 + 4
b. 12 + 12 + 2
d. 24 + 2

5.36. For a computer, the main size: 256MB, cache: 128KB, line: 32 bytes, short length: 4 bytes. In
the case of a fully concatenated image processing algorithm, use only ® processing generated by
the child ®Cache access is: a. 13 + 11 + 2 c. 23 + 3
b. 14 + 10 + 2
d. 24 + 2

5.37. Give a small capacity calculation Main: 128MB, cache: 64KB, line: 16 bytes, short length: 1
byte, set: 4 lines. In the case of the association association algorithm, use only the child-processed
code to access the cache: a. 13 + 10 + 4 c. 14 + 9 + 4
b. 13 + 9 + 5
d. 14 + 10 + 4

5.38. Give a small capacity calculation Main: 512MB, cache: 128KB, line: 32 bytes, short length: 2
bytes, set: 4 lines. In the case of the association association algorithm, use only the child-processed
code to access the cache: a. 12 + 12 + 4 c. 14 + 10 + 4
b. 13 + 11 + 4
d. 13 + 9 + 6

5.39. Give a small capacity calculation Main: 256MB, cache: 128KB, line: 128 bytes, short length: 4
bytes, set: 8 lines. In the case of the association association algorithm, use only the child-processed
code to access the cache: a. 13 + 8 + 5 c. 14 + 7 + 5
b. 13 + 7 + 6
d. 14 + 8 + 6

5.40. For direct response when accessing the cache, the txm blocks in the cache are executed
according to the above instructions generated by the CPU as follows:
a. Line -> Tag -> Word
b. Line -> Word -> Tag
c. Tag -> Line -> Word
d. Tags -> Word -> Line

5.41. For the cache child, the clustering association definition algorithm, which can block txm blocks in the cache, is executed
according to the number of caches in the memory, which is output only by the CPU as follows. :
a. Word -> Set -> Tag

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b. Set -> Word -> Tag c.

Set -> Tag -> Word d.
Word -> Tag -> Set

5.42. To specify the algorithm for replacing data in the cache, perform the following operations:
a. Don't disagree b. Direct
image does not change the full replacement algorithm
c. Two association effects (complete and union) of all four algorithms
d. B and C ®u ®ong

5.43. For small cache children, the data replacement algorithms are: a.
Power, FIFO, LRU, LFU b. Power, LIFO, LRU, LFU c. Power,
FIFO, LFU, LTU d. Power, LIFO, LTU, LVU

5.44. For the methods of writing data to the cache, any of the following statements will fail:
a. Write through: write additionally to the cache and main child b. Write
back: write only to the cache, when the block increases, you can write to the child instead.
Chinh
c. A and b ®u is wrong
d. A and B ®Òu ®ong

5.45. For the methods of writing data to the cache, do the following: a. Write back: write more to
the cache and main child b. Write through: only write to the cache, when the block is
removed, it will be written to the main child. a and b Òu ng ®ng d. A and B ®Òu ®ong

5.46. For the algorithm (TT) to replace the data in the cache, do the following: a. FIFO is the smallest change
of the current block in the current blocks b. LRU is the TT that replaces ®i block of the highest
number of accesses c. LFU will be replaced by the nearest access block ®©y Best d. NAME c¶ Òu
wrong

5.47. For the algorithm (TT) to replace the data in the cache, do any of the following errors: a. FIFO is the
TT that replaces the smallest trigger block in the current blocks b. FIFO is the TT that replaces ®i
block with the highest number of accesses c. LRU replaces ®i short access block ®©y Best d.
Random is a random block instead of a random block

5.48. For the algorithm (TT) to replace the data in the cache, do the following: a. LIFO is the TT that replaces
the smallest trigger block in the current blocks b. LTU TT replaces ®i block with the highest number
of accesses c. LVU TT replace ®i short access block ®©y Most d. NAME c¶ Òu wrong

5.49. For the algorithm (TT) to replace the data in the cache, any of the following will result in an error:
a. TT Random gives the highest number of cache
hits b. TT LRU gives the highest cache hit rate c.
TT FIFO gives the highest cache hit rate

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d. TT LFU for high rate of cache hits

5.50. Connect with 2 SRAM ICs to connect:

A0 -> A12

Chips Chips
D4 -> D7
kid kid D0 -> D3

RD
WR
CS

a. 4K x 4 bit ®There are 8K x 4 bit submodules available

b. 8K x 4 bits ®Each 16K x 4 bit child module
c. 8K x 4 bits ®There are 8K x 8 bit submodules
d. 4K x 4 bit ®Available 4K x 8 bit submodule

5.51. Connecting to the ®©isable to connect 2 SRAM

ICs: A0 -> A14

Chips Chips
D8 -> D15
kid kid D0 -> D7

RD
WR
CS
a. 32K x 8 bit ® 32K x 16 bit mini module
b. 16K x 8 bit ®Each 32K x 8 bit child module c.
32K x 4 bits ®Each 32K x 8 bit submodule d.
16K x 16 bit ® 32K x 16 bit mini module

5.52. How to connect with 4 SRAM ICs:

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A0 -> A13

D12 -> D15

Chips Chips Chips Chips D8 -> D11

kid kid kid kid D4 -> D7

D0 -> D3

RD
WR
a.
CS

a. 32K x 8 bit ® 32K x 16 bit mini module

b. 16K x 4 bits ®Occasionally 32K x 8 bit
submodule c. 16K x 4 bits ®There is a 16K x 16 bit
child module d. 32K x 4 bit ® 32K x 16 bit mini module

5.53. How to connect with 4 SRAM ICs:

A0 -> A11

D6 -> D7
Chips Chips Chips Chips D4 -> D5

kid kid kid kid D2 -> D3

D0 -> D1

RD
WR

CS

a. 4K x 4 bit ®Available 4K x 8 bit submodule

b. 4K x 2 bit ®Available 4K x 8 bit submodule
c. 8K x 4 bits ®There are 8K x 8 bit submodules
d. 8K x 2 bits ®There are 16K x 2 bit submodules

5.54. Check and connect with 2 SRAM ICs:

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A0 -> A10

Baby Chips

A11 A Y0

D0 -> D3
WOOD Y1
CS Baby Chips

RD WR

a. 2K x 4 bits ®There is a 4K x 4 bit submodule b.

2K x 4 bits ®There is a 4K x 8 bit child module c.
2K x 4 bits ®There is a 2K x 8 bit submodule d.
4K x 4 bit ®There are 8K x 4 bit submodules available

5.55. Check and connect with 2 SRAM ICs:

A0 -> A14

Baby Chips

A15
A Y0

D0 -> D7
WOOD Y1
CS Baby Chips

RD WR

a. 32K x 8 bit ® 32K x 16 bit mini module

b. 16K x 8 bit ®Each 32K x 8 bit child module
c. 32K x 8 bit ®Each 64K x 16 bit submodule d.
32K x 8 bit ®Ultra module 64K x 8 bit available

5.56. Check and connect with 4 SRAM ICs:

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A0 -> A9

Baby Chips
A10
A Y0
A11
REMOVE

Y1
Y2
Baby Chips
WOOD
Y3
CS

D0 -> D3
Baby Chips

Baby Chips

RD WR

a. 2K x 8 bits ®Occasionally 8K x 8 bit submodules

b. 2K x 4 bits ®Occasionally 8K x 8 bit submodule
c. 1K x 4 bits ®There is a 4K x 4 bit submodule d.
1K x 4 bits ® 4K x 8 bit submodules available

5.57. Check and connect with 4 SRAM ICs:

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A0 -> A12

Baby Chips
A13
A Y0
A14 REMOVE

Y1
Y2
Baby Chips
WOOD
Y3
CS

D0 -> D7
Baby Chips

Baby Chips

RD WR

a. 4K x 8 bit ®There are 16K x 8 bit submodules

b. 8K x 8 bit ®Each 32K x 8 bit submodule
c. 8K x 8 bit ®Each 16K x 8 bit child module
d. 8K x 16 bit ®16K x 16 bit submodule available

5.58. How to connect 4 SRAM ICs:

A0 -> A12

Baby Chips Baby Chips

A13
A Y0 D4 -> D7

D0 -> D3
WOOD Y1
CS Baby Chips Baby Chips

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RD

WR
Machine Translated by Google

a. 8K x 4 bits ®There are 16K x 8 bit submodules

b. 8K x 4 bits ®Each 16K x 4 bit child module c. 8K
x 8 bit ®Each 16K x 8 bit child module d. 8K x 8 bit
®16K x 16 bit mini module available

5.59. How to connect 4 SRAM ICs:

A0 -> A11

Baby Chips Baby Chips

A12
A Y0 D4 -> D7

D0 -> D3
WOOD
Y1
CS Baby Chips Baby Chips

RD

WR
a. 4K x 4 bits ®Each 16K x 8 bit submodule b. 8K x
8 bit ®There are 8K x 16 bit child modules c. 8K x 8
bit ®Each 16K x 8 bit child module d. 4K x 4 bits
®Occasionally 8K x 8 bit submodules

5.60. Since the SRAM microchip has a specific size, the maximum amount of data × capacity of the chip:
a. 2m x n bits
b. 2n xm bits c.
2m x n bytes d.
2n xm bytes

5.61. Since the SRAM microchip has a specific size, the maximum amount of data × capacity of the chip:
a. 2m x n bits
b. 22n xm bit c.
22m x n bits d.
2n xm bits

5.62. For the DRAM child chip, there is a special capacity, the maximum amount of data × the capacity of the chip:
a. 22m x n bits
b. 22n xm bits

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c. 22m x n bytes
d. 22n xm bytes

5.63. For the DRAM child chip, there is a special capacity, the maximum amount of data × the capacity of the chip:
a. 2m x n bits
b. 22n xm bit c.
22m x n bits d.
2n xm bits

5.64. For small children with cache, x Determine the management principle of the time, the following statements are
found: a. The correct login information will be accessed again only after it has been accessed b. The thx
access information is likely to be accessed later c. The following login information that has been selected will
not be accessed again d. The thx access information will be selected after the re-accessed

5.65. For small cache children, define the space management principle, say the following: a. The method of accessing
information will only be able to be accessed after all the other methods need to be accessed b. A secure access
information model will only be available after the remaining modules are accessible c. The method of accessing
information will definitely be selected after the remaining methods to be accessed d. The thx access information
will be sure to come after some are still not able to access

5.66. When accessing the cache, the image is processed directly, do the following: a. The Mçi
block has been added to the concrete line b. The Mçi block has been calculated on the
concrete line meter in the correct line set of c. The Mçi block is only ®delimited to a single line
meter d. The Mçi block is only ®calibrated to the meter in the correct line.

5.67. When accessing the cache, xIdentifies directly, any of the following ®© results in error: a.
Mçi block does not fit into the concrete line b. Mçi block does not fit into the square
meter in the correct line c. The Mçi block is only ®delimited to a single line meter d. The Mçi
block is only ®calibrated to the meter in two lines of precision

5.68. When accessing the cache, the image will be resolved completely, do one of the following: a. The Mçi
block has been added to the concrete line b. The Mçi block has been fixed to the concrete line in the
correct line c. The Mçi block is only ®delimited to a single line meter d. Mçi block is only adjusted to
meters within the correct line.

5.69. When accessing the cache, if the connection is complete, any of the following statements is wrong:
a. The Mçi block has been added to the concrete line b. The Mçi block has been calculated on
the concrete line in the correct line c. The Mçi block is not only ®defined to a single line meter d.
The Mçi block is not only aligned to the meter in the correct line.

5.70. When accessing the cache, xTo determine the association association, do the following: a. The Mçi
block has been added to the concrete line b. The Mçi block has been calculated on the concrete
line meter in the correct line set of c. The Mçi block is measured on the only line meter in the
exact line meter d. The Mçi block is only ®applied to a single line meter

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5.71. When accessing the cache, xIdentify the association association, the following
statements are wrong: a. The Mçi block has been calculated on the concrete
line meter in the correct line file. b. The Mçi block is not only defined to a single
line meter c. The Mçi block adjusts to the only line meter in the exact line meter
d. Mçi block is only defined in the exact line meter.

Chapter 6. They can't get in and out

6.1. No direct communication with external device (TBNV) by internal bus, v×: a. The
Management Board does not respond when accepting the names of employees b.
The ®é gives ®æi, different data usage areas c. The name of the device is older
than the processor and RAM d. Names of ideas ®u ®ong

6.2. Make sure to include the I/O Module:

a. Take care of the microprocessor and the
children b. Live with many meters or many
employees c. A and B ®u ®ong d. A and B ®u
is wrong

6.3. Members of the staff of staff members: a.

Baby Moves Signals, Logic, Baby B. Baby Moves, Logic, and
Consciousness c. Baby moves to display, Logic writes, Baby
checks d. Baby Moves, Moves, Logs

6.4. To make sure of the I/O Module, the following error occurs:
a. § When the time is available b.
Meters Modules are only used for the purpose of îCell Meters
TBNV c. Giving information to the processor, to the employee
d. Baby ®retrieve data, display lçi

6.5. The following methods of input/output only: a. I/O b. In/

out with your child ®å c. I/O by ®å register d. Doors
of a and b ®gong

6.6. To prevent differential input/output, do any of the following errors:

a. The space ® is not the same as the 'space ' baby b. Use the child access commands
®To access the same c. Signage for accessing and accessing children are different d.
Direct I/O commands

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6.7. To prevent differential I/O, do the following: a. The «baby ® space is

only the same as the «baby's' space b. Use the child access
commands ®To access the same c. Direct I/O commands d. Shared sign-
in for children and I/O

6.8. To prevent in/out according to the child's hand, the following statements are
wrong: a. The «baby ® space is only the same as the «baby's' space b. Use
the child access commands ®To access the same c. Not sure whether to
access with or without children d. Shared Access Tokens for parents and
children

6.9. In order to allow in/out with your baby, please do the following:
a. The «baby space ® is only the same as that of the «baby space»
b. Must know Signal when accessing baby or also in/out c. Direct I/
O commands d. Use the child access commands ®Using the same
access

6.10. There are 3 ways to enter/exit as follows:

a. I/O by DMA, by interrupt, by DMA b. In/out from
the network, the system, the DMA c. I/O by interrupt, by
CPU access, by DMA d. I/O by interrupt, by CPU access,
by system configuration

6.11. To prevent entering/exiting the program (CT), do any of the following errors: a.
Use the I/O command in the CT ®Obtain data with the same b. TBNV is a
major contributor to data exchange c. When executing CT, concatenate the
CPU I/O command while giving the data to TBNV d. Employees are greatly benefited
in exchanging data.

6.12. To prevent entering/exiting the program (CT), do the following: a. §Effective method
of transferring data in the shortest time b. Provides the fastest way to transfer
data c. The design of the remedy d. B and C ®u ®ong

6.13. To prevent unexpected I/O, do the following: a. Staff members are

always willing to exchange data b. CPU does not have to wait
for the full time of the staff c. The CPU I/O module is ready to go
d. The I/O module interrupts the CPU when the power is on.

6.14. To prevent unexpected I/O, do any of the following:

a. Staff members are very active in exchanging data b.
Fully legal department to handle the same part

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c. CPU slows down in data transfer

d. Completely legal department for handling

6.15. The number of blocks for adjusting the interrupt module:

a. 4 rooms
b. 3 rooms
c. 2 rooms
d. 1 room

6.16. Methods for adjusting the interrupt module include:

a. Check the area of the software and the general part, bus control, CPU capture
b. Many requirements are interrupted, check the area of the keyboard, bus stop, baby bird.
kid
c. Bus control, general area check, and many sever requirements
d. Many interruptions are required, check the balance of the parts and, in general, take into account.
bus

6.17. To prevent various types of interrupts (during the interrupt module setting), do the following:

a. The CPU has specific interrupt requirements for the I/O

modules b. The CPU must have different interrupt requirements for the I/O module.
c. The amount of waste that is used for the treatment
d. The CPU is conflicted with the interrupt requirements for the I/O module.

6.18. To check the area of the fraction (in the case of the interrupt modulus), do the following:

a. The processor checks multiple input/output modules

b. Quick drying
c. The processor performs the check of the I/O module
d. The processor performs the function of checking the I/O module.

6.19. For the same part area test (during the interrupt module determination), any of the following
statements is wrong:
a. The processor must accept the switch to accept the input/output modules.
b. I/O module ®Æt interrupts on the data bus
c. The processor uses the circuit breaker ® when it's hot.
d. NAME c¶ Òu wrong

6.20. Figure out how to fix any interruptions to the module:

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INTR 3

INTR 2
INTR 1

INTR 0

I/O
Modules I/O
Modules I/O
Modules I/O
Modules

log in
module log in
module log in
module module
log in
processor

a. Check the area with the mÒm

b. Check the same section
c. Many special requirements
d. Take the bus

6.21. Figure out how to fix any interruptions to the module:

Cê
INTRODUCTION

Shortcut
sweet request

I/O
Modules I/O
Modules I/O
Modules I/O
Modules

log in
module log in
module log in
module log in
module
processor

a. Check the area with the mÒm

b. Check the same section
c. Many special requirements
d. Take the bus

6.22. Figure out how to fix any interruptions to the module:

Data bus
Cê
INTRODUCTION

INTA
Supplied
sweet Bridge Requests

I/O
Modules I/O
Modules I/O
Modules I/O
Modules

module
log in module
log in module
log in module
log in
processor

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a. Check the area of the body b. The

same departmental inspection c. Many
severance requirements d. Take the
bus

6.23. For example, ®©y, do the following:

a. The X and Y stops are the same as the ®îc ®¸on the same
length b. ©y will ®å be similar to each other c. The X and Y
interrupts send the required signal along with the length d. After processing
the X interrupt, the Y . interrupt is handled

6.24. For example ®©y, the following statements ®©y are wrong:

a. ©y will ®å sever prison time

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b. X ®Creator Y c. The Y interrupt requests

the X interrupt d. Shut off Y ®îPull in after OFF
X

6.25. For example, ®©y, do the following:

a. §©yµwill ®åwithdrawal from

prison b. ©y will ®å be similar to each
other c. The X interrupt has a higher payout than the
Y switch d. The X and Y interrupts have the same money

6.26. For example ®©y, the following statements ®©y are wrong:

a. The Y interrupt has a higher payout than the X switch

b. ©y will ®å be similar to each other c. The Y interrupt
is finished processing the X interrupt d. The X interrupt
is finished processing the Y interrupt

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6.27. To prevent DMA in/out, do the following:

a. Errors due to CPU when transferring data b. The error
is not caused by the CPU when transferring the data c. Methods
for the implementation of this part d. The fastest way to exchange
data between employees and CPUs

6.28. To prevent DMA in/out, do the following: a. Employees use the DACK
signal to request data exchange b. The CPU uses DREQ ®Understand
®Acceptance DMA c. DMAC sends a message to HRQ ®Please use
bus lines d. DMAC sends HLDA ®Using bus lines

6.29. To prevent I/O using DMA, do any of the following: a. Refund by

DMAC upon handover of data b. §Collecting the data exchange
process between employees and children c. The CPU does not
interfere with the data transfer process d. CPU and DMAC combine
when transferring data

6.30. To prevent I/O using DMA, do any of the following: a. §©authorized

for the exchange of ædata b. Collective method for fast data transfer
c. When you turn on, the DMAC must ask for CPU permission d.
The need to exchange data from employees

6.31. The types of DMA data transfer are as follows:

a. Network DMA, Sequential DMA, High Meter DMA
b. DMA is on cycle time, DMA is second, DMA is transparent
c. More meter DMA, more cycle DMA, network DMA d. Sequential
DMA, Over m cycles DMA, Transparent DMA

6.32. In the meantime, do any of the following: a. Both

types of interrupts b. Every time ®option ®ac c.
Every time ®cannot be selected d. Shut down with
MI interrupts do not select ®îc

6.33. In the end, if any of the following statements is

wrong: a. Both types of interrupts b. Every time
®option ®ac c. Also, MI sends the INTR interrupt
d. Stop with the ®îc . selection switch

6.34. In the event of a shutdown, do the following:

a. Produced by the
processor b. Sent by
employee ®Õn c. Due to a sudden shutdown in
the process d. There is no order in the library

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6.35. In the event of a shutdown, which of the following statements

is incorrect: a. Not born of a child b. Not sent by employees
®Õn c. There is no need to measure the temperature in
the water column d. Meters in square meter

6.36. In case of an emergency, take the following actions: a. Irregularity

caused by a fault b. External interruption c. The ROM input
interrupt sends ®Õn d. Unforgettable holiday

6.37. In the event of an outage, the following statements are wrong:

a. The division by 0 generates an external interrupt b.
The wrong command can generate an external
interrupt c. Totally born out of date d. Little Lçi was born
unexpectedly 6.38. The circuit breaker for DMA Ion is
output in the following manner ®©y:
a. DREQ -> HLDA -> DACK -> HRQ -> hand over data-> close b. DREQ -> HRQ ->
HLDA -> DACK -> hand over data-> close c. HRQ -> HLDA -> DACK -> DREQ ->
hand over data-> close d. HRQ -> DACK -> DREQ -> HLDA -> hand over data-> close

6.39. In the case of DMA on demand, do the following: a. Unplug the data bus rçi
th× data transfer b. The processor must be suspended for more bus cycles
c. Non-contiguous data byte transmission d. Complete transmission of
data from the bus to the processor

6.40. In the case of a DMA on request, do the following: a. Processor but full
bus for DMAC b. The processor does not need to be suspended for
more bus cycles c. Non-linear transmission of 2 bytes of data d.
Complete transmission of data from the bus to the processor

6.41. If the DMA type is limited to cycle times, please do the following: a. The processor
and the DMAC are interleaved on the bus b. The processor will run the bus
completely c. DMAC will bust completely d. When a child rçi th× DMAC uses the
bus

6.42. If the DMA type is limited to cycle times, please select the following error: a. The
DMAC will only be as long as the bus has been installed b. The processor
does not have a full bus c. DMAC will bust completely d. Data is not transmitted
at high speed

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6.43. For a clear DMA model, do the following: a. When the DMAC does not
use the th× bus, the processor tries to use the bus b. When the
processor does not use the thx bus, compete with the DMA image
c. The processor and DMAC interleave using the bus d. DMAC CPU
Switching the bus

6.44. For a clear DMA model, say the following: a. When the DMAC does
not use the th× bus, the processor tries to use the bus b. DMA ® is
forwarded when the processor is not using the bus c. Processor
and DMAC use interleaved bus d. Processors and DMACs are not
the same bus

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