CS 202 Computer Organization and Architecture

Module 5
Processor Logic Design

E S . I N
NOT
Sheena N

KTU
Assistant Professor
Dept. of CSE
College of Engineering & Management Punnapra
[email protected]

May 1, 2017

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Overview

1 Register Trasfer Logic

2 Inter Register Transfer

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NOT
3 Arithmetic Microoperation

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4 Logic Micooperation

5 Shift Micooperation

6 Conditional Control Statements

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 Register Transfer Logic

Register Transfer Logic

Digital system
Sequential logic system constructed with flip flops and gates
Specified by means of state table
Difficult to specify a large digital system with state table because of
the huge number of states.
Modular approach
E S . I N
NOT
System is partitioned into modular subsytems with a specific functional

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task
Modules constructed from such digital functions are registers, counters,
decorders, multiplexers, arithmetic elements and control logic
Modules are interconnected with common data and control paths to
form a digital computer system .
Typical digital system module - processor unit of a digital computer
To decribe Digital system module high level mathemetical notations
are used - Register Trasfer Logic
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 Register Transfer Logic

Register Transfer Logic (cont.)

Register Trasfer Logic

. I
Regiters are the primitive component

E S N
Information flow and processing tasks among the data stored in

NOT
registers are described in precise and concise mannner

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Uses set of expressions & statements which resemble the statements in
programming language

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 Register Transfer Logic

Register Transfer Logic (cont.)

Components that form the basis of register transfer logic

1

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The set of registers in the system and their functions
The binary coded information stored in the registers

NOT
2

3 The operations performed on the information stored in the registers -

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Microoperations
4 The control functions that initiate the sequence of operations

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 Register Transfer Logic

Register Transfer Logic (cont.)

Registers
Emcompasses all type of registers such as shift registers, counters and
memory units

E S . I N
Counter :- Funtion is to increment by 1 the information stored within it

NOT
Memory unit :- Collection of storage registers where information can be

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stored
Flip flop :- stand alone flip flop is a 1 bit register
Flip flops and associated gates of any sequential circuit are called a
register

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 Register Transfer Logic

Register Transfer Logic (cont.)

The binary coded information stored in the registers

Binary information stored in registers may be binary numbers, binary

. I N
coded decimal numbers, alphanumeric characters, control information

E S
or any other binary coded information

NOT
The operations performed on the data stored in registers depend upon

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the type of data
Numbers are manipulated with arithmetic operations
Control information is manipulated with logic operations such as
setting and clearing specified bits in the register

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 Register Transfer Logic

Register Transfer Logic (cont.)

Microoperation
Operations performed in data stored in registers
Elementary operation that can be performed parallel during one clock
pulse period
The result of operation may replace the previous binary information of

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a register or may be transfered to another register
Eg. of microoperation - Shift, count, clear, add & load

E
NOT
A counter with parallel load - perform microoperations increment &
load

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Bidirectional shift register - Peform shift left & shift right
microoperation
Binry parallel adder - Used for implementing add micooperation on the
content of two registers that hold binary numbers
A microoperation requires one clock pulse for the execution if the
operation done in parallel
In serial computer a microoperation requires a number of clock pulses
equal to the word time in the system.
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 Register Transfer Logic

Register Transfer Logic (cont.)

Control information
Timing signals that sequence the operations one at a time
Certain conditions depend on the result of previous operations

N
determine the state of control functions

S . I
Control function is a binary variable that when in one binary state

E
NOT
initiates an opeartion and when in the other binary state inhibits the
operation

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Register transfer language(Computer hardware description language)
Symbolic notation used for registers, for specifying operations on the
contents of registers and specifying control functions
A statement in a register transfer language consists of control function
and a list of microoperations

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 Register Transfer Logic

Register Transfer Logic (cont.)

Types of micooperations in digital system

Interregister transfer microoperation
Do not change the information content when the binary information

Arithmetic operation

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moves from one register to another

NOT
Perform arithmetic on numbers stored in registers

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Logic microoperation
Perform operations such as AND and OR on individual pairs of bits
stored in registers
Shift microoperation
Specify operations for shift registers

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 Register Transfer Logic

Register Transfer Logic (cont.)

Categories of binary information found in registers of digital

computers

. I N
Numerical data such as binary numbers or binary coded decimal

E S
numbers used in arithmetic computations

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Nonnumerical data such as alphanumeric characters or any other
binary coded symbols used for special applications
Instruction codes, addresses and any other control information used
to specify the data processing requirements in the system

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 Inter Register Transfer

Inter Register Transfer

Registers in a digital system are designated by capital

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letters(sometimes followed by numerals) to denote function of register
Eg :- Register that holds address of memory - Memory address

NOT
register designated by MAR

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other designations are A, B, R1, R2 and IR
The cells or flipflops of n-bit register are numbered in sequence from
1 to n (from 0 to n-1) starting either from left or from right

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 Inter Register Transfer

Inter Register Transfer (cont.)

4 ways to represent register

Rectangular box with name of the register inside
The individual cells is assigned a letter with a subscript number
The numbering of cells from right to left can be marked on top of the
box

. I N
16 bit register is partitioned into 2 parts , bits 1 to 8 are assigned the

E S
NOT
letter L(for low) and bits 9 to 16 are assigned the letter H(for high)

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Figure: Block diagram of registers

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 Inter Register Transfer

Inter Register Transfer (cont.)

Registers can be specified in a register transfer language with a

declaration statement
Eg :- Registers in the above figure can be defined with declaration
statement such as

E S
DECLARE REGISTER A(8), MBR(12), PC(16)
. I N
NOT
DECLARE SUBREGISTER PC(L) = PC(1-8), PC(H) = PC(9-16)

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Information transfer from one register to another is designated in
sybolic form by means of replacement operator
A←B
Transfer of the contents of rgister B to register A.
Content of source register do not change

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 Inter Register Transfer

Inter Register Transfer (cont.)

Sometimes transfer occures under a predefined condition called
control function which is a boolean function equal to 1 or 0
Eg:-
0
x T1 : A ← B

E S .
Control function terminated with a colon
I N
Transfer occurs when x T1 = 1 ie, x=0 and T1 = 1

KTU NOT
0
Figure: hardware implementation of the statement x T1 : A ← B

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 Inter Register Transfer

Inter Register Transfer (cont.)

Table: Basic symbols for register trnsfer logic

E S . I N
KTU NOT

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 Inter Register Transfer

Inter Register Transfer (cont.)

Destination register receives information from two sources but not at
the same time
T1 : C ← A
T2 : C ← B

E S . I N
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Figure: Use of multiplexer to transfer information from two sources into a
single destination

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 Inter Register Transfer

Inter Register Transfer (cont.)

Bus transfer
Paths must be provided to transfer information from one register to
another in digital system

E S . I N
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Figure: Transfer among three registers

Eg :- Data tranfer among 3 registers - 6 data paths - each register

requires a multiplexer to select between 2 sources
If a register contains n flip flops - 6n lines - 3 multiplexers
Number of registers increases number of interconnection lines and
multiplexer increases
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 Inter Register Transfer

Inter Register Transfer (cont.)

If restrict transfer one at a time then the number of paths among

registers can be reduced

E S . I N
KTU NOT
Figure: Transfer through one common line

Each flipflop is connected to a common line through an electronic

circuit that acts as a switch
This scheme can be extended to registers with n flip flops and it
requires n common lines

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 Inter Register Transfer

Inter Register Transfer (cont.)

Bus :- Group of wires through which binary information is transfered
For parallel transfer number of lines in the bus is equal to the number
of bits in the registers
A common bus system can be constructed with multiplexers and

N
decoder

E S . I
Multiplexer selects one of the source register for the bus

NOT
Decoder selects one destination register to transfer the information

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from the bus
The 4-bits in the same significant position in the registers go through
4-to-1 line multiplexer to form one line of the bus
2 multiplexers are shown in figure - one for high order significant bit
and other for low order significant bits
For registers with n bits n multiplexers are needed to produce n line
bus
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 Inter Register Transfer

Inter Register Transfer (cont.)

n lines in the bus are connected to the n inputs of all registers
The transfer of information from the bus into one destination register
is accomplished by activting the load control of that register
The particular load control activated is selected by outputs of the
decoder when enabled.

S . I N
If decoder is not enabled no information will be transferred even

E
NOT
though the multiplexers place the contents of a source register onto

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the bus
Eg :- The statement C ← A The control function that enables this
transfer must select register A for the bus and register C for the
destination
The multiplexer and decoder selects inputs must be
select source = 00(MUXs select register A)
select destination = 10 (Decoder selects register C)
Decoder enable =0 (Decoder is enabled)
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 Inter Register Transfer

Inter Register Transfer (cont.)

E S . I N
KTU NOT
Figure: Bus system four registers

on the next clock pulse the content of A, being on the bus, are loaded
into register C
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 Inter Register Transfer

Inter Register Transfer (cont.)

Memory transfer
Read operation :- Transfer of information from memory register to
outside enviornment

E S . I N
NOT
Write operation :- Transfer of new information into memory register

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selected
Memory register is selected by an address Memory register is
symbolised by the letter M

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 Inter Register Transfer

Inter Register Transfer (cont.)

Only one address register is connected to the address terminals of
memory
This register specifies the address
The letter M stands by itself in a statement designate a memory
register selected by the address presently in MAR

out of memory

E S . I N
A single memory buffer register MBR used to transfer data into and

NOT
2 memory transfer operations - Read & Write

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Read operation :- Transfer of information from selected memory
register M specified by the address in MAR into MBR
R : MBR ← M
R is the control function that initiate the read operation
Write operation :- Trasfer of information from MBR into the register M
selected by the address presently in MAR
W : M ← MBR
W is the control function that intiate write operation

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 Inter Register Transfer

Inter Register Transfer (cont.)

E S . I N
KTU NOT
Figure: Memory unit that communicate with two external registers

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 Inter Register Transfer

Inter Register Transfer (cont.)

The address lines form a common bus system to allow many registers
to specify an address
The register specifies the address will be enclosed within square bracket
after the symbol M

S . I N
The address to the memory unit comes from an address bus
4 registers are connected to the bus and any one may supply an address

E
NOT
The output of the memory can go to any one of 4 registers selected by

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the decoder
Data input to the memory comes from the data bus which selects one
of the four registers
Write operation :- The transfer of information from register B2 to a
memory word selected by the register A1 is
W: M[A1] ← B2
Read operation :- R : B0 ← M[A3]

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 Inter Register Transfer

Inter Register Transfer (cont.)

E S . I N
KTU NOT
Figure: Memory unit that communicate with multiple registers

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 Arithmetic Microoperation

Arithmetic Microoperation

Basic arithmetic microoperations - add, subtract, complement & shift

The arithmetic add microoperations are defined by the statement

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F ←A+B

NOT
It states that the contents of register A are to be added to the

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contents of register B and the sum is transfered to register F
To implement this statement require 3 registers A, B and F and a
digital functon that performs the addition operation such as parallel
addder

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 Arithmetic Microoperation

Arithmetic Microoperation (cont.)

Table: Arithmetic microoperation

E S . I N
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Increment micropoperation symbolised by plus-one & implemented
with an up counter
Decrement micropoperation symbolised by minus-one & implemented
with an down counter

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 Arithmetic Microoperation

Arithmetic Microoperation (cont.)

There must be a direct relationship between the statements written in

a register transfer language and the registers and digital functions
which are required for the implementation
Consider the statements

E S . I N
T2 : A ← A + B

NOT
T5 : A ← A + 1

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Timing variable T2 initiates an operation to add the contents of
register B to the present contents of A with a parallel adder.
Timing variable T5 increments register A with a counter.
The transfer of the sum from parallel adder into register A can be
activated with a load input in the register.
Register be a counter with parallel load capability.

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 Arithmetic Microoperation

Arithmetic Microoperation (cont.)

The parallel adder receives input information from registers A and B.

The sum bits from the parallel adder are applied to the inputs of A

. I N
and timing variable T2 loads the sum into register A. Timing variable

E S
T5 increments there by enabling increment input register

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microoperations NOT
Multiplication - Implemented with sequence of add & shift

Division - Implemented with sequence of subtract & shift

microoperations

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 Arithmetic Microoperation

Arithmetic Microoperation (cont.)

E S . I N
KTU NOT
Figure: Implementation for addd and incrment microoperation

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 Logic Micooperation

Logic Micooperation

Specify binary operations for a string of bits stored in registers

Consider each bit in the registers separately and treat as a binary
variable

S . I N
Exclusive OR operation is symbolised by the statement
E
NOT
F ←A⊕B

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The + symbol has different meaning
T1 + T2 : A ← A + B, C ← D ∨ F
The + between T1 and T2 is an OR opeartion between 2 timing
variables of a control function
The + between A & B specifies an add microoperation

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 Logic Micooperation

Logic Micooperation (cont.)

Table: Logic & shift microoperation

E S . I N
KTU NOT

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 Shift Micooperation

Shift Micooperation

Transfers binary information between registers in serial computers

Used in parallel computers for arithmetic, logic and control operations
Registers are shifted to the left or to the right

. I N
No conventioal symbol for shift operation

E S
NOT
Here adopt symbols shl or shr
shl - shift left

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shr - shift right
Eg :-
A ← shl A - 1-bit shift to the left of register A
B ← shr B - 1-bit shift to the right of register B
While the bits are shifted extreme flip flops receive information from
the serial input

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 Shift Micooperation

Shift Micooperation (cont.)

Information transferred to extreme flip flop is not specified by shl or

shr symbols
Shift operation is accompanied with other microopeartion that

. I N
specifies the value of the serial input for the bit transfer into the

E S
NOT
extreme fip flop
Eg:-

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A ← shl, A1 ← An - Circular shift that tranfers the leftmost bit from
An into the rightmost flipflop A1
A ← shr , An ← E - Shift right opration with the leftmost flip flop An
receiving the value of the 1-bit register E

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 Conditional Control Statements

Conditional Control Statements

Specify a control condition by a conditional statement rather than a

boolean control function
Symbolised by if-then-else statement

S . I N
P : If(condition) then [microoperation(s)] else [microoperation(s)]

E
NOT
mean that if control condition stated within the parentheses after the

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word if is true, then microoperation enclosed within the parentheses
after the word then is executed otherwise the microoperation listed
within after the word else is executed
In any case the control function P must occur for anything to be done
If else part of the statement is missing then nothing is executed if the
condition is not true

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 Conditional Control Statements

Conditional Control Statements (cont.)

Eg:-
T2 : If (C=0) then (F ← 1) else (F ← 0)
F is asssumed to be 1-bit register(flip flop) that can be set or cleared.
If register C is a 1-bit register the statement is equivalent to the
following statements

E S . I N
C 0 T2 : F ← 1

NOT
CT2 : F ← 0

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Same timing variable can occur in two separate control function. The
valu of C is 0 or 1. So only one microoperation will be executed
during T2 depending on the value of C.
If C has more than 1 bit the condition C = 0 means that all bits of C
must be 0.
Register C has 4 bits C1 , C2 , C3 and C4 the condition C=0 can be
expressed with boolean function
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 Conditional Control Statements

Conditional Control Statements (cont.)

x = C10 C20 C30 C40 = (C1 + C2 + C3 + C4 )0

variable x can be generated with a NOR gate.

S . I N
Conditional control statements now equivalent to 2 statements

E
KTU NOT xT2 : F ← 1
x 0 T2 : F ← 0
variable x = 1 if C = 0 but is equal to 0 if C 6= 0

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 ES . I N
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