University of Technology Digital Laboratory

Department of Electrical and Electronic Engineering Third Year

Introduction to FPGA Programming

A Field-Programmable Gate Array (FPGA) is a semiconductor device

containing programmable logic components called "logic blocks", and
programmable interconnects. Logic blocks can be programmed to perform the
function of basic logic gates such as AND, and XOR, or more complex
combinational functions such as decoders or simple mathematical functions. In
most FPGAs, the logic blocks also include memory elements, which may be
simple flip- flops or more complete blocks of memories.

There are several different types of FPGA chips available and many
different types of technologies for those chips. The historical roots of FPGAs
are in Complex Programmable Logic Devices (CPLDs) of the early to mid
1980s. Ross Freeman, Xilinx cofounder, invented the field programmable gate
array in 1984- CPLDs and FPGAs include a relatively large number of
programmable logic elements.

General Procedure

The general procedure is used to simulate digital circuit design using

Xilinx ISE 9.2i software.

Procedure

.Verify the simulation design for two- input AND gate

:Starting the ISE software -1

.To start ISE, double - click the desktop icon as shown in Figure (1)

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Figure (1) Starting the ISE software.

2- Create a new project

a) Select File > New Project …the new project wizard appears.

b) Type tutorial in the project name field.

c) Enter or brows to a location (directory path) for the new

project. A tutorial subdirectory is created automatically.

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d) Verify that Schematic is selected from the Top – Level Source

Type as shown in Figure (2).

Figure (2) A new project wizard – create new project.

e) Click Next to move to the device properties page.

f) Fill in the properties table as shown below:

 Product category : ALL

 Family : Spartan 3

 Device: XC3S200

 Package : FT256

 Speed grade : - 4

 Top- Level Source Type : Schematic

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 Synthesis tool : XST ( VHDL / Verilog)

 Simulator : ISE simulator (VHDL / Verilog)

 Preferred language : Verilog

 Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields. When the table is complete,
.your project will look like Figure(3)

Figure (3) The project device properties.

g) Click Next to proceed and create new source window in the new project
.wizard, at the end of the next section, your new project will be completed

Creating a schematic source -3

:Create a schematic source file for the project as follows
.a) Click the New source button in the new project wizard
.b) Select schematic module as the source type

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.c) Type in the file name and

.d)Verify that the Add to project check the box is selected
.e) Click Next, as shown in Figure (4) and Figure (5)

Figure (4) The module defines.

.Figure (5) The circuit connection

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Design simulation. Verifying functionally using behavioral simulation. Create -4

a test bench waveform containing input stimulus you can use to verify the
functionality of the AND module. The test bench waveform is a graphical view
:of a test bench. Create the test bench waveform as follows

.a) Select the AND HDL file in the sources window

.b) Create a new test bench source by selecting, Project  New source

c) In the new source wizard select Test Bench Waveform as the source type,
.AND-tbw in the file name field

d) Click Next

e) The associated source page shows that you are associating the test bench
waveform with the source file and Click Next.

f) The summary page shows that the source will be added to the project and it
displays the source directory, type and name click Finish.

g) You need to test the clock frequency, setup time, and output delay times in
the initialize timing dialog box before the test bench waveform editing window
opens. The design requirements correspond with the values below: Fill in the
fields in the initialize timing dialog box with the following information:

 : Clock high time: …… ns

 Clock low time: …… ns
 Input setup time: …… ns
 Output valid delay: …… ns
 Offset:………. ns
 Global signals GSR (FPGA)
Note: when GRS (FPGA) is enabled, 100ns is added to the offset value
automatically.

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 Initial length of test bench: 1500ns.

Leave the remaining values in the remaining fields as shown in Figure (6).

Figure (6) The initialize timing.

.h) Click Finish to complete the timing initializing as shown in Figure (7)

Figure (7) The test bench waveform.

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.k) Save the waveform

L) In the source window, select the Behavioral Simulation view to see that the
.test bench waveform file is automatically added to your project

.m) Close the test bench waveform

Simulating Design Functionality -5

Verify that the counter design functions as you expect to perform behavior
:simulation as follows
1- Verify the Behavioral Simulation AND-tbw is selected in the source
window.
2- In the Processes tab, click the "+" to expand the Xilinx ISE simulator
process and double click the Simulate Behavioral Model process. The
ISE simulator opens and runs the simulation to the end of the test bench.

3- To view your simulation results, select the Simulation tab and zoom in on
the transitions. The simulation waveform results will look like Figure (8).

Figure (8) The simulation results.

You have now completed simulation of your design using ISE simulator.

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University of Technology Digital Laboratory
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EXPERIMENT NUMBER (1)

Design Logic Gates and Exclusive-OR Applications Based on FPGA

OBJECT

To understand how can draw the logic gates and get simulation by using
Xilinx ISE 9.2i software FPGA to create FPGA designs for the XESS XSA
.boards

THEORY

We will study the various types of logic gates and the applications of
Exclusive-OR that make up a typical digital system. The emphasis is on the
logical operation of the circuits and the limitation and considerations involved
in their operation. It is very important to know that the output of a gate is for
various combinations of inputs and to understand how the electrical
characteristics affect its operation so that we can predict and analyze how a
circuit will perform in a given system.

THE AND GATE

The AND gate performs the basic operation of logic multiplication more
commonly known as the AND function as shown in Figure (1-1). The operation
of the AND gate is such that the output is HIGH only when all of the inputs are
HIGH. When any of the inputs is LOW, the output is LOW as shown in

Table (1-1).

.Fig. (1-1) The two- input AND gate symbol

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.Table (1-1) Truth table for two – input AND gate

A B C
0 0 0
0 1 0
1 0 0
1 1 1

THE OR GATE

The operation of the OR gate is such that a HIGH on the output is

produced when any of the inputs is HIGH. The output is LOW only when all of
the inputs are LOW. Therefore, the purpose of an OR gate is to determine when
one or more of its inputs are HIGH and to determine when one or more of its
inputs are HIGH and to produce a HIGH on its output to indicate this condition.
The Two – input OR gate symbol and its truth table is shown in Figure (1-2) and
table (1-2) respectively.
A C
B
Fig. (1- 2) The two – input OR gate symbol.

.Table (1-2) Truth table for a Two – input OR gate

A B C
0 0 0
0 1 1
1 0 1
1 1 1

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THE INVERTOR

Figure (1-3) show the symbol of inverter. When a HIGH level is

applied to an inverter input, a LOW level will appear on its output, when a
LOW level is applied to its input a HIGH will appear on its output as illustrated
.in Figure (1-3)

.Fig. (1- 3) The NOT gate symbol

.Table (1- 3) Truth table for NOT gate

A C
0 1
1 0

THE NAND GATE

Figure (1-4) show the symbol of NAND gate, which is a logic circuit
whose output is LOW when all inputs are HIGH as illustrated in table (1-4).

A C
B
Fig. (1-4) The two inputs NAND gate symbol.

Table (1-4 ) Truth table for two –input NAND gate.

A B C
0 0 1
0 1 1
1 0 1
1 1 0

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THE NOR GATE

Figure (1-5) show the symbol of NOR gate, which is a logic circuit whose
output is LOW when at least one of its input is HIGH as illustrated in table(1-5).

A C
B

Fig. (1-5) The two input NOR gate symbol.

Table (1-5) Truth table for NOR gate.

A B C
0 0 1
0 1 0
1 0 0
1 1 0

THE EXCLUSIVE- OR GATE

Figure (1-6) show the symbol of EX-OR gate, which is a logic circuit
whose output is HIGH when one input ( but not both) is HIGH as illustrated in
table(1-6).

Fig. (1-6) The EX- OR gate symbol.

Table (1-6) Truth table for EX- OR gate.

A B C
0 0 0
0 1 1
1 0 1
1 1 0

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THE EXCLUSIVE - NOR GATE

Figure (1-7) show the symbol of EX-NOR gate, which is a logic circuit
whose output is the complement of an exclusive – OR gate as illustrated in table
(1-7).

A C
B
Fig. (1- 7) the EX – NOR gate symbol

Table (1-7) truth table for EX -NOR

A B C
0 0 1
0 I 0
1 0 0
1 1 1

THE APPLICATIONS OF EX – OR GATE

1- Parity Checker

Errors can occur as digital codes are being transferred from one point to
another within a digital system or while codes are being transmitted from one
system to another. The errors like the form of understanding change in the bits
that make up of coded information that is a 1 can be changed to 0 or a 0 to 1,
due to component many functions or electrical noise. If we have three bit word,
to detect the occurrence of an odd number of errors in this word, a single bit
will be added to the word that makes the number of ones in the word either even
number (even parity) or odd number (odd parity), so if an odd number of errors
occurred in the word, then, the total number of ones will not remain the same, it
will change from odd to even or from even to odd. The EX – OR gate is the
most suitable circuit to provide parity checker. Figure (1-8) gives the circuit of
three bit even parity checker.

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A
B

C X

L=even parity bit

H=odd parity bit

Fig. (1- 8) Three-bit parity checker.

2. Control Inverter

We can use EX- OR gate as a ( NOT ) gate by connecting one of either

inputs to logic 1, for this reason it can be used to complement a word by
using one of the inputs as control line as shown in Figure(1-9). When
control signal is logic zero then:

A = X, B = Y, C = Z.

When control signal is logic one then:

A = X, B = Y, C = Z.

A B C

Control signal

x y z

Fig. (1- 9) The control inverter logic circuit.

3. Binary To Gray and Gray To Binary Conversion

The gray code is widely used in many digital systems especially in

shaft encoders and analog to digital converters, but it is very difficult to use
the gray – code in arithmetic operations, since there is only one bit change
between any two consecutive gray code number, and it is un weighted code,

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and the EX – OR gate is the most suitable gate for this purpose as shown in
Figure (1-10).

(a) (b)

Fig. (1-10) (a) Binary to gray code inverter. (b) Gray to binary code inverter.

4. Digital comparator

The basic function of a comparator is to compare the magnitude of

two quantities in order to determine the relationship of those quantities. In
its simplest form, a comparator circuit determines if two numbers are
equal. The EX – OR gate is a basic comparator because its output is a one
if its two inputs are not equal and zero if the two inputs are equal. If the
comparison is, such that the state of one number with respect to the other
is to be specified one of three conditions: A > B, A < B, A = B as shown
in Figure (1-11).

B A>B

A<B

A=B

.Fig. (1- 11) The logic diagram of two-bit numbers comparator

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:APPARATUS
1- FPGA on the XSA Board.
2- Xilinx ISE 9.2i software FPGA
PROCEDURE
1- Connect the circuit shown in Figure (1-1), draw the input, and output
waveforms.
2- Connect the three inputs OR gate and draw the input and output
waveform.
3- Repeat step (2) for 3-input NAND gate and NOR gate.
4- Repeat step (1) for EX-OR gate and EX-NOR gate.
5- Connect the circuit shown in Figure (1-8) and draw the input and
output waveform and find its truth table..
6- Repeat step (5) for Figure (1- 9), Figure (1-10), and Figure (1- 11).

7- Implement all steps illustrated above using FPGA on the XSA Board.

DISCUSSION
Implement EX–OR gate using NOR gate only and find the simulation .1
.result

.Design and simulate four bits even parity checker .2

.Design and simulate four bits binary to gray converter .3

Show that the dual of EX – OR is equal to its complement (design and .4

.simulation)

.Determine the output waveform simulation shown in Figure (1-12) .5

B A
B
C Y
D

Figure (1-12)

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EXPERIMENT NUMBER (2)

DESIGN DECODERS AND ENCODERS BASED ON FPGA

OBJECT

Design decoders and encoder's circuits and get simulation by using

Xilinx ISE 9.2i software FPGA to create FPGA designs for the XESS XSA
.boards
THEORY

The process of taking some type of code and determining what it

represents in terms of a recognizable number or character is called decoding. A
decoder is a combinational logic circuit that performs the decoding function and
produces an output that indicates the meaning of the input code. An encoder is
combinational logic circuit that essentially perform a reverse decoder function,
an encoded accepts a digital on its inputs such as a decimal or octal digital and
converse it to a coded output such as binary or BCD. Encoders canals be
devised to encode varies symbols and alphabetic characters this process of
converting from familiar symbols or numbers to a coded format is called
encoding.

ENCODERS:

An encoder is a digital function that produces a reverse operation from

that of a decoder. An encoder has 2n (or less) input lines and n output.

BCD DECODER:

The BCD decoder converts each BCD code word (8421) into one of ten
possible decimal digit indications. It is typically referred to as a 1–of –10 or 4–
line – to 10-line decoder. The method of implementation is essentially the same
as for the 1-of-16 decoder, except that only ten decimal digits 0 through 9.

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BCD TO SEVEN – SEGMENT DECODER:

This type of decoder accepts the BCD code on its inputs provides outputs
to energize seven – segment display devices in order to produce a digital
readout. Figure(2 -1 ) shows a common display format composed of seven light
– emitting elements or segments. By lighting certain combinations of these
segments, each of the ten decimal digits can be produced.
a
f b
g

e c
d

Fig. (2-1) Seven – segment display digit.

APPARATUS:

1- FPGA on the XSA Board.

2- Xilinx ISE 9.2i software FPGA.
PROCEDURE
1- Design and simulate internal structure of (2*4) decoder.
2- Simulate (2*4) decoder using block.
3- Design the internal structure of (3*8) decoder.
4- Simulate (4*16) decoder using block and find its true table.
5- Design and simulate internal structure (4*2) encoder.
6- Design and simulate internal structure (8*3) encoder.
7- Implement all steps illustrated above using FPGA on the XSA Board.

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DISCUSSION

1) If the input waveforms are applied to the decoding logic as indicated in

Figure (2-2) bellow. Simulate the output waveform in proper relation to
the inputs.
A

B Y

Fig. (2-2)
2) Draw and simulate the logic diagram of (2*4) decoder using NOR gates
only.
3) Implement and find simulation result of the following function using
decoder F= A B C + A B.
4) Draw and simulate the logic diagrams of (8*3) encoder using NAND
gates only.
5) BCD numbers are applied sequentially to the BCD – to – decimal in
Figure (2-3) draw using software the ten output waveforms, showing each
in the relation ship to the other and to the input D is the MSB.

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0
A 1
2
B 3
4
C 5
6
D 7
8
9

.Fig. (2-3) BCD to decimal decoder

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EXPERIMENT NUMBER (3)

DESIGN MULTIPLEXER AND DEMULTIPLEXER BASED ON

FPGA

OBJECT

Design multiplexer, demultiplexer circuits, and get simulation by using

Xilinx ISE 9.2i software FPGA to create FPGA designs for the XESS XSA
.boards

THEORY

A multiplexer is a device that allows digital information from several

sources to be routed onto a single line for transmission over that line to a
common destination. The basic multiplexer, then, has several input lines and
a single output line. It also has control or selection inputs that permit digital
data on any one of the inputs to be switched to the output line. A blocked
diagram symbol for a four – input multiplexer is shown in Figure (3- 1).

Fig. (3-1) Four – line multiplexer block diagram.

A Demultiplexer basically reverse the multiplexer function. It takes data

from one line and distributes them to a given number of outputs. Figure (3-2)
shows block diagram for a one-line– to four-line demultiplexer circuit.

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D0

D1
Data Input Data Output
D2

D3
S1 S0

Data Select

Fig. (3-2) Four-demultiplexer block diagram.

APPARATUS:

1- FPGA on the XSA Board.

2- Xilinx ISE 9.2i software FPGA.

PROCEDURE

1- Design and simulate internal structure of (2 * 1) multiplexer.

2- Simulate (2 * 1) multiplexer using blocks.
3- Design and simulate internal structure of (4 * 1) multiplexer.
4- Design and simulate internal structure of (1 * 2) demultiplexer.
5- Design and simulate internal structure of (1 * 4) demultiplexer.
6- Implement all steps illustrated above using FPGA on the XSA Board.

DISCUSSION

1- For the four–input multiplexer shown in Figure(3-3) below determine by

using software the output state if the data select inputs is shown in
Figure(3-4).

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1 D0

0 D1
Output
1 D2

0 D3

S1 S0

Fig. (3-3)

S1

S0

Fig. (3-4)
2- Implement and simulate the following function using multiplexer
F=AC+BC+ABC

3- Design and simulate (1 * 4) demultiplexer.

4- Design and simulate internal structure of (8 * 1) multiplexer.

5- Design and simulate full adder using multiplexer.

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University of Technology Digital Laboratory
Department of Electrical and Electronic Engineering Third Year

EXPERIMENT NUMBER (4)

DESIGN FLIP – FLOPS BASED ON FPGA

OBJECT

Design various types of flip – flops and get simulation by using Xilinx
.ISE 9.2i software FPGA to create FPGA designs for the XESS XSA boards

THEORY

The flip – flop belongs to a category of digital circuits known as

multivibrators. There are three basic types of multivibrators in common use:
the bistable multivibrators, the monostable multivibrators, and the astable
multivibrators. The bistable multivibrator is commonly called as flip – flop.
The flip – flop has two stable states. It is capable of being in either a HIGH
state (logic 1) or a LOW state (logic o) indefinitely. Since it can retain either
state. It is useful as a storage or memory device. The flip – flop finds wide
application digital system as a building block for counters, registers,
memories control logic and other functions.

S - R FLIP – FLOP

Figure (4-1) shows a basic positive edge – triggered S – R flip – flop.

Fig. (4-1) The positive edge triggered S – R flip – flop.

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D FLIP – FLOP

The D flip – flop is very useful in cases where a single data bit (1 or 0) is
to be stored. The simple addition of an inverter to an S – R flip – flop creates a
basic D flip – flop, as shown in Figure (4-2) which a positive edge – triggered
type.

Fig. (4-2) The positive edge –triggered D flip - flop

J - K FLIP – FLOP

The J – K flip – flop is very versatile and perhaps the most widely used
type of flip – flop as shown in Figure (4-3).

Fig. (4-3) The positive edge triggered J – K Flip-Flop.

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Figure (4-4) shows a J – K flip – flop with preset and clear inputs, this
illustrate how these inputs work.

Fig. (4-4) J – K flip – flop with active LOW preset and clear

APPARATUS:

1- FPGA on the XSA Board.

2- Xilinx ISE 9.2i software FPGA.
PROCEDURE

1-Connect the circuit shown in Figure (4-1). Find the simulation and truth
table.

2-Find the simulation of S – R Flip – Flop blocks.

3-Connect the circuit shown in Figure (4-2). Find the simulation and truth table.
4-Find the simulation of D flip – flop blocks.
5-Connect the circuit shown in Figure (4-3). Find the simulation and truth table.
6-Find the simulation of J - K flip – flop blocks.
7-Connect the circuit shown in Figure (4-4).Find the simulation and truth table.
8-Find the simulation of J - K flips – flop blocks with preset and clear.

9- Implement all steps illustrated above using FPGA on the XSA Board.

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DISCUSSION

1- For the Figure(4-5) simulate the output result, assume initial Reset

J1 = 0 1 00 1 0 1 1 J2 = 1 0 0 0 1 0 0 1 K1 = 0 1 1 10 1 1 0

K2 = 0 1 0 1 0 0 1 0 K3 = 0 1 1 1 1 0 1 1

J1
K1 J Q

CLK
K1
K2 K Q
K3

Fig. (4-5)

2- For the edge – triggered J – K flip – flop with PRESET and CLEAR in Figure
(4-6), Determine the simulation output for the inputs shown in the timing diagram,
Q is initially LOW.

PR
HIGH

J Q

CLK
K Q

CLR

CLK
PR

CLR

Fig. (4-6)

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3- Determine simulation output waveform if the signal shown in Figure (4-7)

below is applied to inputs of the edge – triggered J – K Flip–Flop. Q is initially
LOW.

PR

J Q

CLK
K Q

CLR

CLK

PR

CLR

Fig.(4-7)

4- Sketch and simulate the Q output of flip – flop B in Figure(4-8) below in

proper relation to the clock. The Flip-Flops are initially RESET. The following
serial data stream is be generated using a J – K flip – flop. Determine
(simulation) the input required (0101 1100 0011 1011).

A B
J Q J Q

K Q K Q

CLK

Fig. (4-8)

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EXPERIMENT NUMBER (5)

DESIGN BINARY COUNTERS BASED ON FPGA

OBJECT

Design various asynchronous and synchronous counters and get simulation

by using Xilinx ISE 9.2i software FPGA to create FPGA designs for the XESS
.XSA boards

THEORY
A digital counter is a logic circuit that can progress through a sequence
of numbers or states when activated by a clock pulse input. The outputs of
counters indicate the binary number contained within the counter at any given
time.
1) Asynchronous Binary Counter
Figure (5-1) shows a two –stage counter connected for asynchronous
operation each flip-flop in counter commonly referred to a stage of the counter.

Fig. (5-1) A two stage asynchronous binary counter.

A three - stage asynchronous binary counter is shown in Figure(5-2).

Fig. (5-2) Three – stage asynchronous binary counter.

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A logic circuit for asynchronous decade counter is shown in Figure (5-3)

it consists of four stages and have any given sequence of states as long as there
are ten.

Fig. (5-3) Asynchronous decade binary counter.

2) Synchronous Binary Counter
The counter shown in Figure (5-4) for a two stage synchronous counter.

Fig. (5-4) A two stage synchronous binary counter.

A three stage synchronous binary counter is shown in Figure (5-5).

Fig. (5-5) A three stage synchronous binary counter.

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Synchronous decade counter shown in Figure (5-6).

Fig. (5-6) Synchronous decade binary counter.

APPARATUS:
1- FPGA on the XSA Board.
2- Xilinx ISE 9.2i software FPGA.

PROCEDURE
1- Connect the circuit shown in Figure (5-1). Find the table and its timing
diagram by using software.

2- Repeat step 1 for circuit shown in Figure (5-2) and Figure (5-3).

3- Simulate the four stage asynchronous binary counter by using blocks.

4- Connect the circuit shown in Figure (5-4). Find the table and its timing
diagram by using software.

5- Repeat step 1 for circuit shown in Figure (5-5) and Figure (5-6).

6- Simulate the four stage synchronous binary counter by using blocks.

7- Implement all steps illustrated above using FPGA on the XSA Board.

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DISCUSSION

1. Design and simulation a counter that has the following repeated sequence
(0, 3, 8, 5, 12) using J –K flip – flop.

2. Design and simulation a counter that has the following repeated sequence
(1, 2, 3, 4, and 5) using T flip – flop.

3. Design and simulation asynchronous counter count (0, 1, 2, 3, 4) using J–

K Flip–Flop.

4. The state diagram for a positive edge – triggered counter shown in the
Figure (5-7). Sketch the corresponding timing diagram.

CK1 CK2 CK3 CK4 CK5

start 1 4 7 9 12 14

Fig. (5-7)

5. Draw the complete timing diagram for the five-stage synchronous binary
counter shown in Figure (5-8) below verify that the waveform of the Q
outputs represent the proper binary number after each clock pulse.

Fig.(5-8)

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EXPERIMENT NUMBER (6)

DESIGN SHIFT REGISTER BASED ON FPGA

OBJECT

Design various types of shift register and get simulation by using Xilinx
.ISE 9.2i software FPGA to create FPGA designs for the XESS XSA boards

THEORY
The shift register is very important in applications involving the storage
and transfer of data in a digital system the basic difference between a register
and a counter is that a register has no specified sequence of states except in
certain very specialized applications a register in general is used to delay for the
purpose of storing and shifting data (1s and 0s) entered into it form an external
source and possesses no characteristic internal sequence of states.
Serial in Serial out Shift Register
Figure (6-1) shows a four- bit Serial in – serial out shift register
Data SA QA SB QB SC QC SD QD Data output
input
CLK CLK CLK CLK

RA RB RC RD Data output

FFA FFB FFC FFD

Clock

Fig. (6-1) Serial in – Serial out shift register.

Serial in Parallel out Shift Register
Figure (6-2) shows a four bit serial in parallel out register.
Data SA QA SB QB SC QC SD QD
input
CLK CLK CLK CLK

RA QA RB QB RC QC RD QD

Clock

QA QB QC QD

Fig. (6-2) Serial in – parallel out shift register.

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Department of Electrical and Electronic Engineering Third Year

Parallel In Serial out Shift Register

Figure (6-3) illustrates a four-bit parallel in serial register.

DA DB DC DD
PE

SA QA SB QB SC QC QD
SD
CLK CLK
CLK CLK
RA RB RC RD

Clock

Fig. (6-3) Parallel in – serial out shift register.

Parallel In – Parallel Out Shift Registers]

Figure (6-4) shows parallel in – parallel out shift register.

DA DB DC DD

SA QA SB QB SC QC SD QD

CLK CLK CLK CLK

RA RB RC RD

Clock

QA QB QC QD

Fig. (6-4) Parallel In – Parallel Out shift register.

APPARATUS:
1- FPGA on the XSA Board.
2- Xilinx ISE 9.2i software FPGA.

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University of Technology Digital Laboratory
Department of Electrical and Electronic Engineering Third Year

PROCEDURE

1) Connect the circuit shown in Figure (6-1) and find its timing using software.

2) Repeat step (1) for Figure (6-2), Figure (6-3) and Figure (6-4).

3) Find the simulation of Figure (6-1), Figure (6-2), Figure (6-3) and Figure (6-
4) by using block.

4) Implement all steps illustrated above using FPGA on the XSA Board.

DISCUSSION

1) For the data input and clock timing diagram in Figure (6-5), determine the
state of each flip-flop in the Figure (6-1), Assume the register contains all one
initially.

CLK

Data in

Fig. (6-5)

2) What is the state of the register shown in Figure (6-6) after each clock pulse
if it starts in the 100101 state?

Dat i Dat ou
a n a t
CLK 6- bit register
Data in

Fig. (6-6)

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University of Technology Digital Laboratory
Department of Electrical and Electronic Engineering Third Year

3) Show using simulation the state of the five bit Serial in parallel out shift
register for the data input and clock waveform shown in Figure(6-7). The
register initially contains all 1s.

CLK

Data in

Fig. (6-7)

4) Show using simulation the output wave form for a five –bit Parallel in serial
out shift register with the input data PE , and clock wave form as shown in
Figure(6-8). The register is initially cleared.

CLK

PE

Fig. (6-8)

5) Determine using simulation the count sequence of feed back shift register
shown in Figure (6-9) assume the initial state is (10101).

CK

A QA Q B QC QD

Fig. (6-9)

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