SPC560B40x, SPC560B50x

SPC560C40x, SPC560C50x
32-bit MCU family built on the Power Architecture®
for automotive body electronics applications
Datasheet - production data

– Up to 6 FlexCAN interfaces (2.0B active)

with 64-message objects each
– Up to 4 LINFlex/UART
LQFP100 (14 x 14 x 1.4 mm) – 3 DSPI / I2C
LQFP64 (10 x 10 x 1.4 mm)  Single 5 V or 3.3 V supply
LQFP144 (20 x 20 x 1.4 mm)
 10-bit analog-to-digital converter (ADC) with up
to 36 channels
Features
– Extendable to 64 channels via external
 High-performance 64 MHz e200z0h CPU multiplexing
– 32-bit Power Architecture® technology – Individual conversion registers
– Up to 60 DMIPs operation – Cross triggering unit (CTU)
– Variable length encoding (VLE)  Dedicated diagnostic module for lighting
 Memory – Advanced PWM generation
– Up to 512 KB Code Flash with ECC – Time-triggered diagnostic
– 64 KB Data Flash with ECC – PWM-synchronized ADC measurements
– Up to 48 KB SRAM with ECC  Clock generation
– 8-entry memory protection unit (MPU) – 4 to 16 MHz fast external crystal oscillator
 Interrupts (FXOSC)
– 16 priority levels – 32 kHz slow external crystal oscillator
(SXOSC)
– Non-maskable interrupt (NMI)
– 16 MHz fast internal RC oscillator (FIRC)
– Up to 34 external interrupts incl. 18 wakeup
lines – 128 kHz slow internal RC oscillator (SIRC)
– Software-controlled FMPLL
 GPIO: 45(LQFP64), 75(LQFP100),
123(LQFP144) – Clock monitor unit (CMU)
 Timer units  Exhaustive debugging capability
– 6-channel 32-bit periodic interrupt timers – Nexus1 on all devices
– 4-channel 32-bit system timer module – Nexus2+ available on emulation package
– Software watchdog timer (LBGA208)
– Real-time clock timer
 Low power capabilities
 16-bit counter time-triggered I/Os
– Ultra-low power standby with RTC, SRAM
– Up to 56 channels with PWM/MC/IC/OC
and CAN monitoring
– ADC diagnostic via CTU
– Fast wakeup schemes
 Communications interface
 Operating temp. range up to -40 to 125 °C
Table 1. Device summary
Part number
Package
256 KB code Flash memory 512 KB code Flash memory
LQFP144 SPC560B40L5 — SPC560B50L5 —
LQFP100 SPC560B40L3 SPC560C40L3 SPC560B50L3 SPC560C50L3
LQFP64(1) SPC560B40L1 SPC560C40L1 SPC560B50L1 SPC560C50L1
1. All LQFP64information is indicative and must be confirmed during silicon validation.

February 2015 DocID14619 Rev 13 1/116

This is information on a product in full production. www.st.com
Contents SPC560B40x/50x, SPC560C40x/50x

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 41
3.11.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 41
3.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.13 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.14 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.14.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.14.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.15 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.15.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.15.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.15.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.15.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.15.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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SPC560B40x/50x, SPC560C40x/50x Contents

3.16 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.17 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 60
3.17.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 60
3.17.2 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . 65
3.18 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.19 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.19.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.19.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.19.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.20 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 70
3.20.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 70
3.20.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.20.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 71
3.21 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 72
3.22 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 75
3.23 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.24 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 78
3.25 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 79
3.26 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.26.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.26.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.27 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.27.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.27.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.27.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.27.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.1 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.2 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.3 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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Contents SPC560B40x/50x, SPC560C40x/50x

5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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SPC560B40x/50x, SPC560C40x/50x List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. SPC560B40x/50x and SPC560C40x/50x device comparison . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary . . . . . . . . . . . . . . . . . . . . 13
Table 4. Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11. WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 13. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 14. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 15. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 16. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 17. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 18. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 49
Table 20. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 21. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 22. I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 24. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 25. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 26. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 27. Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 28. Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 29. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 30. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 31. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 32. Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 33. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 34. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 36. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 37. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 74
Table 39. Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 77
Table 41. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 78
Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 79
Table 44. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 45. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 46. On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 47. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 48. Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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List of tables SPC560B40x/50x, SPC560C40x/50x

Table 49. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 50. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 51. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 52. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 53. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 54. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 55. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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SPC560B40x/50x, SPC560C40x/50x List of figures

List of figures

Figure 1. SPC560B40x/50x and SPC560C40x/50x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. LQFP 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP 100-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. LQFP 144-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 7. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 8. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 9. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 10. VDD_HV and VDD_BV maximum slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. VDD_HV and VDD_BV supply constraints during STANDBY mode exit . . . . . . . . . . . . . . . . 62
Figure 12. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 13. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 14. Fast external crystal oscillator (4 to 16 MHz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 15. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16. Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 17. Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 18. ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 19. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 20. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 21. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 22. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 23. DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 24. DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 25. DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 26. DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 27. DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 28. DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 29. DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 30. DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 31. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 32. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 33. Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 34. LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 35. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 36. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 37. LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 38. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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7
Introduction SPC560B40x/50x, SPC560C40x/50x

1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device. To
ensure a complete understanding of the device functionality, refer also to the device
reference manual and errata sheet.

1.2 Description
The SPC560B40x/50x and SPC560C40x/50x is a family of next generation microcontrollers
built on the Power Architecture embedded category.
The SPC560B40x/50x and SPC560C40x/50x family of 32-bit microcontrollers is the latest
achievement in integrated automotive application controllers. It belongs to an expanding
family of automotive-focused products designed to address the next wave of body
electronics applications within the vehicle. The advanced and cost-efficient host processor
core of this automotive controller family complies with the Power Architecture embedded
category and only implements the VLE (variable-length encoding) APU, providing improved
code density. It operates at speeds of up to 64 MHz and offers high performance processing
optimized for low power consumption. It capitalizes on the available development
infrastructure of current Power Architecture devices and is supported with software drivers,
operating systems and configuration code to assist with users implementations.

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 SPC560B40x/50x, SPC560C40x/50x
Table 2. SPC560B40x/50x and SPC560C40x/50x device comparison(1)
Device
Feature SPC560B SPC560B SPC560B SPC560C SPC560C SPC560B SPC560B SPC560B SPC560C SPC560C SPC560B
40L1 40L3 40L5 40L1 40L3 50L1 50L3 50L5 50L1 50L3 50B2

CPU e200z0h
Execution
Static – up to 64 MHz
speed(2)
Code Flash 256 KB 512 KB
Data Flash 64 KB (4 × 16 KB)
RAM 24 KB 32 KB 32 KB 48 KB
MPU 8-entry
DocID14619 Rev 13

ADC (10-bit) 12 ch 28 ch 36 ch 8 ch 28 ch 12 ch 28 ch 36 ch 8 ch 28 ch 36 ch
CTU Yes
(3)
Total timer I/O 12 ch, 28 ch, 56 ch, 12 ch, 28 ch, 12 ch, 28 ch, 56 ch, 12 ch, 28 ch, 56 ch,
eMIOS 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit
– PWM + MC +
2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch
IC/OC(4)
– PWM +
10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch
IC/OC(4)
– IC/OC(4) — 3 ch 6 ch — 3 ch — 3 ch 6 ch — 3 ch 6 ch
SCI (LINFlex) 3(5) 4
SPI (DSPI) 2 3 2 3 2 3 2 3
CAN (FlexCAN) 2(6) 5 6 3(7) 5 6
I2C 1
32 kHz oscillator Yes

Introduction
GPIO(8) 45 79 123 45 79 45 79 123 45 79 123
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 Table 2. SPC560B40x/50x and SPC560C40x/50x device comparison(1) (continued)
10/116

Introduction
Device
Feature SPC560B SPC560B SPC560B SPC560C SPC560C SPC560B SPC560B SPC560B SPC560C SPC560C SPC560B
40L1 40L3 40L5 40L1 40L3 50L1 50L3 50L5 50L1 50L3 50B2

Debug JTAG Nexus2+

LBGA208
Package LQFP64(9) LQFP100 LQFP144 LQFP64(9) LQFP100 LQFP64(9) LQFP100 LQFP144 LQFP64(9) LQFP100 (10)

1. Feature set dependent on selected peripheral multiplexing—table shows example implementation.

2. Based on 125 °C ambient operating temperature.
3. See the eMIOS section of the device reference manual for information on the channel configuration and functions.
4. IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter.
5. SCI0, SCI1 and SCI2 are available. SCI3 is not available.
6. CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.
DocID14619 Rev 13

7. CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available.
8. I/O count based on multiplexing with peripherals.
9. All LQFP64 information is indicative and must be confirmed during silicon validation.
10. LBGA208 available only as development package for Nexus2+.

SPC560B40x/50x, SPC560C40x/50x
SPC560B40x/50x, SPC560C40x/50x Block diagram

2 Block diagram

Figure 1 shows a top-level block diagram of the SPC560B40x/50x and SPC560C40x/50x

device series.

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115
Block diagram SPC560B40x/50x, SPC560C40x/50x

Figure 1. SPC560B40x/50x and SPC560C40x/50x block diagram

SRAM Code Flash Data Flash

JTAG
48 KB 512 KB 64 KB
JTAG port

64-bit 2 x 3 Crossbar Switch

Instructions
Nexus port SRAM
e200z0h (Master) Flash
Nexus controller controller

Data

MPU
NMI
Nexus 2+ (Slave)
(Master)
SIUL
Voltage (Slave)
regulator
Interrupt requests (Slave)
NMI from peripheral
blocks MPU
INTC registers
Clocks CMU
FMPLL

RTC STM SWT ECSM PIT MC_RGM MC_CGM MC_ME MC_PCU BAM SSCM

Peripheral bridge

SIUL 36 Ch. 2x 4x 3x 6x
Reset control ADC CTU eMIOS LINFlex DSPI I2C FlexCAN
Interrupt
request External
interrupt
request
IMUX
WKPU
GPIO and
pad control

Interrupt
request with
wakeup
I/O ... ... ... ... ...
functionality
Legend:

ADC Analog-to-Digital Converter MC_ME Mode Entry Module

BAM Boot Assist Module MC_PCU Power Control Unit
FlexCAN Controller Area Network MC_RGM Reset Generation Module
CMU Clock Monitor Unit MPU Memory Protection Unit
CTU Cross Triggering Unit Nexus Nexus Development Interface (NDI) Level
DSPI Deserial Serial Peripheral Interface NMI Non-Maskable Interrupt
eMIOS Enhanced Modular Input Output System PIT Periodic Interrupt Timer
FMPLL Frequency-Modulated Phase-Locked Loop RTC Real-Time Clock
I2C Inter-integrated Circuit Bus SIUL System Integration Unit Lite
IMUX Internal Multiplexer SRAM Static Random-Access Memory
INTC Interrupt Controller SSCM System Status Configuration Module
JTAG JTAG controller STM System Timer Module
LINFlex Serial Communication Interface (LIN support) SWT Software Watchdog Timer
ECSM Error Correction Status Module WKPU Wakeup Unit
MC_CGM Clock Generation Module

Table 3 summarizes the functions of all blocks present in the SPC560B40x/50x and
SPC560C40x/50x series of microcontrollers. Please note that the presence and number of
blocks vary by device and package.

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SPC560B40x/50x, SPC560C40x/50x Block diagram

Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary

Block Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

A block of read-only memory containing VLE code which is executed according
Boot assist module (BAM)
to the boot mode of the device
Clock monitor unit (CMU) Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the eMIOS
Cross triggering unit (CTU)
or from the PIT
Deserial serial peripheral interface
Provides a synchronous serial interface for communication with external devices
(DSPI)
Provides a myriad of miscellaneous control functions for the device including
Error Correction Status Module program-visible information about configuration and revision levels, a reset
(ECSM) status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host
(eDMA) processor via “n” programmable channels.
Enhanced modular input output
Provides the functionality to generate or measure events
system (eMIOS)
Flash memory Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated phase- Generates high-speed system clocks and supports programmable frequency
locked loop (FMPLL) modulation
Internal multiplexer (IMUX) SIU
Allows flexible mapping of peripheral interface on the different pins of the device
subblock
A two wire bidirectional serial bus that provides a simple and efficient method of
Inter-integrated circuit (I2C™) bus
data exchange between devices
Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
JTAG controller
transparent to system logic when not in test mode
Manages a high number of LIN (Local Interconnect Network protocol) messages
LINFlex controller
efficiently with a minimum of CPU load
Clock generation module Provides logic and control required for the generation of system and peripheral
(MC_CGM) clocks
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
Mode entry module (MC_ME)
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Reduces the overall power consumption by disconnecting parts of the device
Power control unit (MC_PCU) from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module
Centralizes reset sources and manages the device reset sequence of the device
(MC_RGM)

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Block diagram SPC560B40x/50x, SPC560C40x/50x

Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary (continued)

Block Function

Provides hardware access control for all memory references generated in a

Memory protection unit (MPU)
device
Nexus development interface Provides real-time development support capabilities in compliance with the
(NDI) IEEE-ISTO 5001-2003 standard
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
A free running counter used for time keeping applications, the RTC can be
Real-time counter (RTC) configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit (SIU) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Static random-access memory
Provides storage for program code, constants, and variables
(SRAM)
Provides system configuration and status data (such as memory size and
System status configuration
status, device mode and security status), device identification data, debug
module (SSCM)
status port enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AUTOSAR (Automotive
System timer module (STM)
Open System Architecture) and operating system tasks
Software watchdog timer (SWT) Provides protection from runaway code
The wakeup unit supports up to 18 external sources that can generate interrupts
Wakeup unit (WKPU) or wakeup events, of which 1 can cause non-maskable interrupt requests or
wakeup events.
Supports simultaneous connections between two master ports and three slave
Crossbar (XBAR) switch ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.

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SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions

3 Package pinouts and signal descriptions

3.1 Package pinouts

The available LQFP pinouts and the LBGA208 ballmap are provided in the following figures.
For pin signal descriptions, please refer to the device reference manual (RM0017).

Figure 2. LQFP 64-pin configuration(a)

VDD_HV
VSS_HV
VDD_LV
VSS_LV

PH[10]
PC[8]
PC[4]
PC[5]
PH[9]
PC[0]

PC[1]

PC[2]
PC[3]
PB[2]

PA[6]
PA[5]
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB[3] 1 48 PA[11]
PC[9] 2 47 PA[10]
PA[2] 3 46 PA[9]
PA[1] 4 45 PA[8]
PA[0] 5 44 PA[7]
VSS_HV 6 43 PA[3]
VDD_HV 7 42 PB[15]
VSS_HV 8 41 PB[14]
RESET 9 LQFP64 Top view 40 PB[13]
VSS_LV 10 39 PB[12]
VDD_LV 11 38 PB[11]
VDD_BV 12 37 PB[7]
PC[10] 13 36 PB[6]
PB[0] 14 35 PB[5]
PB[1] 15 34 VDD_HV_ADC
PC[6] 16 33 VSS_HV_ADC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PC[7]

VDD_LV
VSS_LV
XTAL
VSS_HV
EXTAL
VDD_HV
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]

PB[9]
PB[8]
PB[10]
PB[4]

a. All LQFP64 information is indicative and must be confirmed during silicon validation.

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Figure 3. LQFP 100-pin configuration

VDD_HV
VSS_HV
VDD_LV
VSS_LV
PC[13]
PC[12]

PH[10]

PE[12]
PC[8]

PC[4]
PC[5]

PH[9]
PC[0]

PC[1]

PC[2]
PC[3]
PB[2]

PE[7]
PE[6]
PE[5]
PE[4]

PE[3]
PE[2]

PA[6]
PA[5]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[3] 1 75 PA[11]
PC[9] 2 74 PA[10]
PC[14] 3 73 PA[9]
PC[15] 4 72 PA[8]
PA[2] 5 71 PA[7]
PE[0] 6 70 VDD_HV
PA[1] 7 69 VSS_HV
PE[1] 8 68 PA[3]
PE[8] 9 67 PB[15]
PE[9] 10 66 PD[15]
PE[10] 11 65 PB[14]
PA[0] 12 64 PD[14]
PE[11] 13 63 PB[13]
VSS_HV 14 LQFP100 62 PD[13]
VDD_HV 15 61 PB[12]
VSS_HV 16 Top view 60 PD[12]
RESET 17 59 PB[11]
VSS_LV 18 58 PD[11]
VDD_LV 19 57 PD[10]
VDD_BV 20 56 PD[9]
PC[11] 21 55 PB[7]
PC[10] 22 54 PB[6]
PB[0] 23 53 PB[5]
PB[1] 24 52 VDD_HV_ADC
PC[6] 25 51 VSS_HV_ADC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD_LV
VSS_LV

VSS_HV

VDD_HV
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]

PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
XTAL

EXTAL

Note:
Availability of port pin alternate functions depends on product selection.

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Figure 4. LQFP 144-pin configuration

VDD_HV
VSS_HV
VDD_LV
VSS_LV

PG[10]

PG[15]
PG[14]
PC[13]
PC[12]

PH[10]

PG[11]

PE[15]
PE[14]

PE[12]
PC[8]

PH[8]
PH[7]
PH[6]
PH[5]
PH[4]

PC[4]
PC[5]

PH[9]
PC[0]

PC[1]

PC[2]
PC[3]
PB[2]

PE[7]
PE[6]

PE[5]
PE[4]

PE[3]
PE[2]

PA[6]
PA[5]
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120

109
119
118
117
116
115
114
113
112

110
111
PB[3] 1 108 PA[11]
PC[9] 2 107 PA[10]
PC[14] 3 106 PA[9]
PC[15] 4 105 PA[8]
PG[5] 5 104 PA[7]
PG[4] 6 103 PE[13]
PG[3] 7 102 PF[14]
PG[2] 8 101 PF[15]
PA[2] 9 100 VDD_HV
PE[0] 10 99 VSS_HV
PA[1] 11 98 PG[0]
PE[1] 12 97 PG[1]
PE[8] 13 96 PH[3]
PE[9] 14 95 PH[2]
PE[10] 15 94 PH[1]
PA[0] 16 93 PH[0]
PE[11] 17 92 PG[12]
VSS_HV
VDD_HV
18
19
LQFP144 91
90
PG[13]
PA[3]
VSS_HV 20 89 PB[15]
RESET 21 Top view 88 PD[15]
VSS_LV 22 87 PB[14]
VDD_LV 23 86 PD[14]
VDD_BV 24 85 PB[13]
PG[9] 25 84 PD[13]
PG[8] 26 83 PB[12]
PC[11] 27 82 PD[12]
PC[10] 28 81 PB[11]
PG[7] 29 80 PD[11]
PG[6] 30 79 PD[10]
PB[0] 31 78 PD[9]
PB[1] 32 77 PB[7]
PF[9] 33 76 PB[6]
PF[8] 34 75 PB[5]
PF[12] 35 74 VDD_HV_ADC
PC[6] 36 73 VSS_HV_ADC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
XTAL

EXTAL
VDD_LV
VSS_LV

VSS_HV

VDD_HV
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]

PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
Note:
Availability of port pin alternate functions depends on product selection.

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Package pinouts and signal descriptions SPC560B40x/50x, SPC560C40x/50x

Figure 5. LBGA208 configuration

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A PC[8] PC[13] NC NC PH[8] PH[4] PC[5] PC[0] NC NC PC[2] NC PE[15] NC NC NC A

B PC[9] PB[2] NC PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] NC PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B

C PC[14] VDD_HV PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] NC PA[5] NC PE[14] PE[12] PA[9] PA[8] C

D NC NC PC[15] NC PH[6] PE[4] PE[2] VDD_LV VDD_HV NC PA[6] NC PG[10] PF[14] PE[13] PA[7] D

E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E

F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F

G PE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV NC NC MSEO G

H VSS_HV PE[11] VDD_HV NC VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H

J RESET VSS_LV NC NC VSS_HV VSS_HV VSS_HV VSS_HV NC NC NC NC J

K EVTI NC VDD_BV VDD_LV VSS_HV VSS_HV VSS_HV VSS_HV NC PG[12] PA[3] PG[13] K

L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L

M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M

N PB[1] PF[9] PB[0] NC NC PA[4] VSS_LV EXTAL VDD_HV PF[0] PF[4] NC PB[11] PD[10] PD[9] PD[11] N

VDD_HV
P PF[8] NC PC[7] NC NC PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3] PB[6] PB[7] P
_ADC

OSC32K VSS_HV
R PF[12] PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] NC PF[3] PF[7] PD[2] PD[4] PD[7] PB[5] R
_XTAL _ADC

OSC32K
T NC NC NC MCKO NC PF[13] PA[12] NC PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T
_EXTAL

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1. Note: LBGA208 available only as development package for Nexus 2+. NC = Not connected

3.2 Pad configuration during reset phases

All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are forced to tristate with the following exceptions:
 PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from
flash.
 PA[8] (ABS[0]) is pull-up.
 RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
 JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate.
 Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).
 Main oscillator pads (EXTAL, XTAL) are tristate.
 Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.

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3.3 Voltage supply pins

Voltage supply pins are used to provide power to the device. Three dedicated
VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization.

Table 4. Voltage supply pin descriptions

Pin number
Port pin Function
LQFP64 LQFP100 LQFP144 LBGA208(1)

C2, D9, E16,

15, 37, 70, 19, 51, 100,
VDD_HV Digital supply voltage 7, 28, 56 G13, H3, N9,
84 123
R5
G7, G8, G9,
G10, H1, H7,
14, 16, 35, 18, 20, 49, H8, H9, H10,
VSS_HV Digital ground 6, 8, 26, 55
69, 83 99, 122 J7, J8, J9,
J10, K7, K8,
K9, K10
1.2V decoupling pins. Decoupling
VDD_LV capacitor must be connected between 11, 23, 57 19, 32, 85 23, 46, 124 D8, K4, P7
these pins and the nearest VSS_LV pin.(2)
1.2V decoupling pins. Decoupling
VSS_LV capacitor must be connected between 10, 24, 58 18, 33, 86 22, 47, 125 C8, J2, N7
these pins and the nearest VDD_LV pin.(2)
VDD_BV Internal regulator supply voltage 12 20 24 K3
Reference ground and analog ground for
VSS_HV_ADC 33 51 73 R15
the ADC
Reference voltage and analog supply for
VDD_HV_ADC 34 52 74 P14
the ADC
1. LBGA208 available only as development package for Nexus2+
2. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage
(see the recommended operating conditions in the device datasheet for details).

3.4 Pad types

In the device the following types of pads are available for system pins and functional port
pins:
S = Slow(b)
M = Medium(b) (c)
F = Fast(b) (c)
I = Input only with analog feature(b)
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator

b. See the I/O pad electrical characteristics in the device datasheet for details.

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3.5 System pins

The system pins are listed in Table 5.

Table 5. System pin descriptions

Pin number

RESET configuration
I/O direction
System pin

Pad type

LBGA208(1)
LQFP100

LQFP144
LQFP64
Function

Input, weak
Bidirectional reset with Schmitt-Trigger characteristics
RESET I/O M pull-up only 9 17 21 J1
and noise filter.
after PHASE2
Analog output of the oscillator amplifier circuit, when the
oscillator is not in bypass mode.
EXTAL I/O X Tristate 27 36 50 N8
Analog input for the clock generator when the oscillator
is in bypass mode.(2)
Analog input of the oscillator amplifier circuit. Needs to
XTAL I X Tristate 25 34 48 P8
be grounded if oscillator is used in bypass mode.(2)
1. LBGA208 available only as development package for Nexus2+
2. See the relevant section of the datasheet

3.6 Functional ports

The functional port pins are listed in Table 6.

c. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium
(see PCR.SRC in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual).

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Table 6. Functional port pin descriptions

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[0] SIUL I/O
AF1 E0UC[0] eMIOS_0 I/O
PA[0] PCR[0] AF2 CLKOUT CGL O M Tristate 5 12 16 G4
AF3 — — —
— WKPU[19](4) WKPU I
AF0 GPIO[1] SIUL I/O
AF1 E0UC[1] eMIOS_0 I/O
AF2 — — —
PA[1] PCR[1] S Tristate 4 7 11 F3
AF3 — — —
(5)
— NMI WKPU I
— WKPU[2](4) WKPU I
AF0 GPIO[2] SIUL I/O
AF1 E0UC[2] eMIOS_0 I/O
PA[2] PCR[2] AF2 — — — S Tristate 3 5 9 F2
AF3 — — —
— WKPU[3](4) WKPU I
AF0 GPIO[3] SIUL I/O
AF1 E0UC[3] eMIOS_0 I/O
PA[3] PCR[3] AF2 — — — S Tristate 43 68 90 K15
AF3 — — —
— EIRQ[0] SIUL I
AF0 GPIO[4] SIUL I/O
AF1 E0UC[4] eMIOS_0 I/O
PA[4] PCR[4] AF2 — — — S Tristate 20 29 43 N6
AF3 — — —
— WKPU[9](4) WKPU I
AF0 GPIO[5] SIUL I/O
AF1 E0UC[5] eMIOS_0 I/O
PA[5] PCR[5] M Tristate 51 79 118 C11
AF2 — — —
AF3 — — —
AF0 GPIO[6] SIUL I/O
AF1 E0UC[6] eMIOS_0 I/O
PA[6] PCR[6] AF2 — — — S Tristate 52 80 119 D11
AF3 — — —
— EIRQ[1] SIUL I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[7] SIUL I/O
AF1 E0UC[7] eMIOS_0 I/O
PA[7] PCR[7] AF2 LIN3TX LINFlex_3 O S Tristate 44 71 104 D16
AF3 — — —
— EIRQ[2] SIUL I
AF0 GPIO[8] SIUL I/O
AF1 E0UC[8] eMIOS_0 I/O
AF2 — — —
Input, weak
PA[8] PCR[8] AF3 — — — S 45 72 105 C16
pull-up
— EIRQ[3] SIUL I
N/A(6) ABS[0] BAM I
— LIN3RX LINFlex_3 I
AF0 GPIO[9] SIUL I/O
AF1 E0UC[9] eMIOS_0 I/O
PA[9] PCR[9] AF2 — — — S Pull-down 46 73 106 C15
AF3 — — —
N/A(6) FAB BAM I
AF0 GPIO[10] SIUL I/O
AF1 E0UC[10] eMIOS_0 I/O
PA[10] PCR[10] S Tristate 47 74 107 B16
AF2 SDA I2C_0 I/O
AF3 — — —
AF0 GPIO[11] SIUL I/O
AF1 E0UC[11] eMIOS_0 I/O
PA[11] PCR[11] S Tristate 48 75 108 B15
AF2 SCL I2C_0 I/O
AF3 — — —
AF0 GPIO[12] SIUL I/O
AF1 — — —
PA[12] PCR[12] AF2 — — — S Tristate 22 31 45 T7
AF3 — — —
— SIN_0 DSPI0 I
AF0 GPIO[13] SIUL I/O
AF1 SOUT_0 DSPI_0 O
PA[13] PCR[13] M Tristate 21 30 44 R7
AF2 — — —
AF3 — — —

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[14] SIUL I/O
AF1 SCK_0 DSPI_0 I/O
PA[14] PCR[14] AF2 CS0_0 DSPI_0 I/O M Tristate 19 28 42 P6
AF3 — — —
— EIRQ[4] SIUL I
AF0 GPIO[15] SIUL I/O
AF1 CS0_0 DSPI_0 I/O
PA[15] PCR[15] AF2 SCK_0 DSPI_0 I/O M Tristate 18 27 40 R6
AF3 — — —
— WKPU[10](4) WKPU I
AF0 GPIO[16] SIUL I/O
AF1 CAN0TX FlexCAN_0 O
PB[0] PCR[16] M Tristate 14 23 31 N3
AF2 — — —
AF3 — — —
AF0 GPIO[17] SIUL I/O
AF1 — — —
AF2 — — —
PB[1] PCR[17] S Tristate 15 24 32 N1
AF3 — — —
— WKPU[4](4) WKPU I
— CAN0RX FlexCAN_0 I
AF0 GPIO[18] SIUL I/O
AF1 LIN0TX LINFlex_0 O
PB[2] PCR[18] M Tristate 64 100 144 B2
AF2 SDA I2C_0 I/O
AF3 — — —
AF0 GPIO[19] SIUL I/O
AF1 — — —
AF2 SCL I2C_0 I/O
PB[3] PCR[19] S Tristate 1 1 1 C3
AF3 — — —
— WKPU[11](4) WKPU I
— LIN0RX LINFlex_0 I
AF0 GPIO[20] SIUL I
AF1 — — —
PB[4] PCR[20] AF2 — — — I Tristate 32 50 72 T16
AF3 — — —
— GPI[0] ADC I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[21] SIUL I
AF1 — — —
PB[5] PCR[21] AF2 — — — I Tristate 35 53 75 R16
AF3 — — —
— GPI[1] ADC I
AF0 GPIO[22] SIUL I
AF1 — — —
PB[6] PCR[22] AF2 — — — I Tristate 36 54 76 P15
AF3 — — —
— GPI[2] ADC I
AF0 GPIO[23] SIUL I
AF1 — — —
PB[7] PCR[23] AF2 — — — I Tristate 37 55 77 P16
AF3 — — —
— GPI[3] ADC I
AF0 GPIO[24] SIUL I
AF1 — — —
AF2 — — —
PB[8] PCR[24] I Tristate 30 39 53 R9
AF3 — — —
— ANS[0] ADC I
— OSC32K_XTAL(7) SXOSC I/O
GPIO[25]
AF0 SIUL I
—
AF1 — —
—
AF2 — —
PB[9] PCR[25] — I Tristate 29 38 52 T9
AF3 — —
ANS[1]
— ADC I
OSC32K_EXTAL(
— 7) SXOSC I/O

AF0 GPIO[26] SIUL I/O

AF1 — — —
AF2 — — —
PB[10] PCR[26] J Tristate 31 40 54 P9
AF3 — — —
— ANS[2] ADC I
— WKPU[8](4) WKPU I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[27] SIUL I/O
AF1 E0UC[3] eMIOS_0 I/O
PB[11]
(8) PCR[27] AF2 — — — J Tristate 38 59 81 N13
AF3 CS0_0 DSPI_0 I/O
— ANS[3] ADC I
AF0 GPIO[28] SIUL I/O
AF1 E0UC[4] eMIOS_0 I/O
PB[12] PCR[28] AF2 — — — J Tristate 39 61 83 M16
AF3 CS1_0 DSPI_0 O
— ANX[0] ADC I
AF0 GPIO[29] SIUL I/O
AF1 E0UC[5] eMIOS_0 I/O
PB[13] PCR[29] AF2 — — — J Tristate 40 63 85 M13
AF3 CS2_0 DSPI_0 O
— ANX[1] ADC I
AF0 GPIO[30] SIUL I/O
AF1 E0UC[6] eMIOS_0 I/O
PB[14] PCR[30] AF2 — — — J Tristate 41 65 87 L16
AF3 CS3_0 DSPI_0 O
— ANX[2] ADC I
AF0 GPIO[31] SIUL I/O
AF1 E0UC[7] eMIOS_0 I/O
PB[15] PCR[31] AF2 — — — J Tristate 42 67 89 L13
AF3 CS4_0 DSPI_0 O
— ANX[3] ADC I
AF0 GPIO[32] SIUL I/O
AF1 — — — Input, weak
PC[0](9) PCR[32] M 59 87 126 A8
AF2 TDI JTAGC I pull-up
AF3 — — —
AF0 GPIO[33] SIUL I/O
AF1 — — —
PC[1](9) PCR[33] M Tristate 54 82 121 C9
AF2 TDO(10) JTAGC O
AF3 — — —

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[34] SIUL I/O
AF1 SCK_1 DSPI_1 I/O
PC[2] PCR[34] AF2 CAN4TX(11) FlexCAN_4 O M Tristate 50 78 117 A11
AF3 — — —
— EIRQ[5] SIUL I
AF0 GPIO[35] SIUL I/O
AF1 CS0_1 DSPI_1 I/O
AF2 MA[0] ADC O
PC[3] PCR[35] AF3 — — — S Tristate 49 77 116 B11
— CAN1RX FlexCAN_1 I
— CAN4RX(11) FlexCAN_4 I
— EIRQ[6] SIUL I
AF0 GPIO[36] SIUL I/O
AF1 — — —
AF2 — — —
PC[4] PCR[36] M Tristate 62 92 131 B7
AF3 — — —
— SIN_1 DSPI_1 I
— CAN3RX(11) FlexCAN_3 I
AF0 GPIO[37] SIUL I/O
AF1 SOUT_1 DSPI1 O
PC[5] PCR[37] AF2 CAN3TX(11) FlexCAN_3 O M Tristate 61 91 130 A7
AF3 — — —
— EIRQ[7] SIUL I
AF0 GPIO[38] SIUL I/O
AF1 LIN1TX LINFlex_1 O
PC[6] PCR[38] S Tristate 16 25 36 R2
AF2 — — —
AF3 — — —
AF0 GPIO[39] SIUL I/O
AF1 — — —
AF2 — — —
PC[7] PCR[39] S Tristate 17 26 37 P3
AF3 — — —
— LIN1RX LINFlex_1 I
— WKPU[12](4) WKPU I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[40] SIUL I/O
AF1 LIN2TX LINFlex_2 O
PC[8] PCR[40] S Tristate 63 99 143 A1
AF2 — — —
AF3 — — —
AF0 GPIO[41] SIUL I/O
AF1 — — —
AF2 — — —
PC[9] PCR[41] S Tristate 2 2 2 B1
AF3 — — —
— LIN2RX LINFlex_2 I
— WKPU[13](4) WKPU I
AF0 GPIO[42] SIUL I/O
AF1 CAN1TX FlexCAN_1 O
PC[10] PCR[42] M Tristate 13 22 28 M3
AF2 CAN4TX(11) FlexCAN_4 O
AF3 MA[1] ADC O
AF0 GPIO[43] SIUL I/O
AF1 — — —
AF2 — — —
PC[11] PCR[43] AF3 — — — S Tristate — 21 27 M4
— CAN1RX FlexCAN_1 I
— CAN4RX(11) FlexCAN_4 I
— WKPU[5](4) WKPU I
AF0 GPIO[44] SIUL I/O
AF1 E0UC[12] eMIOS_0 I/O
PC[12] PCR[44] AF2 — — — M Tristate — 97 141 B4
AF3 — — —
— SIN_2 DSPI_2 I
AF0 GPIO[45] SIUL I/O
AF1 E0UC[13] eMIOS_0 I/O
PC[13] PCR[45] S Tristate — 98 142 A2
AF2 SOUT_2 DSPI_2 O
AF3 — — —
AF0 GPIO[46] SIUL I/O
AF1 E0UC[14] eMIOS_0 I/O
PC[14] PCR[46] AF2 SCK_2 DSPI_2 I/O S Tristate — 3 3 C1
AF3 — — —
— EIRQ[8] SIUL I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[47] SIUL I/O
AF1 E0UC[15] eMIOS_0 I/O
PC[15] PCR[47] M Tristate — 4 4 D3
AF2 CS0_2 DSPI_2 I/O
AF3 — — —
AF0 GPIO[48] SIUL I
AF1 — — —
PD[0] PCR[48] AF2 — — — I Tristate — 41 63 P12
AF3 — — —
— GPI[4] ADC I
AF0 GPIO[49] SIUL I
AF1 — — —
PD[1] PCR[49] AF2 — — — I Tristate — 42 64 T12
AF3 — — —
— GPI[5] ADC I
AF0 GPIO[50] SIUL I
AF1 — — —
PD[2] PCR[50] AF2 — — — I Tristate — 43 65 R12
AF3 — — —
— GPI[6] ADC I
AF0 GPIO[51] SIUL I
AF1 — — —
PD[3] PCR[51] AF2 — — — I Tristate — 44 66 P13
AF3 — — —
— GPI[7] ADC I
AF0 GPIO[52] SIUL I
AF1 — — —
PD[4] PCR[52] AF2 — — — I Tristate — 45 67 R13
AF3 — — —
— GPI[8] ADC I
AF0 GPIO[53] SIUL I
AF1 — — —
PD[5] PCR[53] AF2 — — — I Tristate — 46 68 T13
AF3 — — —
— GPI[9] ADC I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[54] SIUL I
AF1 — — —
PD[6] PCR[54] AF2 — — — I Tristate — 47 69 T14
AF3 — — —
— GPI[10] ADC I
AF0 GPIO[55] SIUL I
AF1 — — —
PD[7] PCR[55] AF2 — — — I Tristate — 48 70 R14
AF3 — — —
— GPI[11] ADC I
AF0 GPIO[56] SIUL I
AF1 — — —
PD[8] PCR[56] AF2 — — — I Tristate — 49 71 T15
AF3 — — —
— GPI[12] ADC I
AF0 GPIO[57] SIUL I
AF1 — — —
PD[9] PCR[57] AF2 — — — I Tristate — 56 78 N15
AF3 — — —
— GPI[13] ADC I
AF0 GPIO[58] SIUL I
AF1 — — —
PD[10] PCR[58] AF2 — — — I Tristate — 57 79 N14
AF3 — — —
— GPI[14] ADC I
AF0 GPIO[59] SIUL I
AF1 — — —
PD[11] PCR[59] AF2 — — — I Tristate — 58 80 N16
AF3 — — —
— GPI[15] ADC I
AF0 GPIO[60] SIUL I/O
AF1 CS5_0 DSPI_0 O
PD[12](
8) PCR[60] AF2 E0UC[24] eMIOS_0 I/O J Tristate — 60 82 M15
AF3 — — —
— ANS[4] ADC I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[61] SIUL I/O
AF1 CS0_1 DSPI_1 I/O
PD[13] PCR[61] AF2 E0UC[25] eMIOS_0 I/O J Tristate — 62 84 M14
AF3 — — —
— ANS[5] ADC I
AF0 GPIO[62] SIUL I/O
AF1 CS1_1 DSPI_1 O
PD[14] PCR[62] AF2 E0UC[26] eMIOS_0 I/O J Tristate — 64 86 L15
AF3 — — —
— ANS[6] ADC I
AF0 GPIO[63] SIUL I/O
AF1 CS2_1 DSPI_1 O
PD[15] PCR[63] AF2 E0UC[27] eMIOS_0 I/O J Tristate — 66 88 L14
AF3 — — —
— ANS[7] ADC I
AF0 GPIO[64] SIUL I/O
AF1 E0UC[16] eMIOS_0 I/O
AF2 — — —
PE[0] PCR[64] S Tristate — 6 10 F1
AF3 — — —
— CAN5RX(11) FlexCAN_5 I
— WKPU[6](4) WKPU I
AF0 GPIO[65] SIUL I/O
AF1 E0UC[17] eMIOS_0 I/O
PE[1] PCR[65] M Tristate — 8 12 F4
AF2 CAN5TX(11) FlexCAN_5 O
AF3 — — —
AF0 GPIO[66] SIUL I/O
AF1 E0UC[18] eMIOS_0 I/O
PE[2] PCR[66] AF2 — — — M Tristate — 89 128 D7
AF3 — — —
— SIN_1 DSPI_1 I
AF0 GPIO[67] SIUL I/O
AF1 E0UC[19] eMIOS_0 I/O
PE[3] PCR[67] M Tristate — 90 129 C7
AF2 SOUT_1 DSPI_1 O
AF3 — — —

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[68] SIUL I/O
AF1 E0UC[20] eMIOS_0 I/O
PE[4] PCR[68] AF2 SCK_1 DSPI_1 I/O M Tristate — 93 132 D6
AF3 — — —
— EIRQ[9] SIUL I
AF0 GPIO[69] SIUL I/O
AF1 E0UC[21] eMIOS_0 I/O
PE[5] PCR[69] M Tristate — 94 133 C6
AF2 CS0_1 DSPI_1 I/O
AF3 MA[2] ADC O
AF0 GPIO[70] SIUL I/O
AF1 E0UC[22] eMIOS_0 I/O
PE[6] PCR[70] M Tristate — 95 139 B5
AF2 CS3_0 DSPI_0 O
AF3 MA[1] ADC O
AF0 GPIO[71] SIUL I/O
AF1 E0UC[23] eMIOS_0 I/O
PE[7] PCR[71] M Tristate — 96 140 C4
AF2 CS2_0 DSPI_0 O
AF3 MA[0] ADC O
AF0 GPIO[72] SIUL I/O
AF1 CAN2TX(12) FlexCAN_2 O
PE[8] PCR[72] M Tristate — 9 13 G2
AF2 E0UC[22] eMIOS_0 I/O
AF3 CAN3TX(11) FlexCAN_3 O
AF0 GPIO[73] SIUL I/O
AF1 — — —
AF2 E0UC[23] eMIOS_0 I/O
PE[9] PCR[73] AF3 — — — S Tristate — 10 14 G1
— WKPU[7](4) WKPU I
— CAN2RX(12) FlexCAN_2 I
— CAN3RX(11) FlexCAN_3 I
AF0 GPIO[74] SIUL I/O
AF1 LIN3TX LINFlex_3 O
PE[10] PCR[74] AF2 CS3_1 DSPI_1 O S Tristate — 11 15 G3
AF3 — — —
— EIRQ[10] SIUL I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[75] SIUL I/O
AF1 — — —
AF2 CS4_1 DSPI_1 O
PE[11] PCR[75] S Tristate — 13 17 H2
AF3 — — —
— LIN3RX LINFlex_3 I
— WKPU[14](4) WKPU I
AF0 GPIO[76] SIUL I/O
AF1 — — —
AF2 E1UC[19](13) eMIOS_1 I/O
PE[12] PCR[76] S Tristate — 76 109 C14
AF3 — — —
— SIN_2 DSPI_2 I
— EIRQ[11] SIUL I
AF0 GPIO[77] SIUL I/O
AF1 SOUT2 DSPI_2 O
PE[13] PCR[77] S Tristate — — 103 D15
AF2 E1UC[20] eMIOS_1 I/O
AF3 — — —
AF0 GPIO[78] SIUL I/O
AF1 SCK_2 DSPI_2 I/O
PE[14] PCR[78] AF2 E1UC[21] eMIOS_1 I/O S Tristate — — 112 C13
AF3 — — —
— EIRQ[12] SIUL I
AF0 GPIO[79] SIUL I/O
AF1 CS0_2 DSPI_2 I/O
PE[15] PCR[79] M Tristate — — 113 A13
AF2 E1UC[22] eMIOS_1 I/O
AF3 — — —
AF0 GPIO[80] SIUL I/O
AF1 E0UC[10] eMIOS_0 I/O
PF[0] PCR[80] AF2 CS3_1 DSPI_1 O J Tristate — — 55 N10
AF3 — — —
— ANS[8] ADC I
AF0 GPIO[81] SIUL I/O
AF1 E0UC[11] eMIOS_0 I/O
PF[1] PCR[81] AF2 CS4_1 DSPI_1 O J Tristate — — 56 P10
AF3 — — —
— ANS[9] I I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[82] SIUL I/O
AF1 E0UC[12] eMIOS_0 I/O
PF[2] PCR[82] AF2 CS0_2 DSPI_2 I/O J Tristate — — 57 T10
AF3 — — —
— ANS[10] ADC I
AF0 GPIO[83] SIUL I/O
AF1 E0UC[13] eMIOS_0 I/O
PF[3] PCR[83] AF2 CS1_2 DSPI_2 O J Tristate — — 58 R10
AF3 — — —
— ANS[11] ADC I
AF0 GPIO[84] SIUL I/O
AF1 E0UC[14] eMIOS_0 I/O
PF[4] PCR[84] AF2 CS2_2 DSPI_2 O J Tristate — — 59 N11
AF3 — — —
— ANS[12] ADC I
AF0 GPIO[85] SIUL I/O
AF1 E0UC[22] eMIOS_0 I/O
PF[5] PCR[85] AF2 CS3_2 DSPI_2 O J Tristate — — 60 P11
AF3 — — —
— ANS[13] ADC I
AF0 GPIO[86] SIUL I/O
AF1 E0UC[23] eMIOS_0 I/O
PF[6] PCR[86] AF2 — — — J Tristate — — 61 T11
AF3 — — —
— ANS[14] ADC I
AF0 GPIO[87] SIUL I/O
AF1 — — —
PF[7] PCR[87] AF2 — — — J Tristate — — 62 R11
AF3 — — —
— ANS[15] ADC I
AF0 GPIO[88] SIUL I/O
AF1 CAN3TX(14) FlexCAN_3 O
PF[8] PCR[88] M Tristate — — 34 P1
AF2 CS4_0 DSPI_0 O
AF3 CAN2TX(15) FlexCAN_2 O

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[89] SIUL I/O
AF1 — — —
AF2 CS5_0 DSPI_0 O
PF[9] PCR[89] S Tristate — — 33 N2
AF3 — — —
— CAN2RX(15) FlexCAN_2 I
— CAN3RX(14) FlexCAN_3 I
AF0 GPIO[90] SIUL I/O
AF1 — — —
PF[10] PCR[90] M Tristate — — 38 R3
AF2 — — —
AF3 — — —
AF0 GPIO[91] SIUL I/O
AF1 — — —
PF[11] PCR[91] AF2 — — — S Tristate — — 39 R4
AF3 — — —
— WKPU[15](4) WKPU I
AF0 GPIO[92] SIUL I/O
AF1 E1UC[25] eMIOS_1 I/O
PF[12] PCR[92] M Tristate — — 35 R1
AF2 — — —
AF3 — — —
AF0 GPIO[93] SIUL I/O
AF1 E1UC[26] eMIOS_1 I/O
PF[13] PCR[93] AF2 — — — S Tristate — — 41 T6
AF3 — — —
— WKPU[16](4) WKPU I
AF0 GPIO[94] SIUL I/O
AF1 CAN4TX(11) FlexCAN_4 O
PF[14] PCR[94] M Tristate — — 102 D14
AF2 E1UC[27] eMIOS_1 I/O
AF3 CAN1TX FlexCAN_4 O
AF0 GPIO[95] SIUL I/O
AF1 — — —
AF2 — — —
PF[15] PCR[95] AF3 — — — S Tristate — — 101 E15
— CAN1RX FlexCAN_1 I
— CAN4RX(11) FlexCAN_4 I
— EIRQ[13] SIUL I

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[96] SIUL I/O
AF1 CAN5TX(11) FlexCAN_5 O
PG[0] PCR[96] M Tristate — — 98 E14
AF2 E1UC[23] eMIOS_1 I/O
AF3 — — —
AF0 GPIO[97] SIUL I/O
AF1 — — —
AF2 E1UC[24] eMIOS_1 I/O
PG[1] PCR[97] S Tristate — — 97 E13
AF3 — — —
— CAN5RX(11) FlexCAN_5 I
— EIRQ[14] SIUL I
AF0 GPIO[98] SIUL I/O
AF1 E1UC[11] eMIOS_1 I/O
PG[2] PCR[98] M Tristate — — 8 E4
AF2 — — —
AF3 — — —
AF0 GPIO[99] SIUL I/O
AF1 E1UC[12] eMIOS_1 I/O
PG[3] PCR[99] AF2 — — — S Tristate — — 7 E3
AF3 — — —
— WKPU[17](4) WKPU I
AF0 GPIO[100] SIUL I/O
AF1 E1UC[13] eMIOS_1 I/O
PG[4] PCR[100] M Tristate — — 6 E1
AF2 — — —
AF3 — — —
AF0 GPIO[101] SIUL I/O
AF1 E1UC[14] eMIOS_1 I/O
PG[5] PCR[101] AF2 — — — S Tristate — — 5 E2
AF3 — — —
— WKPU[18](4) WKPU I
AF0 GPIO[102] SIUL I/O
AF1 E1UC[15] eMIOS_1 I/O
PG[6] PCR[102] M Tristate — — 30 M2
AF2 — — —
AF3 — — —

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[103] SIUL I/O
AF1 E1UC[16] eMIOS_1 I/O
PG[7] PCR[103] M Tristate — — 29 M1
AF2 — — —
AF3 — — —
AF0 GPIO[104] SIUL I/O
AF1 E1UC[17] eMIOS_1 I/O
PG[8] PCR[104] AF2 — — — S Tristate — — 26 L2
AF3 CS0_2 DSPI_2 I/O
— EIRQ[15] SIUL I
AF0 GPIO[105] SIUL I/O
AF1 E1UC[18] eMIOS_1 I/O
PG[9] PCR[105] S Tristate — — 25 L1
AF2 — — —
AF3 SCK_2 DSPI_2 I/O
AF0 GPIO[106] SIUL I/O
AF1 E0UC[24] eMIOS_0 I/O
PG[10] PCR[106] S Tristate — — 114 D13
AF2 — — —
AF3 — — —
AF0 GPIO[107] SIUL I/O
AF1 E0UC[25] eMIOS_0 I/O
PG[11] PCR[107] M Tristate — — 115 B12
AF2 — — —
AF3 — — —
AF0 GPIO[108] SIUL I/O
AF1 E0UC[26] eMIOS_0 I/O
PG[12] PCR[108] M Tristate — — 92 K14
AF2 — — —
AF3 — — —
AF0 GPIO[109] SIUL I/O
AF1 E0UC[27] eMIOS_0 I/O
PG[13] PCR[109] M Tristate — — 91 K16
AF2 — — —
AF3 — — —
AF0 GPIO[110] SIUL I/O
AF1 E1UC[0] eMIOS_1 I/O
PG[14] PCR[110] S Tristate — — 110 B14
AF2 — — —
AF3 — — —

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[111] SIUL I/O
AF1 E1UC[1] eMIOS_1 I/O
PG[15] PCR[111] M Tristate — — 111 B13
AF2 — — —
AF3 — — —
AF0 GPIO[112] SIUL I/O
AF1 E1UC[2] eMIOS_1 I/O
PH[0] PCR[112] AF2 — — — M Tristate — — 93 F13
AF3 — — —
— SIN1 DSPI_1 I
AF0 GPIO[113] SIUL I/O
AF1 E1UC[3] eMIOS_1 I/O
PH[1] PCR[113] M Tristate — — 94 F14
AF2 SOUT1 DSPI_1 O
AF3 — — —
AF0 GPIO[114] SIUL I/O
AF1 E1UC[4] eMIOS_1 I/O
PH[2] PCR[114] M Tristate — — 95 F16
AF2 SCK_1 DSPI_1 I/O
AF3 — — —
AF0 GPIO[115] SIUL I/O
AF1 E1UC[5] eMIOS_1 I/O
PH[3] PCR[115] M Tristate — — 96 F15
AF2 CS0_1 DSPI_1 I/O
AF3 — — —
AF0 GPIO[116] SIUL I/O
AF1 E1UC[6] eMIOS_1 I/O
PH[4] PCR[116] M Tristate — — 134 A6
AF2 — — —
AF3 — — —
AF0 GPIO[117] SIUL I/O
AF1 E1UC[7] eMIOS_1 I/O
PH[5] PCR[117] S Tristate — — 135 B6
AF2 — — —
AF3 — — —
AF0 GPIO[118] SIUL I/O
AF1 E1UC[8] eMIOS_1 I/O
PH[6] PCR[118] M Tristate — — 136 D5
AF2 — — —
AF3 MA[2] ADC O

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Table 6. Functional port pin descriptions (continued)

Pin number

I/O direction(2)

configuration
function(1)

Peripheral
Alternate

Function

Pad type
Port pin

RESET

LBGA208(3)
PCR

LQFP100

LQFP144
LQFP64
AF0 GPIO[119] SIUL I/O
AF1 E1UC[9] eMIOS_1 I/O
PH[7] PCR[119] M Tristate — — 137 C5
AF2 CS3_2 DSPI_2 O
AF3 MA[1] ADC O
AF0 GPIO[120] SIUL I/O
AF1 E1UC[10] eMIOS_1 I/O
PH[8] PCR[120] M Tristate — — 138 A5
AF2 CS2_2 DSPI_2 O
AF3 MA[0] ADC O
AF0 GPIO[121] SIUL I/O
AF1 — — — Input, weak
PH[9](9) PCR[121] S 60 88 127 B8
AF2 TCK JTAGC I pull-up
AF3 — — —
AF0 GPIO[122] SIUL I/O
PH[10]( AF1 — — — Input, weak
9) PCR[122] S 53 81 120 B9
AF2 TMS JTAGC I pull-up
AF3 — — —
1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00  AF0;
PCR.PA = 01  AF1; PCR.PA = 10  AF2; PCR.PA = 11  AF3. This is intended to select the output functions; to use
one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields.
For this reason, the value corresponding to an input only function is reported as “—”.
2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
3. LBGA208 available only as development package for Nexus2+
4. All WKPU pins also support external interrupt capability. See wakeup unit chapter for further details.
5. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
6. “Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the
reference manual for details.
7. Value of PCR.IBE bit must be 0
8. Be aware that this pad is used on the SPC560B64L3 and SPC560B64L5 to provide VDD_HV_ADC and VSS_HV_ADC1.
Therefore, you should be careful in ensuring compatibility between SPC560B40x/50x and SPC560C40x/50x and
SPC560B64.
9. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001.
10. The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY
mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an
input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra
consumption TDO must be connected. An external pull-up resistor in the range of 47–100 k should be added between the
TDO pin and VDD_HV. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down
resistor with the same value should be used between TDO pin and GND instead.

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11. Available only on SPC560Cx versions and SPC560B50B2 devices

12. Not available on SPC560B40L3 and SPC560B40L5 devices
13. Not available in 100 LQFP package
14. Available only on SPC560B50B2 devices
15. Not available on SPC560B44L3 devices

3.7 Nexus 2+ pins

In the LBGA208 package, eight additional debug pins are available (see Table 7).

Table 7. Nexus 2+ pin descriptions

Pin number
I/O Function
Debug pin Function Pad type
direction after reset LQFP LQFP LBGA
100 144 208(1)

MCKO Message clock out O F — — — T4

MDO0 Message data out 0 O M — — — H15
MDO1 Message data out 1 O M — — — H16
MDO2 Message data out 2 O M — — — H14
MDO3 Message data out 3 O M — — — H13
EVTI Event in I M Pull-up — — K1
EVTO Event out O M — — — L4
MSEO Message start/end out O M — — — G16
1. LBGA208 available only as development package for Nexus2+.

3.8 Electrical characteristics

3.9 Introduction
This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid applying any voltage higher
than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This could be done by the internal pull-up and pull-down, which is provided by the
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.

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In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.
Caution: All LQFP64 information is indicative and must be confirmed during silicon validation.

3.10 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 8 are used and
the parameters are tagged accordingly in the tables where appropriate.

Table 8. Parameter classifications

Classification tag Tag description

P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
C
relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical
T devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D Those parameters are derived mainly from simulations.

Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.

3.11 NVUSRO register

Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the
device configuration, namely electrical parameters such as high voltage supply and
oscillator margin, as well as digital functionality (watchdog enable/disable after reset).
For a detailed description of the NVUSRO register, please refer to the device reference
manual.

3.11.1 NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 9 shows
how NVUSRO[PAD3V5V] controls the device configuration.

Table 9. PAD3V5V field description

(1)
Value Description

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V
1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

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3.11.2 NVUSRO[OSCILLATOR_MARGIN] field description

The fast external crystal oscillator consumption is dependent on the
OSCILLATOR_MARGIN bit value. Table 10 shows how NVUSRO[OSCILLATOR_MARGIN]
controls the device configuration.

Table 10. OSCILLATOR_MARGIN field description

(1)
Value Description

0 Low consumption configuration (4 MHz/8 MHz)

1 High margin configuration (4 MHz/16 MHz)
1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

3.11.3 NVUSRO[WATCHDOG_EN] field description

The watchdog enable/disable configuration after reset is dependent on the
WATCHDOG_EN bit value. Table 11 shows how NVUSRO[WATCHDOG_EN] controls the
device configuration.

Table 11. WATCHDOG_EN field description

Value(1) Description

0 Disable after reset

1 Enable after reset
1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

3.12 Absolute maximum ratings

Table 12. Absolute maximum ratings
Value
Symbol Parameter Conditions Unit
Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

Voltage on VDD_HV pins with respect
VDD SR — 0.3 6.0 V
to ground (VSS)
Voltage on VSS_LV (low voltage digital
VSS_LV SR supply) pins with respect to ground — VSS0.1 VSS+0.1 V
(VSS)

Voltage on VDD_BV pin (regulator — 0.3 6.0

VDD_BV SR V
supply) with respect to ground (VSS) Relative to VDD 0.3 VDD+0.3
Voltage on VSS_HV_ADC (ADC
VSS_ADC SR reference) pin with respect to ground — VSS0.1 VSS+0.1 V
(VSS)

Voltage on VDD_HV_ADC pin (ADC — 0.3 6.0

VDD_ADC SR V
reference) with respect to ground (VSS) Relative to V VDD 0.3 VDD+0.3
DD

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Table 12. Absolute maximum ratings (continued)

Value
Symbol Parameter Conditions Unit
Min Max

Voltage on any GPIO pin with respect to — 0.3 6.0

VIN SR V
ground (VSS) Relative to VDD — VDD+0.3
Injected input current on any pin during
IINJPAD SR — 10 10
overload condition
mA
Absolute sum of all injected input
IINJSUM SR — 50 50
currents during overload condition
VDD = 5.0 V ± 10%,
— 70
Sum of all the static I/O current within a PAD3V5V = 0
IAVGSEG SR mA
supply segment V = 3.3 V ± 10%,
DD — 64
PAD3V5V = 1
Low voltage static current sink through
ICORELV SR — — 150 mA
VDD_BV
TSTORAGE SR Storage temperature — 55 150 °C

Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS),
the voltage on pins with respect to ground (VSS) must not exceed the recommended values.

3.13 Recommended operating conditions

Table 13. Recommended operating conditions (3.3 V)
Value
Symbol Parameter Conditions Unit
Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

Voltage on VDD_HV pins with respect to ground
VDD(1) SR — 3.0 3.6 V
(VSS)
Voltage on VSS_LV (low voltage digital supply)
VSS_LV(2) SR — VSS0.1 VSS+0.1 V
pins with respect to ground (VSS)

Voltage on VDD_BV pin (regulator supply) with — 3.0 3.6

VDD_BV(3) SR V
respect to ground (VSS) Relative to VDD VDD0.1 VDD+0.1
Voltage on VSS_HV_ADC (ADC reference) pin
VSS_ADC SR — VSS0.1 VSS+0.1 V
with respect to ground (VSS)

Voltage on VDD_HV_ADC pin (ADC reference) — 3.0(5) 3.6

VDD_ADC(4) SR V
with respect to ground (VSS) Relative to VDD VDD0.1 VDD+0.1

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Table 13. Recommended operating conditions (3.3 V) (continued)

Value
Symbol Parameter Conditions Unit
Min Max

Voltage on any GPIO pin with respect to ground — VSS0.1 —

VIN SR V
(VSS) Relative to VDD — VDD+0.1
Injected input current on any pin during overload
IINJPAD SR — 5 5
condition
mA
Absolute sum of all injected input currents
IINJSUM SR — 50 50
during overload condition
250 x 103
TVDD SR VDD slope to ensure correct power up(6) — 3.0(7) (0.25 V/s
[V/µs])
1. 100 nF capacitance needs to be provided between each VDD/VSS pair
2. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
3. 400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is
reset.
6. Guaranteed by device validation.
7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).

Table 14. Recommended operating conditions (5.0 V)

Value
Symbol Parameter Conditions Unit
Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

Voltage on VDD_HV pins with respect to — 4.5 5.5

VDD(1) SR V
ground (VSS) Voltage drop (2) 3.0 5.5
Voltage on VSS_LV (low voltage digital
VSS_LV(3) SR — VSS0.1 VSS+0.1 V
supply) pins with respect to ground (VSS)
— 4.5 5.5
Voltage on VDD_BV pin (regulator supply)
VDD_BV(4) SR Voltage drop(2) 3.0 5.5 V
with respect to ground (VSS)
Relative to VDD VDD0.1 VDD+0.1
Voltage on VSS_HV_ADC (ADC reference)
VSS_ADC SR — VSS0.1 VSS+0.1 V
pin with respect to ground (VSS
— 4.5 5.5
Voltage on VDD_HV_ADC pin (ADC
VDD_ADC(5) SR Voltage drop (2) 3.0 5.5 V
reference) with respect to ground (VSS)
Relative to VDD VDD0.1 VDD+0.1

Voltage on any GPIO pin with respect to — VSS0.1 —

VIN SR V
ground (VSS) Relative to VDD — VDD+0.1

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Table 14. Recommended operating conditions (5.0 V) (continued)

Value
Symbol Parameter Conditions Unit
Min Max

Injected input current on any pin during

IINJPAD SR — 5 5
overload condition
mA
Absolute sum of all injected input currents
IINJSUM SR — 50 50
during overload condition
250 x 103
(6) (7) V/s
TVDD SR VDD slope to ensure correct power up — 3.0 (0.25
[V/µs])
1. 100 nF capacitance needs to be provided between each VDD/VSS pair.
2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog
electrical characteristics will not be guaranteed to stay within the stated limits.
3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4. 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5. 1 µF (electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Another
ceramic cap of 10 nF with low inductance package can be added.
6. Guaranteed by device validation.
7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).

Note: RAM data retention is guaranteed with VDD_LV not below 1.08 V.

3.14 Thermal characteristics

3.14.1 Package thermal characteristics

Table 15. LQFP thermal characteristics(1)

Symbol C Parameter Conditions(2) Pin count Value Unit

64 60
Single-layer board - 1s 100 64

Thermal resistance, junction-to- 144 64

RJA CC D °C/W
ambient natural convection(3) 64 42
Four-layer board - 2s2p 100 51
144 49
64 24
Single-layer board - 1s 100 36

Thermal resistance, junction-to- 144 37

RJB CC D °C/W
board(4) 64 24
Four-layer board - 2s2p 100 34
144 35

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Table 15. LQFP thermal characteristics(1) (continued)

Symbol C Parameter Conditions(2) Pin count Value Unit

64 11
Single-layer board - 1s 100 22

Thermal resistance, junction-to- 144 22

RJC CC D °C/W
case(5) 64 11
Four-layer board - 2s2p 100 22
144 22
64 TBD
Single-layer board - 1s 100 33
Junction-to-board thermal 144 34
JB CC D characterization parameter, natural °C/W
convection 64 TBD
Four-layer board - 2s2p 100 34
144 35
64 TBD
Single-layer board - 1s 100 9
Junction-to-case thermal 144 10
JC CC D characterization parameter, natural °C/W
convection 64 TBD
Four-layer board - 2s2p 100 9
144 10
1. Thermal characteristics are based on simulation.
2. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C
3. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
4. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package.
5. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.

3.14.2 Power considerations

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using
Equation 1:

Equation 1TJ = TA + (PD x RJA)

Where:
TA is the ambient temperature in °C.
RJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal
power.
PI/O represents the power dissipation on input and output pins; user determined.

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Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand,
PI/O may be significant, if the device is configured to continuously drive external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:

Equation 2 PD = K / (TJ + 273 °C)

Therefore, solving equations Equation 1 and Equation 2:

Equation 3 K = PD x (TA + 273 °C) + RJA x PD2

Where:
K is a constant for the particular part, which may be determined from Equation 3
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values
of PD and TJ may be obtained by solving equations Equation 1 and Equation 2
iteratively for any value of TA.

3.15 I/O pad electrical characteristics

3.15.1 I/O pad types

The device provides four main I/O pad types depending on the associated alternate
functions:
 Slow pads—These pads are the most common pads, providing a good compromise
between transition time and low electromagnetic emission.
 Medium pads—These pads provide transition fast enough for the serial communication
channels with controlled current to reduce electromagnetic emission.
 Fast pads—These pads provide maximum speed. There are used for improved Nexus
debugging capability.
 Input only pads—These pads are associated to ADC channels and the external 32 kHz
crystal oscillator (SXOSC) providing low input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.

3.15.2 I/O input DC characteristics

Table 16 provides input DC electrical characteristics as described in Figure 6.

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Figure 6. I/O input DC electrical characteristics definition

VIN
VDD

VIH

VHYS

VIL

PDIx = ‘1’
(GPDI register of SIUL)

PDIx = ‘0’

Table 16. I/O input DC electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Input high level CMOS

VIH SR P — 0.65VDD — VDD+0.4
(Schmitt Trigger)
Input low level CMOS
VIL SR P — 0.4 — 0.35VDD V
(Schmitt Trigger)
Input hysteresis CMOS
VHYS CC C — 0.1VDD — —
(Schmitt Trigger)
D TA = 40 °C — 2 200
D TA = 25 °C — 2 200
No injection
ILKG CC D Digital input leakage on adjacent TA = 85 °C — 5 300 nA
pin
D TA = 105 °C — 12 500
P TA = 125 °C — 70 1000
WFI(2) SR P Wakeup input filtered pulse — — — 40 ns
Wakeup input not filtered
WNFI(2) SR P — 1000 — — ns
pulse
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.

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3.15.3 I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:
 Table 17 provides weak pull figures. Both pull-up and pull-down resistances are
supported.
 Table 18 provides output driver characteristics for I/O pads when in SLOW
configuration.
 Table 19 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
 Table 20 provides output driver characteristics for I/O pads when in FAST
configuration.

Table 17. I/O pull-up/pull-down DC electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

P PAD3V5V = 0 10 — 150
C Weak pull-up current VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V =
|IWPU| C 10 — 250 µA
C absolute value 1(2)
P VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150
P PAD3V5V = 0 10 — 150
C Weak pull-down current VIN = VIH, VDD = 5.0 V ± 10%
|IWPD| C PAD3V5V = 1 10 — 250 µA
C absolute value
P VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 18. SLOW configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

IOH = 2 mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — —
(recommended)
IOH = 2 mA,
Output high level
VOH CC C Push Pull VDD = 5.0 V ± 10%, PAD3V5V = 0.8VDD — — V
SLOW configuration
1(2)
IOH = 1 mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD0.8 — —
(recommended)

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Table 18. SLOW configuration output buffer electrical characteristics (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

IOL = 2 mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD
(recommended)
IOL = 2 mA,
Output low level
VOL CC C Push Pull VDD = 5.0 V ± 10%, PAD3V5V = — — 0.1VDD V
SLOW configuration
1(2)
IOL = 1 mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5
(recommended)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 19. MEDIUM configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

IOH = 3.8 mA,

C 0.8VDD — —
VDD = 5.0 V ± 10%, PAD3V5V = 0
IOH = 2 mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — —
(recommended)
Output high level I = 1 mA,
VOH CC C Push Pull OH 0.8VDD — — V
MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOH = 1 mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD0.8 — —
(recommended)
IOH = 100 µA,
C 0.8VDD — —
VDD = 5.0 V ± 10%, PAD3V5V = 0
IOL = 3.8 mA,
C — — 0.2VDD
VDD = 5.0 V ± 10%, PAD3V5V = 0
IOL = 2 mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD
(recommended)
Output low level I = 1 mA,
VOL CC C Push Pull OL — — 0.1VDD V
MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOL = 1 mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5
(recommended)
IOL = 100 µA,
C — — 0.1VDD
VDD = 5.0 V ± 10%, PAD3V5V = 0
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

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2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 20. FAST configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

IOH = 14mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — —
(recommended)
Output high level I = 7mA,
VOH CC C Push Pull OH 0.8VDD — — V
FAST configuration VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOH = 11mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD0.8 — —
(recommended)
IOL = 14mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD
(recommended)
Output low level I = 7mA,
VOL CC C Push Pull OL — — 0.1VDD V
FAST configuration VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOL = 11mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5
(recommended)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

3.15.4 Output pin transition times

Table 21. Output pin transition times

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

D CL = 25 pF — — 50
T CL = 50 pF — — 100
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL =
D Output transition time output — — 125
100 pF
ttr CC pin(2) ns
D SLOW configuration CL = 25 pF — — 50
T CL = 50 pF — — 100
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL =
D — — 125
100 pF

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Table 21. Output pin transition times (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

D CL = 25 pF — — 10
T CL = 50 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 20
SIUL.PCRx.SRC = 1
CL =
D Output transition time output — — 40
100 pF
ttr CC pin(2) ns
D MEDIUM configuration CL = 25 pF — — 12
T CL = 50 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 25
SIUL.PCRx.SRC = 1
CL =
D — — 40
100 pF
CL = 25 pF — — 4
CL = 50 pF — — 6
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL =
Output transition time output — — 12
100 pF
ttr CC D pin(2) ns
FAST configuration CL = 25 pF — — 4
CL = 50 pF — — 7
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL =
— — 12
100 pF
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. CL includes device and package capacitances (CPKG < 5 pF).

3.15.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in Table 22.

Table 22. I/O supply segment

Supply segment
Package
1 2 3 4 5 6

LBGA208(1) Equivalent to LQFP144 segment pad distribution MCKO MDOn/MSEO

LQFP144 pin20–pin49 pin51–pin99 pin100–pin122 pin 123–pin19 — —
LQFP100 pin16–pin35 pin37–pin69 pin70–pin83 pin 84–pin15 — —
LQFP64(2) pin8–pin26 pin28–pin55 pin56–pin7 — — —
1. LBGA208 available only as development package for Nexus2+
2. All LQFP64 information is indicative and must be confirmed during silicon validation.

Table 23 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IAVGSEG maximum value.

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Table 23. I/O consumption

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

VDD = 5.0 V ± 10%,

— — 20
ISWTSLW Dynamic I/O current for PAD3V5V = 0
(2) CC D CL = 25 pF mA
SLOW configuration VDD = 3.3 V ± 10%,
— — 16
PAD3V5V = 1
VDD = 5.0 V ± 10%,
— — 29
ISWTMED (2
Dynamic I/O current for PAD3V5V = 0
) CC D CL = 25 pF mA
MEDIUM configuration VDD = 3.3 V ± 10%,
— — 17
PAD3V5V = 1
VDD = 5.0 V ± 10%,
— — 110
Dynamic I/O current for PAD3V5V = 0
(2)
ISWTFST CC D CL = 25 pF mA
FAST configuration VDD = 3.3 V ± 10%,
— — 50
PAD3V5V = 1
CL = 25 pF, 2 MHz — — 2.3
VDD = 5.0 V ± 10%,
CL = 25 pF, 4 MHz — — 3.2
PAD3V5V = 0
Root mean square I/O CL = 100 pF, 2 MHz — — 6.6
IRMSSLW CC D current for SLOW mA
configuration CL = 25 pF, 2 MHz — — 1.6
VDD = 3.3 V ± 10%,
CL = 25 pF, 4 MHz — — 2.3
PAD3V5V = 1
CL = 100 pF, 2 MHz — — 4.7
CL = 25 pF, 13 MHz — — 6.6
VDD = 5.0 V ± 10%,
CL = 25 pF, 40 MHz — — 13.4
PAD3V5V = 0
Root mean square I/O CL = 100 pF, 13 MHz — — 18.3
IRMSMED CC D current for MEDIUM mA
configuration CL = 25 pF, 13 MHz — — 5
VDD = 3.3 V ± 10%,
CL = 25 pF, 40 MHz — — 8.5
PAD3V5V = 1
CL = 100 pF, 13 MHz — — 11
CL = 25 pF, 40 MHz — — 22
VDD = 5.0 V ± 10%,
CL = 25 pF, 64 MHz — — 33
PAD3V5V = 0
Root mean square I/O CL = 100 pF, 40 MHz — — 56
IRMSFST CC D current for FAST mA
configuration CL = 25 pF, 40 MHz — — 14
VDD = 3.3 V ± 10%,
CL = 25 pF, 64 MHz — — 20
PAD3V5V = 1
CL = 100 pF, 40 MHz — — 35
Sum of all the static I/O VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70
IAVGSEG SR D current within a supply mA
segment VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

Table 24 provides the weight of concurrent switching I/Os.

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Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on
a single segment must not exceed 100% to ensure device functionality.

Table 24. I/O weight(1)

LQFP144/LQFP100 LQFP64(2)
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(3) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
144 100 64 0

PB[3] 10% — 12% — 10% — 12% —

3
PC[9] 10% — 12% — 10% — 12% —
4
— PC[14] 9% — 11% — — — — —
4 — PC[15] 9% 13% 11% 12% — — — —
— — PG[5] 9% — 11% — — — — —
— — PG[4] 9% 12% 10% 11% — — — —
— — PG[3] 9% — 10% — — — — —
— — PG[2] 8% 12% 10% 10% — — — —
3 PA[2] 8% — 9% — 8% — 9% —
— PE[0] 8% — 9% — — — — —
3 PA[1] 7% — 9% — 7% — 9% —
— PE[1] 7% 10% 8% 9% — — — —
4
4 — PE[8] 7% 9% 8% 8% — — — —
— PE[9] 6% — 7% — — — — —
— PE[10] 6% — 7% — — — — —
3 PA[0] 5% 8% 6% 7% 5% 8% 6% 7%
— PE[11] 5% — 6% — — — — —

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Table 24. I/O weight(1) (continued)

LQFP144/LQFP100 LQFP64(2)
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(3) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
144 100 64 0

— — PG[9] 9% — 10% — — — — —
— — PG[8] 9% — 11% — — — — —
— PC[11] 9% — 11% — — — — —
1
1 PC[10] 9% 13% 11% 12% 9% 13% 11% 12%
— — PG[7] 10% 14% 11% 12% — — — —
— — PG[6] 10% 14% 12% 12% — — — —
PB[0] 10% 14% 12% 12% 10% 14% 12% 12%
1 1
PB[1] 10% — 12% — 10% — 12% —
— — PF[9] 10% — 12% — — — — —
— — PF[8] 10% 15% 12% 13% — — — —
1 — — PF[12] 10% 15% 12% 13% — — — —
PC[6] 10% — 12% — 10% — 12% —
1 1
PC[7] 10% — 12% — 10% — 12% —
— — PF[10] 10% 14% 12% 12% — — — —
— — PF[11] 10% — 11% — — — — —
1 1 PA[15] 9% 12% 10% 11% 9% 12% 10% 11%
— — PF[13] 8% — 10% — — — — —
PA[14] 8% 11% 9% 10% 8% 11% 9% 10%
PA[4] 8% — 9% — 8% — 9% —
1 1
PA[13] 7% 10% 9% 9% 7% 10% 9% 9%
PA[12] 7% — 8% — 7% — 8% —

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Table 24. I/O weight(1) (continued)

LQFP144/LQFP100 LQFP64(2)
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(3) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
144 100 64 0

PB[9] 1% — 1% — 1% — 1% —
2 2 PB[8] 1% — 1% — 1% — 1% —
PB[10] 6% — 7% — 6% — 7% —
— — PF[0] 6% — 7% — — — — —
— — PF[1] 7% — 8% — — — — —
— — PF[2] 7% — 8% — — — — —
— — PF[3] 7% — 9% — — — — —
— — PF[4] 8% — 9% — — — — —
— — PF[5] 8% — 10% — — — — —
— — PF[6] 8% — 10% — — — — —
— — PF[7] 9% — 10% — — — — —
— PD[0] 1% — 1% — — — — —
— PD[1] 1% — 1% — — — — —
— PD[2] 1% — 1% — — — — —
— PD[3] 1% — 1% — — — — —
2 — PD[4] 1% — 1% — — — — —
— PD[5] 1% — 1% — — — — —
— PD[6] 1% — 1% — — — — —
— PD[7] 1% — 1% — — — — —
— PD[8] 1% — 1% — — — — —
PB[4] 1% — 1% — 1% — 1% —
2
PB[5] 1% — 1% — 1% — 2% —
2
PB[6] 1% — 1% — 1% — 2% —
PB[7] 1% — 1% — 1% — 2% —
— PD[9] 1% — 1% — — — — —
— PD[10] 1% — 1% — — — — —
— PD[11] 1% — 1% — — — — —
2 PB[11] 11% — 13% — 17% — 21% —
— PD[12] 11% — 13% — — — — —
2 PB[12] 11% — 13% — 18% — 21% —
— PD[13] 10% — 12% — — — — —

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Table 24. I/O weight(1) (continued)

LQFP144/LQFP100 LQFP64(2)
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(3) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
144 100 64 0

2 PB[13] 10% — 12% — 18% — 21% —

— PD[14] 10% — 12% — — — — —
2 PB[14] 10% — 12% — 18% — 21% —
2
— PD[15] 10% — 11% — — — — —
PB[15] 9% — 11% — 18% — 21% —
2
PA[3] 9% — 11% — 18% — 21% —
— — PG[13] 9% 13% 10% 11% — — — —
2
— — PG[12] 9% 12% 10% 11% — — — —
— — PH[0] 5% 8% 6% 7% — — — —
— — PH[1] 5% 7% 6% 6% — — — —
— — PH[2] 5% 6% 5% 6% — — — —
— — PH[3] 4% 6% 5% 5% — — — —
— — PG[1] 4% — 4% — — — — —
— — PG[0] 3% 4% 4% 4% — — — —
— — PF[15] 3% — 4% — — — — —
— — PF[14] 4% 5% 5% 5% — — — —
— — PE[13] 4% — 5% — — — — —
PA[7] 5% — 6% — 16% — 19% —
PA[8] 5% — 6% — 16% — 19% —
2 PA[9] 5% — 6% — 15% — 18% —
3
PA[10] 6% — 7% — 15% — 18% —
PA[11] 6% — 8% — 14% — 17% —
3 — PE[12] 7% — 8% — — — — —
— — PG[14] 7% — 8% — — — — —
— — PG[15] 7% 10% 8% 9% — — — —
— — PE[14] 7% — 8% — — — — —
— — PE[15] 7% 9% 8% 8% — — — —
— — PG[10] 6% — 8% — — — — —
— — PG[11] 6% 9% 7% 8% — — — —
PC[3] 6% — 7% — 7% — 9% —
3 2
PC[2] 6% 8% 7% 7% 6% 9% 8% 8%

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Table 24. I/O weight(1) (continued)

LQFP144/LQFP100 LQFP64(2)
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(3) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
144 100 64 0

PA[5] 5% 7% 6% 6% 6% 8% 7% 7%
PA[6] 5% — 6% — 5% — 6% —
3 3 2
PH[10] 4% 6% 5% 5% 5% 7% 6% 6%
PC[1] 5% — 5% — 5% — 5% —
PC[0] 6% 9% 7% 8% 6% 9% 7% 8%
3
PH[9] 7 7 8 8 7 7 8 8
— PE[2] 7% 10% 9% 9% — — — —
— PE[3] 8% 11% 9% 9% — — — —
4
PC[5] 8% 11% 9% 10% 8% 11% 9% 10%
3
PC[4] 8% 12% 10% 10% 8% 12% 10% 10%
— PE[4] 8% 12% 10% 11% — — — —
— PE[5] 9% 12% 10% 11% — — — —
— — PH[4] 9% 13% 11% 11% — — — —
4 — — PH[5] 9% — 11% — — — — —
— — PH[6] 9% 13% 11% 12% — — — —
— — PH[7] 9% 13% 11% 12% — — — —
— — PH[8] 10% 14% 11% 12% — — — —
— PE[6] 10% 14% 12% 12% — — — —
— PE[7] 10% 14% 12% 12% — — — —
— PC[12] 10% 14% 12% 13% — — — —
4
— PC[13] 10% — 12% — — — — —
PC[8] 10% — 12% — 10% — 12% —
3
PB[2] 10% 15% 12% 13% 10% 15% 12% 13%
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified
2. All LQFP64 information is indicative and must be confirmed during silicon validation.
3. SRC: “Slew Rate Control” bit in SIU_PCR

3.16 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

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Figure 7. Start-up reset requirements

VDD

VDDMIN

RESET

VIH

VIL

device reset forced by RESET device start-up phase

Figure 8. Noise filtering on reset signal

VRESET

hw_rst
VDD
‘1’

VIH

VIL

‘0’
filtered by filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset

WFRST WFRST
WNFRST

Table 25. Reset electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Input High Level CMOS

VIH SR P — 0.65VDD — VDD+0.4 V
(Schmitt Trigger)
Input low Level CMOS
VIL SR P — 0.4 — 0.35VDD V
(Schmitt Trigger)

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Table 25. Reset electrical characteristics (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Input hysteresis CMOS

VHYS CC C — 0.1VDD — — V
(Schmitt Trigger)
Push Pull, IOL = 2mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD
(recommended)
Push Pull, IOL = 1mA,
VOL CC C Output low level — — 0.1VDD V
VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
Push Pull, IOL = 1mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5
(recommended)
CL = 25pF,
— — 10
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 50pF,
— — 20
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 100pF,
— — 40
Output transition time VDD = 5.0 V ± 10%, PAD3V5V = 0
ttr CC D ns
output pin(3) CL = 25pF,
— — 12
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 50pF,
— — 25
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 100pF,
— — 40
VDD = 3.3 V ± 10%, PAD3V5V = 1
RESET input filtered
WFRST SR P — — — 40 ns
pulse
RESET input not filtered
WNFRST SR P — 1000 — — ns
pulse
P VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150
Weak pull-up current
|IWPU| CC D VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150 µA
absolute value
P VDD = 5.0 V ± 10%, PAD3V5V = 1(2) 10 — 250
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. This transient configuration does not occurs when device is used in the VDD = 3.3 V ± 10% range.
3. CL includes device and package capacitance (CPKG < 5 pF).

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3.17 Power management electrical characteristics

3.17.1 Voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the
common I/O supply VDD. The following supplies are involved:
 HV—High voltage external power supply for voltage regulator module. This must be
provided externally through VDD_HV power pin.
 BV—High voltage external power supply for internal ballast module. This must be
provided externally through VDD_BV power pin. Voltage values should be aligned with
VDD.
 LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is
generated by the internal voltage regulator but provided outside to connect stability
capacitor. It is further split into four main domains to ensure noise isolation between
critical LV modules within the device:
– LV_COR—Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
– LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.

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Figure 9. Voltage regulator capacitance connection

CREG2 (LV_COR/LV_CFLA)

VDD_HV

VSS_LV VDD_LV
VDD_BV

VREF
VDD_BV

CDEC1 (Ballast decoupling)

CREG1 (LV_COR/LV_DFLA)
VDD_LV
VDD_LVn
DEVICE

Voltage Regulator

I
VSS_LV
VSS_LVn
VSS_LV VDD_LV VSS_HV VDD_HV
DEVICE

CREG3 CDEC2
(LV_COR/LV_PLL) (supply/IO decoupling)

The internal voltage regulator requires external capacitance (CREGn) to be connected to the
device in order to provide a stable low voltage digital supply to the device. Capacitances
should be placed on the board as near as possible to the associated pins. Care should also
be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply
pairs to ensure stable voltage (see Section 3.13: Recommended operating conditions).
The internal voltage regulator requires a controlled slew rate of both VDD_HV and VDD_BV as
described in Figure 10.

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Figure 10. VDD_HV and VDD_BV maximum slope

VDD_HV

VDD_HV(MAX)

d
VDD
dt
VPORH(MAX)

POWER UP FUNCTIONAL RANGE POWER DOWN

When STANDBY mode is used, further constraints are applied to the both VDD_HV and
VDD_BV in order to guarantee correct regulator function during STANDBY exit. This is
described on Figure 11.
STANDBY regulator constraints should normally be guaranteed by implementing equivalent
of CSTDBY capacitance on application board (capacitance and ESR typical values), but
would actually depend on exact characteristics of application external regulator.

Figure 11. VDD_HV and VDD_BV supply constraints during STANDBY mode exit

VDD_HV VDD_HV

VDD_HV(MAX)

d VDD  STDBY 
VDD(STDBY) dt

VDD(STDBY)

VDD_HV(MIN)
d VDD  STDBY 
dt

VDD_LV

VDD_LV(NOMINAL)

0V

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Table 26. Voltage regulator electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Internal voltage regulator external

CREGn SR — — 200 — 500 nF
capacitance

Stability capacitor equivalent serial Range:

RREG SR — — — 0.2 W
resistance 10 kHz to 20 MHz
VDD_BV/VSS_LV pair: 100
(3) —
VDD_BV = 4.5 V to 5.5 V
(2) (4)
CDEC1 SR — Decoupling capacitance ballast 470 nF
VDD_BV/VSS_LV pair:
400 —
VDD_BV = 3 V to 3.6 V
Decoupling capacitance regulator
CDEC2 SR — VDD/VSS pair 10 100 — nF
supply

d VDD SR — Maximum slope on VDD — — 250 mV/µs

dt
Maximum instant variation on VDD
VDD(STDBY)| SR — — — 30 mV
during standby exit

Maximum slope on VDD during

d VDD  STDBY  SR — — — 15 mV/µs
standby exit
dt

Before exiting from

T — 1.32 —
VMREG CC Main regulator output voltage reset V
P After trimming 1.16 1.28 —
Main regulator current provided to
IMREG SR — — — — 150 mA
VDD_LV domain

Main regulator module current IMREG = 200 mA — — 2

IMREGINT CC D mA
consumption IMREG = 0 mA — — 1
Low power regulator output
VLPREG CC P After trimming 1.16 1.28 — V
voltage
Low power regulator current
ILPREG SR — — — — 15 mA
provided to VDD_LV domain
ILPREG = 15 mA;
D — — 600
Low power regulator module TA = 55 °C
ILPREGINT CC µA
current consumption ILPREG = 0 mA;
— — 5 —
TA = 55 °C
Ultra low power regulator output
VULPREG CC P After trimming 1.16 1.28 — V
voltage

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Table 26. Voltage regulator electrical characteristics (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Ultra low power regulator current

IULPREG SR — — — — 5 mA
provided to VDD_LV domain
IULPREG = 5 mA;
— — 100
Ultra low power regulator module TA = 55 °C
IULPREGINT CC D µA
current consumption IULPREG = 0 mA;
— 2 —
TA = 55 °C
In-rush average current on 300
IDD_BV CC D — — — mA
VDD_BV during power-up(5) (6)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical
value is in the range of 470 nF.
3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V
4. External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in
operating range.
5. In-rush average current is seen only for short time (maximum 20 µs) during power-up and on standby exit. It is dependant
on the sum of the CREGn capacitances.
6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized
accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.

The VDD(STDBY)| and dVDD(STDBY)/dt system requirement can be used to define the
component used for the VDD supply generation. The following two examples describe how
to calculate capacitance size:

Example 1 No regulator (worst case)

The VDD(STDBY)| parameter can be seen as the VDD voltage drop through the ESR
resistance of the regulator stability capacitor when the IDD_BV current required to load
VDD_LV domain during the standby exit. It is thus possible to define the maximum equivalent
resistance ESRSTDBY(MAX) of the total capacitance on the VDD supply:
ESRSTDBY(MAX) = VDD(STDBY)|/IDD_BV = (30 mV)/(300 mA) = 0.1 (d)
The dVDD(STDBY)/dt parameter can be seen as the VDD voltage drop at the capacitance
pin (excluding ESR drop) while providing the IDD_BV supply required to load VDD_LV domain
during the standby exit. It is thus possible to define the minimum equivalent capacitance
CSTDBY(MIN) of the total capacitance on the VDD supply:
CSTDBY(MIN) = IDD_BV/dVDD(STDBY)/dt = (300 mA)/(15 mV/µs) = 20µF
This configuration is a worst case, with the assumption no regulator is available.

Example 2 Simplified regulator

The regulator should be able to provide significant amount of the current during the standby
exit process. For example, in case of an ideal voltage regulator providing 200 mA current, it
is possible to recalculate the equivalent ESRSTDBY(MAX) and CSTDBY(MIN) as follows:

d. Based on typical time for standby exit sequence of 20 µs, ESR(MIN) can actually be considered at ~50 kHz.

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ESRSTDBY(MAX) = VDD(STDBY)|/(IDD_BV  200 mA) = (30 mV)/(100 mA) = 0.3 

CSTDBY(MIN) = (IDD_BV  200 mA)/dVDD(STDBY)/dt = (300 mA 
200 mA)/(15 mV/µs) = 6.7 µF
In case optimization is required, CSTDBY(MIN) and ESRSTDBY(MAX) should be calculated
based on the regulator characteristics as well as the board VDD plane characteristics.

3.17.2 Low voltage detector electrical characteristics

The device implements a Power-on Reset (POR) module to ensure correct power-up
initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV
voltage while device is supplied:
 POR monitors VDD during the power-up phase to ensure device is maintained in a safe
reset state (refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR
in device reference manual)
 LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer
to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27 in device
reference manual)
 LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to
RGM Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference
manual)
 LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status
(RGM_DES) Register flag F_LVD12_PD1 in device reference manual
 LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status
(RGM_DES) Register flag F_LVD12_PD0 in device reference manual)
Note: When enabled, power domain No. 2 is monitored through LVDLVBKP.

Figure 12. Low voltage detector vs reset

VDD

VLVDHVxH
VLVDHVxL

RESET

Note: Figure 12: Low voltage detector vs reset does not apply to LVDHV5 low voltage detector
because LVDHV5 is automatically disabled during reset and it must be enabled by software
again. Once the device is forced to reset by LVDHV5, the LVDHV5 is disabled and reset is

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released as soon as internal reset sequence is completed regardless of LVDHV5H

threshold.

Table 27. Low voltage detector electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

VPORUP SR P Supply for functional POR module — 1.0 — 5.5

TA = 25 °C,
P 1.5 — 2.6
VPORH CC Power-on reset threshold after trimming
T — 1.5 — 2.6
VLVDHV3H CC T LVDHV3 low voltage detector high threshold — — 2.95
V
VLVDHV3L CC P LVDHV3 low voltage detector low threshold 2.6 — 2.9
VLVDHV5H CC T LVDHV5 low voltage detector high threshold — — 4.5
—
VLVDHV5L CC P LVDHV5 low voltage detector low threshold 3.8 — 4.4
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold 1.08 — 1.16
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold 1.08 — 1.16
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

3.18 Power consumption

Table 28 provides DC electrical characteristics for significant application modes. These
values are indicative values; actual consumption depends on the application.

Table 28. Power consumption on VDD_BV and VDD_HV

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

RUN mode maximum

IDDMAX(2) CC D — — 115 140(3) mA
average current
T fCPU = 8 MHz — 7 —
T fCPU = 16 MHz — 18 —
RUN mode typical
IDDRUN(4) CC T fCPU = 32 MHz — 29 — mA
average current(5)
P fCPU = 48 MHz — 40 100
P fCPU = 64 MHz — 51 125
C Slow internal RC oscillator TA = 25 °C — 8 15
IDDHALT CC HALT mode current(6) mA
P (128 kHz) running TA = 125 °C — 14 25

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Table 28. Power consumption on VDD_BV and VDD_HV (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

P TA = 25 °C — 180 700(8)
µA
D TA = 55 °C — 500 —
Slow internal RC oscillator
IDDSTOP CC D STOP mode current(7) TA = 85 °C — 1 6(8)
(128 kHz) running
D TA = 105 °C — 2 9(8) mA
P TA = 125 °C — 4.5 12(8)
P TA = 25 °C — 30 100
D TA = 55 °C — 75 —
STANDBY2 mode Slow internal RC oscillator
IDDSTDBY2 CC D TA = 85 °C — 180 700 µA
current(9) (128 kHz) running
D TA = 105 °C — 315 1000
P TA = 125 °C — 560 1700
T TA = 25 °C — 20 60
D TA = 55 °C — 45 —
STANDBY1 mode Slow internal RC oscillator
IDDSTDBY1 CC D TA = 85 °C — 100 350 µA
current(10) (128 kHz) running
D TA = 105 °C — 165 500
D TA = 125 °C — 280 900
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. IDDMAX is drawn only from the VDD_BV pin. Running consumption does not include I/Os toggling which is highly dependent
on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from
code flash while modify operation ongoing on data flash. Notice that this value can be significantly reduced by application:
switch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used
functions, use low power mode when possible.
3. Higher current may be sinked by device during power-up and standby exit. Please refer to in rush current on Table 26.
4. IDDRUN is drawn only from the VDD_BV pin. RUN current measured with typical application with accesses on both flash and
RAM.
5. Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in
loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at
max frequency, periodic SW/WDG timer reset enabled.
6. Data Flash Power Down. Code Flash in Low Power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock.
FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16
channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but
no communication). RTC/API ON. PIT ON. STM ON. ADC ON but not conversion except 2 analog watchdog.
7. Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPvreg off, ULPVreg/LPVreg on.
All possible peripherals off and clock gated. Flash in power down mode.
8. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator
module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures
exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP
specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and
the main regulator will be automatically switched off when the load current is below 6 mA.
9. Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all
possible modules switched off.
10. ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off.

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3.19 Flash memory electrical characteristics

3.19.1 Program/Erase characteristics

Table 29 shows the program and erase characteristics.

Table 29. Program and erase specifications

Value
Symbol C Parameter Unit
Initial
Min Typ(1) Max(3)
max(2)

Tdwprogram Double word (64 bits) program time(4) — 22 50 500 µs

T16Kpperase 16 KB block preprogram and erase time — 300 500 5000 ms
CC C
T32Kpperase 32 KB block preprogram and erase time — 400 600 5000 ms
T128Kpperase 128 KB block preprogram and erase time — 800 1300 7500 ms
Tesus CC D Erase suspend latency — — 30 30 µs
1. Typical program and erase times assume nominal supply values and operation at 25 °C.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.

Table 30. Flash module life

Value
Symbol C Parameter Conditions Unit
Min Typ Max

16 KB blocks 100000 — —
Number of program/erase cycles
P/E CC C per block over the operating 32 KB blocks 10000 100000 — cycles
temperature range (TJ)
128 KB blocks 1000 100000 —
Blocks with
20 — —
0–1000 P/E cycles

Minimum data retention at 85 °C Blocks with

Retention CC C 10 — — years
average ambient temperature(1) 1001–10000 P/E cycles
Blocks with
5 — —
10001–100000 P/E cycles
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.

ECC circuitry provides correction of single bit faults and is used to improve further
automotive reliability results. Some units will experience single bit corrections throughout
the life of the product with no impact to product reliability.

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Table 31. Flash read access timing

Symbol C Parameter Conditions(1) Max Unit

P 2 wait states 64
fREAD CC C Maximum frequency for Flash reading 1 wait state 40 MHz
C 0 wait states 20
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

3.19.2 Flash power supply DC characteristics

Table 32 shows the power supply DC characteristics on external supply.

Table 32. Flash memory power supply DC electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Code flash memory module read

Sum of the current consumption on — 15 33
IFREAD fCPU = 64 MHz(3)
(2) CC D VDD_HV and VDD_BV on read mA
access Data flash memory module read
— 15 33
fCPU = 64 MHz(3)
Program/Erase ongoing while
reading code flash memory — 15 33
Sum of the current consumption on registers fCPU = 64 MHz(3)
IFMOD(2) CC D VDD_HV and VDD_BV on matrix mA
modification (program/erase) Program/Erase ongoing while
reading data flash memory — 15 33
registers fCPU = 64 MHz(3)
During code flash memory low-
— — 900
Sum of the current consumption on power mode
IFLPW CC D µA
VDD_HV and VDD_BV During data flash memory low-
— — 900
power mode
During code flash memory
— — 150
Sum of the current consumption on power-down mode
IFPWD CC D µA
VDD_HV and VDD_BV During data flash memory power-
— — 150
down mode
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. This value is only relative to the actual duration of the read cycle
3. fCPU 64 MHz can be achieved only at up to 105 °C

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3.19.3 Start-up/Switch-off timings

Table 33. Start-up time/Switch-off time

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

T Code Flash — — 125

TFLARSTEXIT CC Delay for Flash module to exit reset mode
T Data Flash — — 125
T Delay for Flash module to exit low-power Code Flash — — 0.5
TFLALPEXIT CC
T mode Data Flash — — 0.5
T Delay for Flash module to exit power-down Code Flash — — 30
TFLAPDEXIT CC µs
T mode Data Flash — — 30
T Delay for Flash module to enter low-power Code Flash — — 0.5
TFLALPENTRY CC
T mode Data Flash — — 0.5
T Delay for Flash module to enter power- Code Flash — — 1.5
TFLAPDENTRY CC
T down mode Data Flash — — 1.5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

3.20 Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

3.20.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user apply EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
 Software recommendations:The software flowchart must include the management of
runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical data corruption (control registers...)
 Prequalification trials:Most of the common failures (unexpected reset and program
counter corruption) can be reproduced by manually forcing a low state on the reset pin
or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When
unexpected behavior is detected, the software can be hardened to prevent
unrecoverable errors occurring (see application note Software Techniques For
Improving Microcontroller EMC Performance (AN1015)).

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3.20.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission
test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI
measurements.

Table 34. EMI radiated emission measurement(1)(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

S
— — Scan range — 0.150 — 1000 MHz
R
S
fCPU — Operating frequency — — 64 — MHz
R
S
VDD_LV — LV operating voltages — — 1.28 — V
R

VDD = 5 V, TA = 25 °C, No PLL

LQFP144 package frequency — — 18 dBµV
C Test conforming to IEC modulation
SEMI T Peak level
C 61967-2, ±2% PLL
fOSC = 8 MHz/fCPU = 64 frequency — — 14 dBµV
MHz modulation
1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4
2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local
marketing representative.

3.20.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.

3.20.3.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).

Table 35. ESD absolute maximum ratings(1) (2)

Symbol C Ratings Conditions Class Max value Unit

Electrostatic discharge voltage TA = 25 °C

VESD(HBM) CC T H1C 2000
(Human Body Model) conforming to AEC-Q100-002
Electrostatic discharge voltage TA = 25 °C
VESD(MM) CC T M2 200 V
(Machine Model) conforming to AEC-Q100-003

Electrostatic discharge voltage TA = 25 °C 500

VESD(CDM) CC T C3A
(Charged Device Model) conforming to AEC-Q100-011 750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

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2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.

3.20.3.2 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up
performance:
 A supply overvoltage is applied to each power supply pin.
 A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 36. Latch-up results

Symbol C Parameter Conditions Class

TA = 125 °C
LU CC T Static latch-up class II level A
conforming to JESD 78

3.21 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics
The device provides an oscillator/resonator driver. Figure 13 describes a simple model of
the internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
Table 37 provides the parameter description of 4 MHz to 16 MHz crystals used for the
design simulations.

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Figure 13. Crystal oscillator and resonator connection scheme

EXTAL
C1

EXTAL

Crystal
XTAL
C2
DEVICE
VDD
I

EXTAL
XTAL
DEVICE

Resonator
XTAL

DEVICE

Notes:
1. XTAL/EXTAL must not be directly used to drive external circuits
2. A series resistor may be required, according to crystal oscillator supplier recommendations.

Table 37. Crystal description

Shunt
Crystal
Crystal Crystal Load on capacitance
Nominal equivalent
NDK crystal motional motional xtalin/xtalout between
frequency series
reference capacitance inductance C1 = C2 xtalout
(MHz) resistance
(Cm) fF (Lm) mH (pF)(1) and xtalin
ESR 
C0(2) (pF)

4 NX8045GB 300 2.68 591.0 21 2.93

8 300 2.46 160.7 17 3.01
10 150 2.93 86.6 15 2.91
12 NX5032GA 120 3.11 56.5 15 2.93
16 120 3.90 25.3 10 3.00
1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all
the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,
etc.).

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Figure 14. Fast external crystal oscillator (4 to 16 MHz) timing diagram

S_MTRANS bit (ME_GS register)

‘1’

‘0’

VXTAL
1/fFXOSC

VFXOSC
90%

VFXOSCOP

10%

tFXOSCSU valid internal clock

Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Fast external crystal

fFXOSC SR — — 4.0 — 16.0 MHz
oscillator frequency
VDD = 3.3 V ± 10%,
CC C PAD3V5V = 1 2.2 — 8.2
OSCILLATOR_MARGIN = 0
VDD = 5.0 V ± 10%,
CC P PAD3V5V = 0 2.0 — 7.4
Fast external crystal OSCILLATOR_MARGIN = 0
gmFXOSC mA/V
oscillator transconductance VDD = 3.3 V ± 10%,
CC C PAD3V5V = 1 2.7 — 9.7
OSCILLATOR_MARGIN = 1
VDD = 5.0 V ± 10%,
CC C PAD3V5V = 0 2.5 — 9.2
OSCILLATOR_MARGIN = 1
fOSC = 4 MHz,
1.3 — —
Oscillation amplitude at OSCILLATOR_MARGIN = 0
VFXOSC CC T V
EXTAL fOSC = 16 MHz,
1.3 — —
OSCILLATOR_MARGIN = 1
VFXOSCOP CC C Oscillation operating point — — 0.95 — V
Fast external crystal
IFXOSC(2) CC T — — 2 3 mA
oscillator consumption
fOSC = 4 MHz,
— — 6
Fast external crystal OSCILLATOR_MARGIN = 0
tFXOSCSU CC T ms
oscillator start-up time fOSC = 16 MHz,
— — 1.8
OSCILLATOR_MARGIN = 1

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Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)
Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Input high level CMOS

VIH SR P Oscillator bypass mode 0.65VDD — VDD+0.4 V
(Schmitt Trigger)
Input low level CMOS
VIL SR P Oscillator bypass mode 0.4 — 0.35VDD V
(Schmitt Trigger)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled
peripherals)

3.22 Slow external crystal oscillator (32 kHz) electrical

characteristics
The device provides a low power oscillator/resonator driver.

Figure 15. Crystal oscillator and resonator connection scheme

OSC32K_EXTAL OSC32K_EXTAL

C1

Resonator
Crystal

OSC32K_XTAL OSC32K_XTAL

DEVICE C2 DEVICE

Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.

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Figure 16. Equivalent circuit of a quartz crystal

C0

Crystal Cm Rm Lm
C1 C2
C1 C2

Table 39. Crystal motional characteristics(1)

Value
Symbol Parameter Conditions Unit
Min Typ Max

Lm Motional inductance — — 11.796 — KH

Cm Motional capacitance — — 2 — fF
Load capacitance at OSC32K_XTAL and
C1/C2 — 18 — 28 pF
OSC32K_EXTAL with respect to ground(2)
AC coupled @ C0 = 2.85
— — 65
pF(4)

Rm(3) Motional resistance AC coupled @ C0 = 4.9 pF(4) — — 50 kW

AC coupled @ C0 = 7.0 pF(4) — — 35
AC coupled @ C0 = 9.0 pF(4) — — 30
1. Crystal used: Epson Toyocom MC306
2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It
includes all the parasitics due to board traces, crystal and package.
3. Maximum ESR (Rm) of the crystal is 50 k
4. C0 includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins

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Figure 17. Slow external crystal oscillator (32 kHz) timing diagram

OSCON bit (OSC_CTL register)

VOSC32K_XTAL 1/fSXOSC

VSXOSC
90%

10%

TSXOSCSU valid internal clock

Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics
Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

fSXOSC SR — Slow external crystal oscillator frequency — 32 32.768 40 kHz

VSXOSC CC T Oscillation amplitude — — 2.1 — V
ISXOSCBIAS CC T Oscillation bias current — — 2.5 — µA
ISXOSC CC T Slow external crystal oscillator consumption — — — 8 µA
TSXOSCSU CC T Slow external crystal oscillator start-up time — — — 2(2) s
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. Values are specified for no neighbor
GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins should not toggle.
2. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.

3.23 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to
generate a fast system clock from the main oscillator driver.

Table 41. FMPLL electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

fPLLIN SR — FMPLL reference clock(2) — 4 — 64 MHz

FMPLL reference clock duty
PLLIN SR — — 40 — 60 %
cycle(2)
fPLLOUT CC D FMPLL output clock frequency — 16 — 64 MHz

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Table 41. FMPLL electrical characteristics (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

VCO frequency without

P — 256 — 512
frequency modulation
fVCO(3) CC MHz
VCO frequency with frequency
C — 245 — 533
modulation
fCPU SR — System clock frequency — — — 64 MHz
fFREE CC P Free-running frequency — 20 — 150 MHz
tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) — 40 100 µs
tSTJIT CC — FMPLL short term jitter(4) fsys maximum –4 — 4 %
fPLLIN = 16 MHz (resonator),
tLTJIT CC — FMPLL long term jitter — — 10 ns
fPLLCLK @ 64 MHz, 4000 cycles
IPLL CC C FMPLL consumption TA = 25 °C — — 4 mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional
mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.
3. Frequency modulation is considered ±4%
4. Short term jitter is measured on the clock rising edge at cycle n and n+4.

3.24 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at
the power-up of the device.

Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

CC P Fast internal RC oscillator high TA = 25 °C, trimmed — 16 —

fFIRC MHz
SR — frequency — 12 20
IFIRCRUN Fast internal RC oscillator high
(2) CC T TA = 25 °C, trimmed — — 200 µA
frequency current in running mode
Fast internal RC oscillator high
IFIRCPWD CC D frequency current in power down TA = 125 °C — — 10 µA
mode
sysclk = off — 500 —
sysclk = 2 MHz — 600 —
Fast internal RC oscillator high
IFIRCSTOP CC T frequency and system clock current TA = 25 °C sysclk = 4 MHz — 700 — µA
in stop mode
sysclk = 8 MHz — 900 —
sysclk = 16 MHz — 1250 —

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Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Fast internal RC oscillator start-up

tFIRCSU CC C VDD = 5.0 V ± 10% — 1.1 2.0 µs
time
Fast internal RC oscillator precision
FIRCPRE CC T TA = 25 °C 1 — +1 %
after software trimming of fFIRC
Fast internal RC oscillator trimming
FIRCTRIM CC T TA = 25 °C — 1.6 %
step
Fast internal RC oscillator variation
in over temperature and supply with
FIRCVAR CC P — 5 — +5 %
respect to fFIRC at TA = 25 °C in
high-frequency configuration
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

3.25 Slow internal RC oscillator (128 kHz) electrical

characteristics
The device provides a 128 kHz slow internal RC oscillator. This can be used as the
reference clock for the RTC module.

Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

CC P Slow internal RC oscillator low TA = 25 °C, trimmed — 128 —

fSIRC kHz
SR — frequency — 100 — 150
Slow internal RC oscillator low
ISIRC(2) CC C TA = 25 °C, trimmed — — 5 µA
frequency current
Slow internal RC oscillator start-up TA = 25 °C, VDD = 5.0 V ±
tSIRCSU CC P — 8 12 µs
time 10%
Slow internal RC oscillator
SIRCPRE CC C precision after software trimming of TA = 25 °C 2 — +2
fSIRC %
Slow internal RC oscillator trimming
SIRCTRIM CC C — — 2.7 —
step
Slow internal RC oscillator variation
in temperature and supply with
SIRCVAR CC C High frequency configuration 10 — +10 %
respect to fSIRC at TA = 55 °C in
high frequency configuration
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

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3.26 ADC electrical characteristics

3.26.1 Introduction
The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital
converter.

Figure 18. ADC characteristic and error definitions

Offset error (EO) Gain error (EG)

1023

1022

1021

1020

1019

1 LSB ideal = VDD_ADC / 1024

1018

(2)

code out
7
(1)
6

5
(5) (1) Example of an actual transfer curve
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve

2 (3)

1
1 LSB (ideal)

0
1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)

Offset error (EO)

3.26.2 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is
considered.

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To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin;
furthermore, it sources charge during the sampling phase, when the analog signal source is
a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: being CS and Cp2 substantially two switched capacitances, with a
frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to
ground. For instance, assuming a conversion rate of 1 MHz, with CS+Cp2 equal to 3 pF, a
resistance of 330 k is obtained (REQ = 1 / (fc × (CS+Cp2)), where fc represents the
conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of RS + RF,
the external circuit must be designed to respect the Equation 4:

Equation 4
RS + RF
1
V A  ---------------------  --- LSB
R EQ 2

Equation 4 generates a constraint for external network design, in particular on a resistive

path.

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Figure 19. Input equivalent circuit (precise channels)

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD
Channel
Sampling
Selection
Source Filter Current Limiter

RS RF RL RSW1 RAD

VA CF CP1 CP2 CS

RS: Source impedance

RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance

Figure 20. Input equivalent circuit (extended channels)

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD
Channel Extended
Sampling
Selection Switch
Source Filter Current Limiter

RS RF RL RSW1 RSW2 RAD

VA CF CP1 CP3 CP2 CS

RS: Source impedance

RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance (two contributions, RSW1 and RSW2)
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1, CP2 and CP3)
CS: Sampling capacitance

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A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit in Figure 19): A charge sharing phenomenon is installed when the
sampling phase is started (A/D switch close).

Figure 21. Transient behavior during sampling phase

VCS Voltage transient on CS

VA
VA2 V <0.5 LSB

1 2
1 < (RSW + RAD) CS << ts

VA1 2 = RL (CS + CP1 + CP2)

ts t

In particular two different transient periods can be distinguished:

1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is

Equation 5
CP  CS
 1 =  R SW + R AD   ---------------------
CP + CS

Equation 5 can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time ts is always much
longer than the internal time constant:

Equation 6
 1   R SW + R AD   C S « t s

The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to Equation 7:

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Equation 7
V A1   C S + C P1 + C P2  = V A   C P1 + C P2 

2. A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:

Equation 8
 2  R L   C S + C P1 + C P2 

In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time ts, a constraints on
RL sizing is obtained:

Equation 9
8.5  
2 = 8.5  R L   C S + C P1 + C P2   t s
Of course, RL shall be sized also according to the current limitation constraints, in
combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. Equation 10 must be respected
(charge balance assuming now CS already charged at VA1):

Equation 10
VA2   C S + C P1 + C P2 + C F  = V A  C F + V A1   C P1 + C P2 + C S 

The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (ts). The filter is typically designed to act as anti-aliasing.

Figure 22. Spectral representation of input signal

Analog source bandwidth (VA)

tc < 2 RFCF (conversion rate vs. filter pole)

Noise fF = f0 (anti-aliasing filtering condition)

2 f0 < fC (Nyquist)

f0 f
Anti-aliasing filter (fF = RC filter pole) Sampled signal spectrum (fC = conversion rate)

fF f f0 fC f

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Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be
at least 2f0; it means that the constant time of the filter is greater than or at least equal to
twice the conversion period (tc). Again the conversion period tc is longer than the sampling
time ts, which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time ts, so the
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:

Equation 11
V A2 C P1 + C P2 + C F
------------ = --------------------------------------------------------
VA C P1 + C P2 + C F + C S

From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:

Equation 12
C F  2048  C S

3.26.3 ADC electrical characteristics

Table 44. ADC input leakage current

Value
Symbol C Parameter Conditions Unit
Min Typ Max

D TA = 40 °C — 1 70
D TA = 25 °C — 1 70
ILKG CC D Input leakage current TA = 85 °C No current injection on adjacent pin — 3 100 nA
D TA = 105 °C — 8 200
P TA = 125 °C — 45 400

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Table 45. ADC conversion characteristics

Value
Uni
Symbol C Parameter Conditions(1)
t
Min Typ Max

Voltage on
VSS_HV_ADC (ADC
S
VSS_ADC — reference) pin with — 0.1 — 0.1 V
R
respect to ground
(VSS)(2)
Voltage on
VDD_HV_ADC pin
S
VDD_ADC — (ADC reference) with — VDD0.1 — VDD+0.1 V
R
respect to ground
(VSS)
S Analog input VDD_ADC+0.
VAINx — — VSS_ADC0.1 — V
R voltage(3) 1
S ADC analog MH
fADC — — 6 — 32 + 4%
R frequency z
ADC_SY S ADC digital clock duty
— ADCLKSEL = 1(4) 45 — 55 %
S R cycle (ipg_clk)
S ADC0 consumption in
IADCPWD — — — — 50 µA
R power down mode
S ADC0 consumption in
IADCRUN — — — — 4 mA
R running mode
S
tADC_PU — ADC power up delay — — — 1.5 µs
R

C fADC = 32 MHz, INPSAMP = 17 0.5 —

ts T Sampling time(5) µs
C fADC = 6 MHz, INPSAMP = 255 — — 42
C
tc P Conversion time(6) fADC = 32 MHz, INPCMP = 2 0.625 — µs
C
C ADC input sampling
CS D — — — 3 pF
C capacitance
C ADC input pin
CP1 D — — — 3 pF
C capacitance 1
C ADC input pin
CP2 D — — — 1 pF
C capacitance 2
C ADC input pin
CP3 D — — — 1 pF
C capacitance 3
C Internal resistance of
RSW1 D — — — 3 k
C analog source
C Internal resistance of
RSW2 D — — — 2 k
C analog source
C Internal resistance of
RAD D — — — 2 k
C analog source

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Table 45. ADC conversion characteristics (continued)

Value
Uni
Symbol C Parameter Conditions(1)
t
Min Typ Max

Current VDD = 
5 — 5
injection on 3.3 V ± 10%
S one ADC input,
IINJ — Input current Injection mA
R different from VDD = 
the converted 5 — 5
5.0 V ± 10%
one
C Absolute value for
| INL | T No overload — 0.5 1.5 LSB
C integral non-linearity
C Absolute differential
| DNL | T No overload — 0.5 1.0 LSB
C non-linearity
C
| EO | T Absolute offset error — — 0.5 — LSB
C
C
| EG | T Absolute gain error — — 0.6 — LSB
C
P Total unadjusted Without current injection 2 0.6 2
C error(7) for precise
TUEp LSB
C T channels, input only With current injection 3 3
pins
T Total unadjusted Without current injection 3 1 3
C
TUEx error(7) for extended LSB
C T With current injection 4 4
channel
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS must be common (to be tied together externally).
3. VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion
will be clamped respectively to 0x000 or 0x3FF.
4. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal
divider by 2.
5. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within ts. After the end of the
sampling time ts, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock ts
depend on programming.
6. This parameter does not include the sampling time ts, but only the time for determining the digital result and the time to load
the result’s register with the conversion result.
7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.

3.27 On-chip peripherals

3.27.1 Current consumption

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3.27.2 DSPI characteristics

Table 46. On-chip peripherals current consumption(1)
Typical
Symbol C Parameter Conditions Unit
value(2)

Bitrate: Total (static + dynamic)

8 * fperiph + 85
500 Kbyte/s consumption:
– FlexCAN in loop-back
CAN (FlexCAN) supply mode
IDD_BV(CAN) CC T µA
current on VDD_BV Bitrate: – XTAL @ 8 MHz used as
8 * fperiph + 27
125 Kbyte/s CAN engine clock source
– Message sending period
is 580 µs
Static consumption:
– eMIOS channel OFF 29 * fperiph
eMIOS supply current on – Global prescaler enabled
IDD_BV(eMIOS) CC T µA
VDD_BV Dynamic consumption:
– It does not change varying the 3
frequency (0.003 mA)
Total (static + dynamic) consumption:
SCI (LINFlex) supply
IDD_BV(SCI) CC T – LIN mode 5 * fperiph + 31 µA
current on VDD_BV
– Baudrate: 20 Kbyte/s
Ballast static consumption (only clocked) 1
Ballast dynamic consumption
SPI (DSPI) supply current (continuous communication):
IDD_BV(SPI) CC T µA
on VDD_BV – Baudrate: 2 Mbit/s 16 * fperiph
– Transmission every 8 µs
– Frame: 16 bits
Ballast static consumption
41 * fperiph
(no conversion)
ADC supply current on
IDD_BV(ADC) CC T VDD = 5.5 V Ballast dynamic µA
VDD_BV
consumption 5 * fperiph
(continuous conversion)(3)
Analog static consumption
2 * fperiph
(no conversion)
ADC supply current on
IDD_HV_ADC(ADC) CC T VDD = 5.5 V Analog dynamic µA
VDD_HV_ADC
consumption 75 * fperiph + 32
(continuous conversion)
Code Flash + Data Flash
IDD_HV(FLASH) CC T supply current on VDD = 5.5 V — 8.21 mA
VDD_HV
PLL supply current on
IDD_HV(PLL) CC T VDD = 5.5 V — 30 * fperiph µA
VDD_HV
1. Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz
2. fperiph is an absolute value.

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3. During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e.,
(41 + 5) * fperiph.

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Package pinouts and signal descriptions

Table 47. DSPI characteristics(1)
DSPI0/DSPI1 DSPI2
No. Symbol C Parameter Unit
Min Typ Max Min Typ Max

Master mode
D 125 — — 333 — —
(MTFE = 0)
Slave mode
D 125 — — 333 — —
(MTFE = 0)
1 tSCK SR SCK cycle time ns
Master mode
D 83 — — 125 — —
(MTFE = 1)
Slave mode
D 83 — — 125 — —
(MTFE = 1)
— fDSPI SR D DSPI digital controller frequency — — fCPU — — fCPU MHz
DocID14619 Rev 13

Internal delay between pad

associated to SCK and pad
— tCSC CC D Master mode — — 130(2) — — 15(3) ns
associated to CSn in master
mode for CSn10
Internal delay between pad
associated to SCK and pad
— tASC CC D Master mode — — 130(3) — — 130(3) ns
associated to CSn in master
mode for CSn11

SPC560B40x/50x, SPC560C40x/50x
2 tCSCext(4) SR D CS to SCK delay Slave mode 32 — — 32 — — ns
3 tASCext (5) SR D After SCK delay Slave mode 1/fDSPI + 5 — — 1/fDSPI + 5 — — ns
CC D Master mode — tSCK/2 — — tSCK/2 —
4 tSDC SCK duty cycle ns
SR D Slave mode tSCK/2 — — tSCK/2 — —
5 tA SR D Slave access time Slave mode — — 1/fDSPI + 70 — — 1/fDSPI + 130 ns
6 tDI SR D Slave SOUT disable time Slave mode 7 — — 7 — — ns
7 tPCSC SR D PCSx to PCSS time 0 — — 0 — — ns
8 tPASC SR D PCSS to PCSx time 0 — — 0 — — ns
 Table 47. DSPI characteristics(1) (continued)

SPC560B40x/50x, SPC560C40x/50x
DSPI0/DSPI1 DSPI2
No. Symbol C Parameter Unit
Min Typ Max Min Typ Max

Master mode 43 — — 145 — —

9 tSUI SR D Data setup time for inputs ns
Slave mode 5 — — 5 — —
Master mode 0 — — 0 — —
10 tHI SR D Data hold time for inputs ns
(6) 2(6)
Slave mode 2 — — — —
Master mode — — 32 — — 50
11 tSUO(7) CC D Data valid after SCK edge ns
Slave mode — — 52 — — 160
Master mode 0 — — 0 — —
12 tHO(7) CC D Data hold time for outputs ns
Slave mode 8 — — 13 — —
DocID14619 Rev 13

1. Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns.

2. Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is
asserted. DSPI2 has only SLOW SCK available.
3. Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before
SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
4. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS
and internal SCK must be higher than tCSC to ensure positive tCSCext.

Package pinouts and signal descriptions

5. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and
internal SCK must be higher than tASC to ensure positive tASCext.
6. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of the DSPI_MCR.
7. SCK and SOUT configured as MEDIUM pad
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Figure 23. DSPI classic SPI timing – master, CPHA = 0

2 3

PCSx

4 1

SCK Output
(CPOL = 0)
4

SCK Output
(CPOL = 1)
10
9

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 47.

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Figure 24. DSPI classic SPI timing – master, CPHA = 1

PCSx

SCK Output
(CPOL = 0)
10

SCK Output
(CPOL = 1)

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 47.

Figure 25. DSPI classic SPI timing – slave, CPHA = 0

3
2
SS

1
SCK Input 4
(CPOL = 0)

4
SCK Input
(CPOL = 1)

5 11
12 6

SOUT First Data Data Last Data

9
10

SIN First Data Data Last Data

Note: Numbers shown reference Table 47.

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Figure 26. DSPI classic SPI timing – slave, CPHA = 1

SS

SCK Input
(CPOL = 0)

SCK Input
(CPOL = 1)
11
5 6
12

SOUT First Data Data Last Data

9
10
SIN First Data Data Last Data

Note: Numbers shown reference Table 47.

Figure 27. DSPI modified transfer format timing – master, CPHA = 0

3
PCSx

4 1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)

9 10

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 47.

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Figure 28. DSPI modified transfer format timing – master, CPHA = 1

PCSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)
10
9

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 47.

Figure 29. DSPI modified transfer format timing – slave, CPHA = 0

3
2
SS

SCK Input
(CPOL = 0)
4 4

SCK Input
(CPOL = 1)
11 12 6
5

SOUT First Data Data Last Data

9 10

SIN First Data Data Last Data

Note: Numbers shown reference Table 47.

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Figure 30. DSPI modified transfer format timing – slave, CPHA = 1

SS

SCK Input
(CPOL = 0)

SCK Input
(CPOL = 1)
11
5 6
12

SOUT First Data Data Last Data

9
10
SIN First Data Data Last Data

Note: Numbers shown reference Table 47.

Figure 31. DSPI PCS strobe (PCSS) timing

7 8

PCSS

PCSx

Note: Numbers shown reference Table 47.

3.27.3 Nexus characteristics

Table 48. Nexus characteristics

Value
No. Symbol C Parameter Unit
Min Typ Max

1 tTCYC CC D TCK cycle time 64 — — ns

2 tMCYC CC D MCKO cycle time 32 — — ns
3 tMDOV CC D MCKO low to MDO data valid — — 8 ns

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Table 48. Nexus characteristics (continued)

Value
No. Symbol C Parameter Unit
Min Typ Max

4 tMSEOV CC D MCKO low to MSEO_b data valid — — 8 ns

5 tEVTOV CC D MCKO low to EVTO data valid — — 8 ns
tNTDIS CC D TDI data setup time 15 — — ns
10
tNTMSS CC D TMS data setup time 15 — — ns
tNTDIH CC D TDI data hold time 5 — — ns
11
tNTMSH CC D TMS data hold time 5 — — ns
12 tTDOV CC D TCK low to TDO data valid 35 — — ns
13 tTDOI CC D TCK low to TDO data invalid 6 — — ns

Figure 32. Nexus TDI, TMS, TDO timing

TCK

10
11

TMS, TDI

12

TDO

Note: Numbers shown reference Table 48.

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3.27.4 JTAG characteristics

Table 49. JTAG characteristics

Value
No. Symbol C Parameter Unit
Min Typ Max

1 tJCYC CC D TCK cycle time 64 — — ns

2 tTDIS CC D TDI setup time 15 — — ns
3 tTDIH CC D TDI hold time 5 — — ns
4 tTMSS CC D TMS setup time 15 — — ns
5 tTMSH CC D TMS hold time 5 — — ns
6 tTDOV CC D TCK low to TDO valid — — 33 ns
7 tTDOI CC D TCK low to TDO invalid 6 — — ns

Figure 33. Timing diagram – JTAG boundary scan

TCK

2/4 3/5

DATA INPUTS INPUT DATA VALID

DATA OUTPUTS OUTPUT DATA VALID

DATA OUTPUTS

Note: Numbers shown reference Table 49.

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4 Package characteristics

4.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

4.2 Package mechanical data

4.2.1 LQFP64

Figure 34. LQFP64 package mechanical drawing

D1 ccc C

D3 A
A2
48 33

49 32

b
L1

E3 E1 E

L
A1 K

64
17
Pin 1
identification 1 16 c
5W_ME

Table 50. LQFP64 mechanical data

mm inches(1)
Symbol
Min Typ Max Min Typ Max

A — — 1.6 — — 0.063
A1 0.05 — 0.15 0.002 — 0.0059
A2 1.35 1.4 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 — 0.2 0.0035 — 0.0079
D 11.8 12 12.2 0.4646 0.4724 0.4803

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Table 50. LQFP64 mechanical data (continued)

mm inches(1)
Symbol
Min Typ Max Min Typ Max

D1 9.8 10 10.2 0.3858 0.3937 0.4016

D3 — 7.5 — — 0.2953 —
E 11.8 12 12.2 0.4646 0.4724 0.4803
E1 9.8 10 10.2 0.3858 0.3937 0.4016
E3 — 7.5 — — 0.2953 —
e — 0.5 — — 0.0197 —
L 0.45 0.6 0.75 0.0177 0.0236 0.0295
L1 — 1 — — 0.0394 —
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc — — 0.08 — — 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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4.2.2 LQFP100

Figure 35. LQFP100 package mechanical drawing

Table 51. LQFP100 mechanical data

mm inches(1)
Symbol
Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630
A1 0.050 — 0.150 0.0020 — 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 — 0.200 0.0035 — 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 — 12.000 — — 0.4724 —
E 15.800 16.000 16.200 0.6220 0.6299 0.6378

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Table 51. LQFP100 mechanical data (continued)

mm inches(1)
Symbol
Min Typ Max Min Typ Max

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 — 12.000 — — 0.4724 —
e — 0.500 — — 0.0197 —
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 — 1.000 — — 0.0394 —
k 0.0 ° 3.5 ° 7.0 ° 0.0 ° 3.5 ° 7.0 °
Tolerance mm inches
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

4.2.3 LQFP144

Figure 36. LQFP144 package mechanical drawing

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Table 52. LQFP144 mechanical data

mm inches(1)
Symbol
Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630
A1 0.050 — 0.150 0.0020 — 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 — 0.200 0.0035 — 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 — 17.500 — — 0.6890 —
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 — 17.500 — — 0.6890 —
e — 0.500 — — 0.0197 —
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 — 1.000 — — 0.0394 —
k 0.0 ° 3.5 ° 7.0° 3.5 ° 0.0 ° 7.0 °
Tolerance mm inches
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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4.2.4 LBGA208

Figure 37. LBGA208 package mechanical drawing

Seating
plane

ddd C
A
D

A2
A4
A3

A1
A
D

B
D1
A
e F

T
R

F
P
N
M
L
K
J

E1
E
H
G
F
E
D
C
B

e
A
1 3 5 7 9 11 13 15
2 4 6 8 10 12 14 16

A1 corner index area b (208 balls)

(See note 1)
eee M C A B
fff M C

Bottom view

1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized
markings, or other feature of package body or integral heatslug.
A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.

Table 53. LBGA208 mechanical data

mm inches(1)
Symbol Notes
Min Typ Max Min Typ Max
(2)
A — — 1.70 — — 0.0669
A1 0.30 — — 0.0118 — — —
A2 — 1.085 — — 0.0427 — —
A3 — 0.30 — — 0.0118 — —
A4 — — 0.80 — — 0.0315 —
(3)
b 0.50 0.60 0.70 0.0197 0.0236 0.0276

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Table 53. LBGA208 mechanical data (continued)

mm inches(1)
Symbol Notes
Min Typ Max Min Typ Max

D 16.80 17.00 17.20 0.6614 0.6693 0.6772 —

D1 — 15.00 — — 0.5906 — —
E 16.80 17.00 17.20 0.6614 0.6693 0.6772 —
E1 — 15.00 — — 0.5906 — —
e — 1.00 — — 0.0394 — —
F — 1.00 — — 0.0394 — —
ddd — — 0.20 — — 0.0079 —
(4)
eee — — 0.25 — — 0.0098
(5)
fff — — 0.10 — — 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. LBGA stands for Low profile Ball Grid Array.
— Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the
component
— The maximum total package height is calculated by the following methodology:
A2 Typ + A1 Typ + (A12 + A32 + A42 tolerance values)
— Low profile: 1.20 mm  A 1.70 mm
3. The typical ball diameter before mounting is 0.60 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.

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Ordering information SPC560B40x/50x, SPC560C40x/50x

5 Ordering information

Figure 38. Commercial product code structure

Example code:
SPC56 0 B 50 L3 C 5E0 Y
Product identifier Core Family Memory Package Temperature Custom vers. Conditioning

Y = Tray
X = Tape and Reel 90°

4E0 = 48 MHz EEPROM 5V/3V
6E0 = 64 MHz EEPROM 5V/3V

B = 40 to 105 °C
C = 40 to 125 °C

L1 = LQFP64
L3 = LQFP100
L5 = LQFP144
B2 = LBGA2081

50 = 512 KB
44 = 384 KB
40 = 256 KB

B = Body
C = Gateway

0 = e200z0

SPC56 = Power Architecture in
90nm

1. LBGA208 available only as development package for Nexus2+

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SPC560B40x/50x, SPC560C40x/50x Abbreviations

Appendix A Abbreviations

Table 54 lists abbreviations used but not defined elsewhere in this document.

Table 54. Abbreviations

Abbreviation Meaning

CMOS Complementary metal–oxide–semiconductor

CPHA Clock phase
CPOL Clock polarity
CS Peripheral chip select
EVTO Event out
MCKO Message clock out
MDO Message data out
MSEO Message start/end out
MTFE Modified timing format enable
SCK Serial communications clock
SOUT Serial data out
TBD To be defined
TCK Test clock input
TDI Test data input
TDO Test data output
TMS Test mode select

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Revision history SPC560B40x/50x, SPC560C40x/50x

Revision history

Table 55. Document revision history

Date Revision Changes

04-Apr-2008 1 Initial release.

Made minor editing and formatting changes to improve readability
Harmonized oscillator naming throughout document
Modified document title
Updated “Feature” on cover page
Replaced LFBGA208 with LBGA208
Updated “Description” Section
Updated “SPC560B40x/50x and SPC560C40x/50x device comparison” table
Added “Block diagram” section
Section 3 “Package pinouts and signal descriptions”:
– Removed signal descriptions (these are found in the device reference manual)
Updated “LQFP 144-pin configuration (top view)” figure:
– Replaced VPP with VSS_HV on pin 18
– Added MA[1] as AF3 for PC[10] (pin 28)
– Added MA[0] as AF2 for PC[3] (pin 116)
– Changed description for pin 120 to PH[10] / GPIO[122] / TMS
– Changed description for pin 127 to PH[9] / GPIO[121] / TCK
– Replaced NMI[0] with NMI on pin 11
Updated “LQFP 100-pin configuration (top view)” figure:
– Replaced VPP with VSS_HV on pin 14
– Added MA[1] as AF3 for PC[10] (pin 22)
06-Mar-2009 2 – Added MA[0] as AF2 for PC[3] (pin 77)
– Changed description for pin 81 to PH[10] / GPIO[122] / TMS
– Changed description for pin 88 to PH[9] / GPIO[121] / TCK
– Removed E1UC[19] from pin 76
– Replaced [11] with WKUP[11] for PB[3] (pin 1)
– Replaced NMI[0] with NMI on pin 7
Updated “LBGA208 configuration” figure:
– Changed description for ball B8 from TCK to PH[9]
– Changed description for ball B9 from TMS to PH[10]
– Updated descriptions for balls R9 and T9
Added “Parameter classification” section and tagged parameters in tables where
appropriate
Added “NVUSRO register” section
Updated “Absolute maximum ratings” table
“Recommended operating conditions” section :
– Added note on RAM data retention to end of section
Updated “Recommended operating conditions (3.3 V)” and “Recommended operating
conditions (5.0 V)”
Added “Package thermal characteristics” section
Updated “Power considerations” section
Updated I/O input DC electrical characteristics definition” figure

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Table 55. Document revision history (continued)

Date Revision Changes

Updated tables:
– “I/O input DC electrical characteristics”
– “I/O pull-up/pull-down DC electrical characteristics”
– “SLOW configuration output buffer electrical characteristics”
– “MEDIUM configuration output buffer electrical characteristics”
– “FAST configuration output buffer electrical characteristics”
Added “Output pin transition times” section
Updated “I/O consumption” table
Updated “Start-up reset requirements” figure
Updated “Reset electrical characteristics” table
“Voltage regulator electrical characteristics” section:
– Amended description of LV_PLL
“Voltage regulator capacitance connection” figure:
– Exchanged position of symbols CDEC1 and CDEC2
Updated tables”
– “Voltage regulator electrical characteristics”
– “Low voltage monitor electrical characteristics”
2
06-Mar-2009 – “Low voltage power domain electrical characteristics”
(continued)
Added “Low voltage monitor vs reset” figure
Updated “Flash memory electrical characteristics” section
Added “Electromagnetic compatibility (EMC) characteristics” section
Updated “Fast external crystal oscillator (4 to 16 MHz) electrical characteristics”
section
Updated “Slow external crystal oscillator (32 kHz) electrical characteristics” section
Updated tables:
– “FMPLL electrical characteristics”
– “Fast internal RC oscillator (16 MHz) electrical characteristics”
– “Slow internal RC oscillator (128 kHz) electrical characteristics”
Added “On-chip peripherals” section
Added “ADC input leakage current” table
Updated “ADC conversion characteristics” table
Updated “ECOPACK®” section
Corrected inverted column headings for typical and minimum dimensions in “LQFP64
mechanical data” and “LQFP100 mechanical data” tables
Added “Abbrevation” appendix
03-Jun-2009 3 Corrected “Commercial product code structure” figure

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Table 55. Document revision history (continued)

Date Revision Changes

Updated “LBGA208 configuration” figure

“Absolute maximum ratings” table:
– VDD_ADC, VIN: changed min value for “relative to VDD” condition
– ICORELV: added new row
“Recommended operating conditions (5.0 V)” table:
– TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part,
TJ M-Grade Part: added new rows
– Changed capacitance value in footnote
“Output pin transition times” table:
– MEDIUM configuration: added condition for PAD3V5V = 0
Updated “Voltage regulator capacitance connection”
“Voltage regulator electrical characteristics” table:
– CDEC1: changed min value
– IMREG: changed max value
06-Aug-2009 4 – IDD_BV: added max value footnote
“Low voltage monitor electrical characteristics” table:
– VLVDHV3H, VLVDHV5H: changed max value
– VLVDHV3L, VLVDHV5L: added max value
Updated “Low voltage power domain electrical characteristics” table
“Flash module life” table:
– Retention: deleted min value footnote for “Blocks with 100000 P/E cycles“
“Fast external crystal oscillator (4 to 16 MHz) electrical characteristics” table:
– IFXOSC: added typ value
“Slow external crystal oscillator (32 kHz) electrical characteristics” table
– VSXOSC: changed typ value
– TSXOSCSU: added max value footnote
“FMPLL electrical characteristics” table
– tLTJIT: added max value
Updated “LQFP100 package mechanical drawing”

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Table 55. Document revision history (continued)

Date Revision Changes

Table: “Absolute maximum ratings”

– VDD_BV, VDD_ADC, VIN: changed max value
Table: ”Recommended operating conditions (3.3 V)”
– TVDD: deleted min value
Table: “Reset electrical characteristics“
– Changed footnotes 2 and 5
Table: “Voltage regulator electrical characteristics“
– CREGn: changed max value
– CDEC1: split into 2 rows
– Updated voltage values in footnote 3
Table: “Low voltage monitor electrical characteristics“
– Updated column Conditions
– VLVDLVCORL, VLVDLVBKPL: changed min/max value
Table: “Program and erase specifications“
20-Jan-2010 5
– Tdwprogram: added initial max value
Table: “Flash module life“
– Retention: changed min value for blocks with 100K P/E cycles
Table: “Flash power supply DC electrical characteristics“
– IFREAD, IFMOD: added typ value
– Added a footnote
Added Section: “ NVUSRO[WATCHDOG_EN] field description“
Section 4.18: “ADC electrical characteristics“ has been moved up in hierarchy (it was
Section 4.18.5).
Table: “ ADC conversion characteristics“
– RAD: changed initial max value
Table: “On-chip peripherals current consumption“
– Removed min/max from the heading
– Changed unit of measurement and consequently rounded the values
15-Mar-2010 6 Internal release.

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Table 55. Document revision history (continued)

Date Revision Changes

Changes between revisions 5 and 7

Added LQFP64 package information
Updated the “Features“ section.
Section “Introduction”
– Relocated a note
Table: “SPC560B40x/50x and SPC560C40x/50x device comparison“
– Added footnote regarding SCI and CAN
Added eDMA block in the “SPC560B40x/50x and SPC560C40x/50x series block
diagram” figure
Removed alternate function information from “LQFP 100-pin configuration” and
“LQFP 100-pin configuration” figures.
Added “Functional port pin descriptions” table
Deleted the “NVUSRO[WATCHDOG_EN] field description“ section
Table: “Absolute maximum ratings“
– Removed the min value of VIN relative tio VDD
Table ”Recommended operating conditions (3.3 V)”
– TVDD: made single row
”Recommended operating conditions (5.0 V)”
– deleted TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ
M-Grade Part rows
Table: “LQFP thermal characteristics”
– Added more rows
– Rounded the values
22-Jul-2010 7 Removed table “LBGA208 thermal characteristics”
Table “I/O input DC electrical characteristics”
– WFI: insered a footnote
– WNFI: insered a footnote
Table “I/O consuption“
– Removed IDYNSEG row
– Added “I/O weight “ table
Replaced “nRSTIN” with “RESET” in the “RESET electrical characteristics” section.
Table “Voltage regulator electrical characteristics“
– Updated the values
– Removed IVREGREF and IVREDLVD12
– Added a note about IDD_BC
Table: “Low voltage monitor electrical characteristics“
– changed min valueVLVDHV3L, from 2.7 to 2.6
– Inserted max value of VLVDLVCORL
– Updated VPORH values
– Updated VLVDLVCORL value
Table “Low voltage power domain electrical characteristics“
– Entirely updated
Table “Program and erase specifications“
– Inserted Teslat row
Table “Flash power supply DC electrical characteristics“
– Entirely updated

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Table 55. Document revision history (continued)

Date Revision Changes

Table “Start-up time/Switch-off time“

– Entirely updated
Figures “Crystal oscillator and resonator connection scheme“
– Relocated a note
Table ”Slow external crystal oscillator (32 kHz) electrical characteristics”
– Removed gmSXOSC row
– Inserted values of ISXOSCBIAS
Table ”FMPLL electrical characteristics”
– Rounded the values of fVCO
Table “Fast internal RC oscillator (16 MHz) electrical characteristics“
– Entirely updated.
Table “ADC conversion characteristics”
7
22-Jul-2010 – Updated the description of the conditions of tADC_PU and tADC_S.
(continued)
– Added “IADCPWD” and “IADCRUN” rows
Table “DSPI characteristics“
– Entirely updated.
Updated “Order codes” table.
Figure “Commercial product code structure”
– Replaced PowerPC with “Power Architecture™“ in the product identifier
– Removed the note about the condition from “Flash read access timing“ table
– Removed the notes that assert the values need to be confirmed before validation
– Exchanged the order of “LQFP 100-pin configuration” and “LQFP 144-pin
configuration”
– Exchanged the order of “LQFP 100-pin package mechanical drawing” and “LQFP
144-pin package mechanical drawing”
Editorial changes and improvements.
In the “SPC560B40x/50x and SPC560C40x/50x device comparison” table, changed
the temperature value from 105 to 125 °C, in the footnote regarding “Execution
speed”.

In the “LQFP thermal characteristics” table, added values concerning LQFP64

package.
In the “MEDIUM configuration output buffer electrical characteristics” table: fixed a typo
25-Nov-2010 8
in last row of conditions column, there was IOH that now is IOL.
In the “Reset electrical characteristics” table, changed the parameter classification tag
for VOL and |IWPU|.
In the “Low voltage monitor electrical characteristics” table, changed the max value of
VLVDLVCORL from 1.5V to 1.15V.
In the “Program and erase specifications” table, replaced “Teslat” with “Tesus”.
In the “FMPLL electrical characteristics” table, changed the parameter classification
tag for fVCO.

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Table 55. Document revision history (continued)

Date Revision Changes

Formatting and minor editorial changes throughout

Harmonized oscillator nomenclature
Device summary table: removed 384 KB code flash device versions
Device comparison table: changed temperature value in footnote 2 from 105 °C to
125 °C; removed 384 KB code flash device versions
LQFP 64-pin configuration: renamed pin 6 from VPP_TEST to VSS_HV
Removed “Pin Muxing” section; added sections “Pad configuration during reset
phases”, “Voltage supply pins”, “Pad types”, “System pins,” “Functional ports”, and
“Nexus 2+ pins”
Section “NVUSRO register”: edited content to separate configuration into electrical
parameters and digital functionality; updated footnote describing default value of ‘1’
in field descriptions NVUSRO[PAD3V5V] and NVUSRO[OSCILLATOR_MARGIN]
Added section “NVUSRO[WATCHDOG_EN] field description”
Recommended operating conditions (3.3 V) and Recommended operating conditions
(5.0 V): updated conditions for ambient and junction temperature characteristics
I/O input DC electrical characteristics: updated ILKG characteristics
Section “I/O pad current specification”: removed content referencing the IDYNSEG
maximum value
I/O consumption: replaced instances of “Root medium square” with “Root mean
square”
I/O weight: replaced instances of bit “SRE” with “SRC”; added pads PH[9] and PH[10];
added supply segments; removed weight values in 64-pin LQFP for pads that do not
exist in that package
Reset electrical characteristics: updated parameter classification for |IWPU|
01-Oct-2011 9
Updated Voltage regulator electrical characteristics
Section “Low voltage detector electrical characteristics”: changed title (was “Voltage
monitor electrical characteristics”); added event status flag names found in RGM
chapter of device reference manual to POR module and LVD descriptions; replaced
instances of “Low voltage monitor” with “Low voltage detector”; updated values for
VLVDLVBKPL and VLVDLVCORL; replaced “LVD_DIGBKP” with “LVDLVBKP” in note
Updated section “Power consumption”
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics: updated
parameter classification for VFXOSCOP
Crystal oscillator and resonator connection scheme: added footnote about possibility
of adding a series resistor
Slow external crystal oscillator (32 kHz) electrical characteristics: updated footnote 1
FMPLL electrical characteristics: added short term jitter characteristics; inserted “—”
in empty min value cell of tlock row
Section “Input impedance and ADC accuracy”: changed “VA/VA2” to “VA2/VA” in
Equation 11
ADC input leakage current: updated ILKG characteristics
ADC conversion characteristics: updated symbols
On-chip peripherals current consumption: changed “supply current on “VDD_HV_ADC”
to “supply current on” VDD_HV” in IDD_HV(FLASH) row; updated IDD_HV(PLL) value—
was 3 * fperiph, is 30 * fperiph; updated footnotes
DSPI characteristics: added rows tPCSC and tPASC
Added DSPI PCS strobe (PCSS) timing diagram
Updated order codes.
17-Jan-2013 10 Internal review.

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Table 55. Document revision history (continued)

Date Revision Changes

In the cover feature list, replaced “System watchdog timer” with “Software watchdog
timer”
Table 3 (SPC560B40x/50x and SPC560C40x/50x series block summary), replaced
“System watchdog timer” with “Software watchdog timer” and specified AUTOSAR
(Automotive Open System Architecture)
Table 6 (Functional port pin descriptions), replaced VDD with VDD_HV
Figure 9 (Voltage regulator capacitance connection), updated pin name apperence
Renamed Figure 10 (VDD_HV and VDD_BV maximum slope) (was “VDD and VDD_BV
maximum slope”) and replaced VDD_HV(MIN) with VPORH(MAX)
Renamed Figure 11 (VDD_HV and VDD_BV supply constraints during STANDBY mode
exit) (was “VDD and VDD_BV supply constraints during STANDBY mode exit”)
Table 13 (Recommended operating conditions (3.3 V)), added minimum value of TVDD
and footnote about it.
Table 14 (Recommended operating conditions (5.0 V)), added minimum value of TVDD
and footnote about it.
18-Jan-2013 11 Section 3.17.1, Voltage regulator electrical characteristics:
replaced “slew rate of VDD/VDD_BV” with “slew rate of both VDD_HV and VDD_BV”
replaced “When STANDBY mode is used, further constraints apply to the
VDD/VDD_BV in order to guarantee correct regulator functionality during STANDBY
exit.” with “When STANDBY mode is used, further constraints are applied to the
both VDD_HV and VDD_BV in order to guarantee correct regulator function during
STANDBY exit.”
Table 28 (Power consumption on VDD_BV and VDD_HV), updated footnotes of
IDDMAX and IDDRUN stating that both currents are drawn only from the VDD_BV pin.
Table 32 (Flash memory power supply DC electrical characteristics), in the paremeter
column replaced VDD_BV and VDD_HV respectively with VDD_BV and VDD_HV.
Table 46 (On-chip peripherals current consumption), in the paremeter column
replaced VDD_BV, VDD_HV and VDD_HV_ADC respectively with VDD_BV, VDD_HV
and VDD_HV_ADC
Updated Section 3.26.2, Input impedance and ADC accuracy
Table 47 (DSPI characteristics), modified symbol for tPCSC and tPASC
18-Sep-2013 12 Updated Disclaimer.
In Table 2: SPC560B40x/50x and SPC560C40x/50x device comparison:
– changed the MPC5604BxLH entry for CAN (FlexCAN) from 37 to 26.
– updated tablenote 7.
In Table 14: Recommended operating conditions (5.0 V), updated tablenote 5 to: “1
µF (electrolithic/tantalum) + 47 nF (ceramic) capacitance needs to be provided
03-Feb-2015 13 between VDD_ADC/VSS_ADC pair. Another ceramic cap of 10nF with low inductance
package can be added”.
In Section 3.17.2: Low voltage detector electrical characteristics, added a note on
LVHVD5 detector.
In Section 5: Ordering information, added a note: “Not all options are available on all
devices”.

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