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Successive Approximation ADC

This document describes the operation of a successive approximation analog-to-digital converter (ADC). It consists of a sample and hold circuit, comparator, digital-to-analog converter (DAC), and successive approximation register. It works by using a binary search algorithm to test each bit of the input voltage level against a reference voltage until the digital output converges on the input value within the converter's resolution.

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268 views

Successive Approximation ADC

This document describes the operation of a successive approximation analog-to-digital converter (ADC). It consists of a sample and hold circuit, comparator, digital-to-analog converter (DAC), and successive approximation register. It works by using a binary search algorithm to test each bit of the input voltage level against a reference voltage until the digital output converges on the input value within the converter's resolution.

Uploaded by

nvenkatesh485
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Successive approximation ADC 1

Successive approximation ADC


A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog
waveform into a discrete digital representation via a binary search through all possible quantization levels before
finally converging upon a digital output for each conversion.

Block diagram
Key
• DAC = Digital-to-Analog converter
• EOC = end of conversion
• SAR = successive approximation register
• S/H = sample and hold circuit
• Vin = input voltage
• Vref = reference voltage

Algorithm
The successive approximation Analog to
digital converter circuit typically consists of
four chief subcircuits:
1. A sample and hold circuit to acquire
the input voltage (Vin).
Successive Approximation ADC Block Diagram
2. An analog voltage comparator that
compares Vin to the output of the
internal DAC and outputs the result of the comparison to the successive approximation register (SAR).
3. A successive approximation register subcircuit designed to supply an approximate digital code of Vin to the
internal DAC.
4. An internal reference DAC that, for comparison with V, supplies the comparator with an analog voltage equal
to the digital code output of the SARin.
The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. This
code is fed into the DAC, which then supplies the analog equivalent of this digital code (Vref/2) into the comparator
circuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin the comparator causes the
SAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing
this binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of the
sampled input voltage and is finally output by the SAR at the end of the conversion (EOC).
Mathematically, let Vin = xVref, so x in [-1, 1] is the normalized input voltage. The objective is to approximately
digitize x to an accuracy of 1/2n. The algorithm proceeds as follows:
1. Initial approximation x0 = 0.
2. ith approximation xi = xi-1 - s(xi-1 - x)/2i.
where, s(x) is the signum-function(sgn(x)) (+1 for x ≥ 0, -1 for x < 0). It follows using mathematical induction that
|xn - x| ≤ 1/2n.
As shown in the above algorithm, a SAR ADC requires:
1. An input voltage source Vin.
2. A reference voltage source Vref to normalize the input.
Successive approximation ADC 2

3. A DAC to convert the ith approximation xi to a voltage.


4. A Comparator to perform the function s(xi - x) by comparing the DAC's voltage with the input voltage.
5. A Register to store the output of the comparator and apply xi-1 - s(xi-1 - x)/2i.

Charge-redistribution successive approximation ADC


One of the most common implementations
of the successive approximation ADC, the
charge-redistribution successive
approximation ADC, uses a charge scaling
DAC. The charge scaling DAC simply
consists of an array of individually switched
binary-weighted capacitors. The amount of
charge upon each capacitor in the array is
used to perform the aforementioned binary
search in conjunction with a comparator
internal to the DAC and the successive
Charge Scaling DAC
approximation register.

1. First, the capacitor array is completely discharged to the offset voltage of the comparator, VOS. This step
provides automatic offset cancellation(i.e. The offset voltage represents nothing but dead charge which can't
be juggled by the capacitors).
2. Next, all of the capacitors within the array are switched to the input signal, vIN. The capacitors now have a
charge equal to their respective capacitance times the input voltage minus the offset voltage upon each of
them.
3. In the third step, the capacitors are then switched so that this charge is applied across the comparator's input,
creating a comparator input voltage equal to -vIN.
4. Finally, the actual conversion process proceeds. First, the MSB capacitor is switched to VREF, which
corresponds to the full-scale range of the ADC. Due to the binary-weighting of the array the MSB capacitor
forms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the comparator is now -vIN plus
VREF/2. Subsequently, if vIN is greater than VREF/2 then the comparator outputs a digital 1 as the MSB,
otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparator
input voltage converges to the offset voltage, or at least as close as possible given the resolution of the DAC.

Split capacitor array


During the binary search process, the charge redistribution DAC
consumes power from the reference source for charging. There are
many energy efficient ways of charging the DAC and split capacitor
array is one of the way in which MSB capacitor is split to look like the
remaining DAC for small energy consumption.

3 bits simulation of a capacitive ADC


Successive approximation ADC 3

Use with non-ideal analog circuits


When implemented as an analog circuit - where the value of each successive bit is not perfectly 2^N (e.g. 1.1, 2.12,
4.05, 8.01, etc.) - a successive approximation approach might not output the ideal value because the binary search
algorithm incorrectly removes what it believes to be half of the values the unknown input cannot be. Depending on
the difference between actual and ideal performance, the maximum error can easily exceed several LSBs, especially
as the error between the actual and ideal 2^N becomes large for one or more bits. Since we don't know the actual
unknown input, it is therefore very important that accuracy of the analog circuit used to implement a SAR ADC be
very close to the ideal 2^N values; otherwise, we cannot guarantee a best match search.
ADVANTAGES
1. The conversion time is equal to the "n" clock cycle period for an n-bit ADC. Thus conversion time is very short.
For example for a 10-bit ADC with a clock frequency of 1 MHz, the conversion time will be only 10*10^-6 i.e.
10 microseconds.
2. Conversion time is constant and independent of the amplitude of analog signal V to the base A

References
• R. J. Baker, CMOS Circuit Design, Layout, and Simulation, Third Edition, Wiley-IEEE, 2010. ISBN
978-0-470-88132-3

External links
• Understanding SAR ADCs [1]

References
[1] http:/ / www. maxim-ic. com/ appnotes. cfm/ appnote_number/ 1080/ CMP/ WP-50
Article Sources and Contributors 4

Article Sources and Contributors


Successive approximation ADC  Source: http://en.wikipedia.org/w/index.php?oldid=594237592  Contributors: Amalas, B Pete, BD2412, Biscuittin, Braincricket, Btyner, EAderhold, Ec5618,
Eus Kevin, Ferdinand Pienaar, Firebat08, Jeff3000, LittleCreature, Mandarax, Michael Hardy, Nolelover, Oli Filth, Omar El-Sewefy, Pankaj Warule, Pjrm, R'n'B, Salvar, SeymourSycamore,
Smyth, Tabletop, Whiteflye, Zeeyanwiki, 65 anonymous edits

Image Sources, Licenses and Contributors


File:SA ADC block diagram.png  Source: http://en.wikipedia.org/w/index.php?title=File:SA_ADC_block_diagram.png  License: Creative Commons Attribution-Sharealike 2.5  Contributors:
White Flye
File:ChargeScalingDAC.png  Source: http://en.wikipedia.org/w/index.php?title=File:ChargeScalingDAC.png  License: Creative Commons Attribution-Sharealike 2.5  Contributors: White Flye
File:CAPadc.png  Source: http://en.wikipedia.org/w/index.php?title=File:CAPadc.png  License: Public Domain  Contributors: Gonzalj

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