+

Chapter 7 Input/Output

William Stallings , Computer Organization and Architecture, 9th Edition

+ 2

Objectives
 Why are peripherals not connected directly to the system bus?
 Why IO module is needed?
 How to control IO devices?
 How to increase IO operations?
 After studying this chapter, you should be able to:
 Explain the use of I/O modules as part of a computer
organization.
 Understand the difference between programmed I/O
and interrupt-driven I/O and discuss their relative
merits.
 Present an overview of the operation of direct memory
access (DMA).
 Explain the function and use of I/O channels.
+ 3

Contents

 7.1 External Devices

 7.2 I/O Modules

 7.3 Programmed I/O

 7.4 Interrupt-Driven I/O

 7.5 Direct Memory Access

 7.6 I/O Channels and Processors

+ 4

Why are devices not connected to

system bus?
 There are a wide variety of peripherals with various methods of
operation. It would be impractical to incorporate the necessary logic
within the processor to control a range of devices.

 The data transfer rate of peripherals is often much slower than that of
the memory or processor. Thus, it is impractical to use the high-speed
system bus to communicate directly with a peripheral.

 The data transfer rate of some peripherals can be faster than that of
the memory or processor. Again, the mismatch would lead to
inefficiencies if not managed properly.

 Peripherals often use different data formats and word lengths than
the computer to which they are attached.
+ Generic
Model
of an I/O
Module

Why an IO module is
needed?
• Interface to the
processor and memory
via the system bus or
central switch

• Interface to one or more

peripheral devices by
tailored data links
+ 6

7.1- External Devices

 Three categories:
 Provide a means of
exchanging data between the  Human readable
external environment and the  Suitable for communicating with
computer the computer user
 Video display terminals (VDTs),
printers
 Attach to the computer by a
link to an I/O module  Machine readable
 The link is used to exchange  Suitable for communicating with
control, status, and data equipment
between the I/O module and  Magnetic disk and tape systems,
the external device sensors and actuators (thiết bị
khởi phát)

 peripheral device  Communication

 An external device connected  Suitable for communicating with
to an I/O module remote devices such as a terminal,
a machine readable device, or
another computer
+
External
Device
Block
Diagram
bộ chuyển đổi
+ Keyboard/Monitor Most common means of
computer/user interaction
8

User provides input through the

International Reference keyboard
Alphabet (IRA) The monitor displays data
provided by the computer
 Basic unit of exchange is the character
Keyboard Codes
 Associated with each character is a code
 Each character in this code is represented  When the user depresses a key it
by a unique 7-bit binary code generates an electronic signal that is
 128 different characters can be interpreted by the transducer in the
represented keyboard and translated into the bit
pattern of the corresponding IRA code
 Characters are of two types:
 This bit pattern is transmitted to the I/O
 Printable
module in the computer
 Alphabetic, numeric, and special
characters that can be printed on paper  On output, IRA code characters are
or displayed on a screen transmitted to an external device from
 Control the I/O module
 Have to do with controlling the printing
or displaying of characters  The transducer interprets the code and
sends the required electronic signals to
 Example is carriage return
the output device either to display the
 Other control characters are concerned indicated character or perform the
with communications procedures
requested control function
7.2-I/O Modules Control and
9

timing
Module Functions • Coordinates the
flow of traffic
between internal
resources and
external devices

Error Processor
detection communication
• Involves command
• Detects and decoding, data,
reports The major status reporting,
transmission functions for address
errors recognition
an I/O
module fall
into the
following
categories:

Data buffering
Device
• Performs the communication
needed buffering
operation to • Involves
balance device commands, status
and memory information, and
speeds data
I/O Module Structure 10

IO Module
+ 7.3- Programmed I/O 11

 Three techniques are possible for I/O operations:

 Programmed I/O
 Data are exchanged between the processor and the I/O module
 Processor executes a program that gives it direct control of the I/O operation
 When the processor issues a command it must wait until the I/O operation is
complete
 If the processor is faster than the I/O module this is wasteful of processor time
 Interrupt-driven I/O
 Processor issues an I/O command, continues to execute other instructions, and is
interrupted by the I/O module when the latter has completed its work
 Direct memory access (DMA)
 The I/O module and main memory exchange data directly without processor
involvement
+ 12

I/O Commands
 There are four types of I/O commands that an I/O module may
receive when it is addressed by a processor:

1) Control
- used to activate a peripheral and tell it what to do

2) Test
- used to test various status conditions associated with an I/O
module and its peripherals

3) Read
- causes the I/O module to obtain an item of data from the
peripheral and place it in an internal buffer

4) Write
- causes the I/O module to take an item of data from the data bus
and subsequently transmit that data item to the peripheral
 13

Three
Techniques
for Input of a
Block of Data
I/O Instructions 14

With programmed I/O there is a close correspondence between the I/O-related

instructions that the processor fetches from memory and the I/O commands that
the processor issues to an I/O module to execute the instructions

Each I/O device connected through I/O modules is given a

unique identifier or address

The form of
the When the processor Memory-mapped I/O
instruction issues an I/O command,
the command contains
depends the address of the
on the way desired device
in which There is a single A single read line
external address space for and a single write
devices are memory locations line are needed on
Thus each I/O module and I/O devices the bus
addressed must interpret the
address lines to
determine if the
command is for itself
+ 15

I/O Mapping Summary

CPU MEM.

 Memory mapped I/O Io module

 Devices and memory share an address space
 I/O looks just like memory read/write Memory and IO
devices share a
 No special commands for I/O common system
 Large selection of memory access commands available bus

 Isolated I/O
 Separate address spaces 2 different
system buses
 Need I/O or memory select lines for Memory and
IO devices
 Special commands for I/O MEM.
CPU
 Limited set

Io module
 16

Memory
Mapped
I/O

Isolated
I/O
Example

+
7.4- Interrupt-Driven I/O 17

The problem with programmed I/O is that the

processor has to wait a long time for the I/O module
to be ready for either reception or transmission of
data

An alternative is for the processor to issue an I/O

command to a module and then go on to do some
other useful work

The I/O module will then interrupt the processor to

request service when it is ready to exchange data
with the processor

The processor executes the data transfer and

resumes its former processing
+

Simple Interrupt
Processing

READ BY YOURSELF
PSW: Process Status Word
+

Changes
in Memory
and Registers
for an
Interrupt
Design Issues
20

• Because there will

be multiple I/O
modules how does
the processor
determine which
Two design device issued the
interrupt?
issues arise in
implementing • If multiple
interrupt I/O: interrupts have
occurred how
does the
processor decide
which one to
process?
+ Device Identification 21

Four general categories of techniques are in

common use:
 Multiple interrupt lines
 Between the processor and the I/O modules
 Most straightforward approach to the problem
 Consequently even if multiple lines are used, it is likely that each line will have multiple I/O
modules attached to it

 Software poll
 When processor detects an interrupt it branches to an interrupt-service routine whose job is
to poll each I/O module to determine which module caused the interrupt
 Time consuming

 Daisy chain (hardware poll, vectored)

 The interrupt acknowledge line is daisy chained through the modules
 Vector – address of the I/O module or some other unique identifier
 Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service
routine, avoiding the need to execute a general interrupt-service routine first

 Bus arbitration (vectored)

 An I/O module must first gain control of the bus before it can raise the interrupt request line
 When the processor detects the interrupt it responds on the interrupt acknowledge line
 Then the requesting module places its vector on the data lines
+
Intel
82C59A
Interrupt
Controller

READ BY YOURSELF
 Intel 82C55A
+ 23

Programmable Peripheral Interface

READ BY YOURSELF
+
Keyboard/
Display
Interfaces to
82C55A

READ BY YOURSELF
 25
Drawbacks of Programmed and
Interrupt-Driven I/O

 Both forms of I/O suffer from two inherent

drawbacks:

1) The I/O transfer rate is limited by the

speed with which the processor can test
and service a device

2) The processor is tied up in managing an

I/O transfer; a number of instructions
must be executed for each I/O transfer

 When large volumes of data are to be moved a more

efficient technique is direct memory access (DMA)
+
7.5- Direct
Memory
Access
Typical DMA
Module Diagram
 DMA Operation 27

DMA

DMA

+ 7.12 shows where in the instruction cycle the processor may be suspended.
Figure
In each case, the processor is suspended just before it needs to use the bus.
The DMA module then transfers one word and returns control to the processor.
Note that this is not an interrupt; the processor does not save a context and do
something else. Rather, the processor pauses for one bus cycle. The overall effect
is to cause the processor to execute more slowly. Nevertheless, for a multiple-word
I/O transfer, DMA is far more efficient than interrupt-driven or programmed I/O.
+
Alternative
DMA
Configurations
8237 DMA Usage of System Bus 29

When DMA carries out, CPU is

idle. True or false?
+ 30

Fly-By DMA Controller

Data does not pass 8237 contains four

through and is not DMA channels
stored in DMA chip • Programmed
• DMA only independently
between I/O port Can do memory to • Any one active
and memory memory via register
• Numbered 0, 1, 2,
• Not between two and 3
I/O ports or two
memory locations
Table 7.2 – Intel 8237A Registers 31

READ BY YOURSELF

E/D = enable/disable
TC = terminal count
+ 7.6- IO Channels and Processors 32

Evolution of the I/O Function

1. The CPU directly controls a 4. The I/O module is given direct

peripheral device. access to memory via DMA. It can
now move a block of data to or
2. A controller or I/O module from memory without involving
the CPU, except at the beginning
is added. The CPU uses and end of the transfer.
programmed I/O without
interrupts. 5. The I/O module is enhanced to
become a processor in its own
3. Same configuration as in right, with a specialized
step 2 is used, but now instruction set tailored for I/O
interrupts are employed.
The CPU need not spend 6. The I/O module has a local
memory of its own and is, in fact, a
time waiting for an I/O
computer in its own right. With
operation to be performed,
this architecture a large set of I/O
thus increasing efficiency. devices can be controlled with
minimal CPU involvement.
+
I/O
Channel
Architecture
+ Exercises 34

 7.1- List three broad classifications of external, or

peripheral, devices.
 7.2- What is the International Reference Alphabet?
 7.3- What are the major functions of an I/O module?
 7.4- List and briefly define three techniques for
performing I/O.
 7.5- What is the difference between memory-mapped
I/O and isolated I/O?
 7.6- When a device interrupt occurs, how does the
processor determine which device issued the interrupt?
 7.7- When a DMA module takes control of a bus, and
while it retains control of the bus, what does the
processor do?
+ Summary
35

Input/Output
Chapter 7
 Direct memory access
 External devices  Drawbacks of programmed and
interrupt-driven I/O
 Keyboard/monitor
 DMA function
 Disk drive
 Intel 8237A DMA controller
 I/O modules
 Module function
 I/O channels and processors
 I/O module structure
 The evolution of the I/O function
 Programmed I/O
 Characteristics of I/O channels
 Overview of programmed I/O
 I/O commands
 The external interface
 I/O instructions
 Types of interfaces
 Interrupt-driven I/O
 Point-to-point and multipoint
 Interrupt processing configurations
 Design issues  Thunderbolt
 Intel 82C59A interrupt controller  InfiniBand
 Intel 82C55A programmable
peripheral interface