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UCC27523, UCC27524, UCC27525, UCC27526

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UCC2752x Dual 5-A High-Speed, Low-Side Gate Driver

1 Features 3 Description
•
1 Industry-Standard Pinout The UCC2752x family of devices are dual-channel,
high-speed, low-side gate-driver devices capable of
• Two Independent Gate-Drive Channels effectively driving MOSFET and IGBT power
• 5-A Peak Source and Sink-Drive Current switches. Using a design that inherently minimizes
• Independent-Enable Function for Each Output shoot-through current, UCC2752x can deliver high-
• TTL and CMOS Compatible Logic Threshold peak current pulses of up to 5-A source and 5-A sink
into capacitive loads along with rail-to-rail drive
Independent of Supply Voltage
capability and extremely small propagation delay
• Hysteretic-Logic Thresholds for High Noise (typically 13 ns). In addition, the drivers feature
Immunity matched internal propagation delays between the two
• Inputs and Enable Pin-Voltage Levels Not channels. These delays are very well suited for
Restricted by VDD Pin Bias Supply Voltage applications requiring dual-gate drives with critical
timing, such as synchronous rectifiers. This also
• 4.5-V to 18-V Single-Supply Range enables connecting two channels in parallel to
• Outputs Held Low During VDD-UVLO, (Ensures effectively increase current-drive capability or driving
Glitch-Free Operation at Power up and Power two switches in parallel with one input signal. The
Down) input pin thresholds are based on TTL and CMOS
• Fast Propagation Delays (13-ns Typical) compatible low-voltage logic, which is fixed and
independent of the VDD supply voltage. Wide
• Fast Rise and Fall Times (7-ns and 6-ns Typical) hysteresis between the high and low thresholds offers
• 1-ns Typical Delay Matching Between Two excellent noise immunity.
Channels
• Two Outputs are in Parallel for Higher Drive Device Information(1)
Current PART NUMBER PACKAGE BODY SIZE (NOM)

• Outputs Held Low When Inputs Floating SOT-23 (8) 4.90 mm × 3.91 mm
UCC27523 HVSSOP (8)
• PDIP (8), SOIC (8), MSOP (8) PowerPAD™ and 3.00 mm × 3.00 mm
3-mm × 3-mm WSON-8 Package Options WSON (8)
SOT-23 (8) 4.90 mm × 3.91 mm
• Operating Temperature Range of –40°C to 140°C
HVSSOP (8)
UCC27524 3.00 mm × 3.00 mm
2 Applications WSON (8)
PDIP (8) 9.81 mm × 6.35 mm
• Switched-Mode Power Supplies
SOT-23 (8) 4.90 mm × 3.91 mm
• DC-DC Converters
UCC27525 HVSSOP (8)
• Motor Control, Solar Power 3.00 mm × 3.00 mm
WSON (8)
• Gate Drive for Emerging Wide Band-Gap Power
UCC27526 WSON (8) 3.00 mm × 3.00 mm
Devices such as GaN
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Pin Configuration
One Inverting and One Dual Input Configuration
Dual Inverting Inputs Dual Non-Inverting Inputs Non-Inverting Input
UCC27526
UCC27523 UCC27524 UCC27525
INA- 1 8 INA+
ENA 1 8 ENB ENA 1 8 ENB ENA 1 8 ENB
+

INA 2 7 OUTA INA 2 7 OUTA INA 2 7 OUTA INB- 2 7 INB+

+

GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD GND 3 6 OUTA

INB 4 5 OUTB INB 4 5 OUTB INB 4 5 OUTB OUTB 4 5 VDD

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC27523, UCC27524, UCC27525, UCC27526
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Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 13
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 20
3 Description ............................................................. 1 9 Application and Implementation ........................ 21
4 Revision History..................................................... 2 9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 21
5 Description (continued)......................................... 4
6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 26
7 Specifications......................................................... 6 11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
7.1 Absolute Maximum Ratings ...................................... 6
11.2 Layout Example .................................................... 27
7.2 ESD Ratings.............................................................. 6
11.3 Thermal Considerations ........................................ 27
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information .................................................. 6 12 Device and Documentation Support ................. 29
7.5 Electrical Characteristics........................................... 7 12.1 Related Links ........................................................ 29
7.6 Switching Characteristics .......................................... 8 12.2 Trademarks ........................................................... 29
7.7 Typical Characteristics .............................................. 9 12.3 Electrostatic Discharge Caution ............................ 29
12.4 Glossary ................................................................ 29
8 Detailed Description ............................................ 12
8.1 Overview ................................................................. 12 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagrams ..................................... 12
Information ........................................................... 29

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (May, 2013) to Revision G Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Changed UCC2752X Gate Driver Output Structure image. ................................................................................................. 17

Changes from Revision E (June 2012) to Revision F Page

• Added 0.5 to PSW equation in Drive Current and Power Dissipation section ....................................................................... 24

Changes from Revision D (April 2012) to Revision E Page

• Added OUTA, OUTB voltage field and values. ...................................................................................................................... 6

• Changed table note from "Values are verified by characterization and are not production tested." to "Values are
verified by characterization on bench."................................................................................................................................... 6
• Added note, "Values are verified by characterization and are not production tested." .......................................................... 6
• Changed Switching Time tPW values from 10 ns and 25 ns to 15 ns and 25 ns ns. .............................................................. 7
• Changed Functional Block Diagrams images....................................................................................................................... 12
• Changed Slow Input Signal Figure 33.................................................................................................................................. 18

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Changes from Revision C (March 2012) to Revision D Page

• Changed Inputs (INA, INB, INA+, INA–, INB+, INB-) section to include UCC2752X (D, DGN, DSD) information. ............... 7
• Added Inputs (INA, INB, INA+, INA-, INB+, INB-) UCC27524P ONLY section. .................................................................... 7
• Changed Enable (ENA, ENB) section to include UCC2752X (D, DGN, DSD) information.................................................... 7
• Added ENABLE (ENA, ENB) UCC27524P ONLY section. .................................................................................................... 7

Changes from Revision B ( December 2011) to Revision C Page

• Added ROH note in the Outputs (OUTA, OUTB) section. ....................................................................................................... 7

• Added an updated Output Stage section. ............................................................................................................................ 17
• Added UCC2752X Gate Driver Output Structure image ...................................................................................................... 17
• Added an updated Low Propagation Delays and Tightly Matched Outputs section. ........................................................... 18
• Added Slow Input Signal Combined with Differences in Input Threshold Voltage image. ................................................... 18
• Added updated Drive Current and Power Dissipation section. ............................................................................................ 23
• Added a PSW... equation. .................................................................................................................................................... 24

Changes from Revision A (November 2011) to Revision B Page

• Changed Supply start threshold row to include two temperature ranges............................................................................... 7

• Changed Minimum operating voltage after supply start min and max values from 3.6 V to 4.2 V to 3.40 V and 4.40 V. ..... 7
• Changed Supply voltage hysteresis typ value from 0.35 to 0.30. .......................................................................................... 7
• Changed UCC27526 Block Diagram drawing. ..................................................................................................................... 13
• Changed UCC27526 Channel A in Inverting and Channel B in Non-Inverting Configuration drawing. ............................... 21

Changes from Original (November 2011) to Revision A Page

• Changed data sheet status to Production Data...................................................................................................................... 1

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5 Description (continued)
The UCC2752x family provide the combination of three standard logic options — dual inverting, dual
noninverting, one inverting and one noninverting driver. UCC27526 features a dual input design which offers
flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN–
pin controls the state of the driver output. The unused input pin is used for enable and disable functions. For
safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family
ensure that outputs are held LOW when input pins are in floating condition. The UCC27523, UCC27524, and
UCC27525 devices feature Enable pins (ENA and ENB) to have better control of the operation of the driver
applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard
operation.
UCC2752x family of devices are available in SOIC-8 (D), MSOP-8 with exposed pad (DGN) and 3-mm × 3-mm
WSON-8 with exposed pad (DSD) packages. UCC27524 is also offered in PDIP-8 (P) package. UCC27526 is
only offered in 3-mm × 3-mm WSON (DSD) package.

6 Pin Configuration and Functions

D, DGN, or P Package UCC2752(3,4,5)

8-Pin SOT-23, HVSSOP, or PDIP DSD Package UCC2752(3,4,5)
Top View 8-Pin WSON
Top View

ENA 1 8 ENB
ENA 1 8 ENB

INA 2 7 OUTA
INA 2 7 OUTA

GND 3 6 VDD
GND 3 6 VDD
INB 4 5 OUTB
INB 4 5 OUTB

DSD Package UCC27526

8-Pin WSON
Top View

INA- 1 8 INA+

INB- 2 7 INB+

GND 3 6 OUTA

OUTB 4 5 VDD

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Pin Functions (UCC27523 / UCC27524 / UCC27525)

PIN
I/O DESCRIPTION
NO. NAME
Enable input for Channel A: ENA biased LOW Disables Channel A output regardless of INA state,
1 ENA I ENA biased HIGH or floating Enables Channel A output, ENA allowed to float hence the pin-to-pin
compatibility with UCC2732X N/C pin.
Input to Channel A: Inverting Input in UCC27523, Non-Inverting Input in UCC27524, Inverting
2 INA I
Input in UCC27525, OUTA held LOW if INA is unbiased or floating.
3 GND - Ground: All signals referenced to this pin.
Input to Channel B: Inverting Input in UCC27523, Non-Inverting Input in UCC27524, Non-Inverting
4 INB I
Input in UCC27525, OUTB held LOW if INB is unbiased or floating.
5 OUTB O Output of Channel B
6 VDD I Bias supply input
7 OUTA O Output of Channel A
Enable input for Channel B: ENB biased LOW Disables Channel B output regardless of INB state,
8 ENB I ENB biased HIGH or floating Enables Channel B output, ENB allowed to float hence the pin-to-pin
compatibility with UCC2732X N/C pin.

Pin Functions (UCC27526)

PIN
I/O DESCRIPTION
NO. NAME
Inverting Input to Channel A: When Channel A is used in Non-Inverting configuration, connect
1 INA– I
INA– to GND in order to Enable Channel A output, OUTA held LOW if INA– is unbiased or floating.
Inverting Input to Channel B: When Channel B is used in Non-Inverting configuration, connect
2 INB– I
INB– to GND in order to Enable Channel B output, OUTB held LOW if INB– is unbiased or floating.
3 GND - Ground: All signals referenced to this pin.
4 OUTB I Output of Channel B
5 VDD O Bias Supply Input
6 OUTA I Output of Channel A
Non-Inverting Input to Channel B: When Channel B is used in Inverting configuration, connect
7 INB+ O
INB+ to VDD in order to Enable Channel B output, OUTB held LOW if INB+ is unbiased or floating.
Non-Inverting Input to Channel A: When Channel A is used in Inverting configuration, connect
8 INA+ I
INA+ to VDD in order to Enable Channel A output, OUTA held LOW if INA+ is unbiased or floating.

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7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage VDD –0.3 20
DC –0.3 VDD + 0.3 V
OUTA, OUTB voltage
Repetitive pulse < 200 ns (3) –2 VDD + 0.3
Output continuous source/sink
IOUT_DC 0.3
current
A
Output pulsed source/sink current
IOUT_pulsed 5
(0.5 µs)
INA, INB, INA+, INA–, INB+, INB–, ENA, ENB voltage (4) –0.3 20 V
Operating virtual junction temperature, TJ –40 150
Soldering, 10 s 300 °C
Lead temperature
Reflow 260
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Mechanical, Packaging, and Orderable Information for thermal limitations and considerations of packages.
(3) Values are verified by characterization on bench.
(4) The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.

7.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±1000 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, VDD 4.5 12 18 V
Operating junction temperature –40 140 °C
Input voltage, INA, INB, INA+, INA–, INB+, INB– 0 18 V
Enable voltage, ENA and ENB 0 18

7.4 Thermal Information

UCC27523/4/5 UCC27524 UCC27523/4/5/6
(1)
THERMAL METRIC SOIC (D) MSOP (DGN) PDIP (P) WSON (DSD) UNIT
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 130.9 71.8 62.1 46.7
RθJC(top) Junction-to-case (top) thermal resistance 80 65.6 52.7 46.7
RθJB Junction-to-board thermal resistance 71.4 7.4 39.1 22.4
°C/W
ψJT Junction-to-top characterization parameter 21.9 7.4 31 0.7
ψJB Junction-to-board characterization parameter 70.9 31.5 39.1 22.6
RθJC(bot) Junction-to-case (bottom) thermal resistance – 19.6 – 9.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics

VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal (unless otherwise noted,)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
BIAS CURRENTS
VDD = 3.4 V,
INA = VDD, 55 110 175
Start-up current, INB = VDD
IDD(off) (based on UCC27524 Input μA
configuration) VDD = 3.4 V,
INA = GND, 25 75 145
INB = GND
UNDERVOLTAGE LOCKOUT (UVLO)
TJ = 25°C 3.91 4.2 4.5
VON Supply start threshold
TJ = –40°C to 140°C 3.7 4.2 4.65
Minimum operating voltage V
VOFF 3.4 3.9 4.4
after supply start
VDD_H Supply voltage hysteresis 0.2 0.3 0.5
INPUTS (INA, INB, INA+, INA–, INB+, INB–), UCC2752X (D, DGN, DSD)
Output high for non-inverting input pins
VIN_H Input signal high threshold 1.9 2.1 2.3
Output low for inverting input pins
Output low for non-inverting input pins V
VIN_L Input signal low threshold 1 1.2 1.4
Output high for inverting input pins
VIN_HYS Input hysteresis 0.7 0.9 1.1
INPUTS (INA, INB, INA+, INA–, INB+, INB–) UCC27524P ONLY
Output high for non-inverting input pins
VIN_H Input signal high threshold 2.3
Output low for inverting input pins
Output low for non-inverting input pins V
VIN_L Input signal low threshold 1
Output high for inverting input pins
VIN_HYS Input hysteresis 0.9
ENABLE (ENA, ENB) UCC2752X (D, DGN, DSD)
VEN_H Enable signal high threshold Output enabled 1.9 2.1 2.3
VEN_L Enable signal low threshold Output disabled 0.95 1.15 1.35 V
VEN_HYS Enable hysteresis 0.7 0.95 1.1
ENABLE (ENA, ENB) UCC27524P ONLY
VEN_H Enable signal high threshold Output enabled 2.3
VEN_L Enable signal low threshold Output disabled 0.95 V
VEN_HYS Enable hysteresis 0.95
OUTPUTS (OUTA, OUTB)
ISNK/SRC Sink/source peak current (1) CLOAD = 0.22 µF, FSW = 1 kHz ±5 A
VDD-VOH High output voltage IOUT = –10 mA 0.075
V
VOL Low output voltage IOUT = 10 mA 0.01
ROH Output pullup resistance (2) IOUT = –10 mA 2.5 5 7.5 Ω
ROL Output pulldown resistance IOUT = 10 mA 0.15 0.5 1 Ω

(1) Ensured by design.

(2) ROH represents on-resistance of only the P-Channel MOSFET device in pullup structure of UCC2752X output stage.

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7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
tR Rise time CLOAD = 1.8 nF 7 18
tF Fall time (1) CLOAD = 1.8 nF 6 10
INA = INB, OUTA and OUTB at 50%
tM Delay matching between 2 channels 1 4
transition point
ns
Minimum input pulse width that
tPW 15 25
changes the output state
(1)
tD1, tD2 Input to output propagation delay CLOAD = 1.8 nF, 5-V input pulse 6 13 23
(1)
tD3, tD4 EN to output propagation delay CLOAD = 1.8 nF, 5-V enable pulse 6 13 23

(1) See timing diagrams in Figure 1, Figure 2, Figure 3, and Figure 4

High High

Input Input
Low Low

High High
Enable Enable
Low Low

90% 90%
Output Output
10% 10%

tD3 tD4 UDG-11217 tD3 tD4 UDG-11218

Figure 1. Enable Function Figure 2. Enable Function

(For Non-Inverting Input Driver Operation) (For Inverting Input Driver Operation)

High High

Input Input
Low Low

High High
Enable Enable
Low Low

90% 90%
Output Output
10% 10%

tD1 tD2 UDG-11219

tD1 tD2 UDG-11220

Figure 3. Non-Inverting Input Driver Operation Figure 4. Inverting Input Driver Operation

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7.7 Typical Characteristics

4
Input=VDD
0.14 Input=GND

Operating Supply Current (mA)

Startup Current (mA)

0.12 3.5

0.1
3
VDD = 12 V
0.08 fSW = 500 kHz
CL = 500 pF
VDD=3.4V
0.06 2.5
−50 0 50 100 150 −50 0 50 100 150
Temperature (°C) G001
Temperature (°C) G002

Figure 5. Start-Up Current vs Temperature Figure 6. Operating Supply Current vs Temperature

(Outputs Switching)
0.6 5
Input=GND UVLO Rising
Input=VDD UVLO Falling

0.5 4.5
Supply Current (mA)

UVLO Threshold (V)

0.4 4

0.3 3.5
Enable=12 V
VDD = 12 V

0.2 3
−50 0 50 100 150 −50 0 50 100 150
Temperature (°C) G012
Temperature (°C) G003

Figure 7. Supply Current vs Temperature (Outputs in DC Figure 8. UVLO Threshold vs Temperature

ON/OFF Condition)
2.5 2.5

2 2
Enable Threshold (V)
Input Threshold (V)

VDD = 12 V VDD = 12 V
1.5 1.5

1 1

Input High Threshold Enable High Threshold

Input Low Threshold Enable Low Threshold
0.5 0.5
−50 0 50 100 150 −50 0 50 100 150
Temperature (°C) G004
Temperature (°C) G005

Figure 9. Input Threshold vs Temperature Figure 10. Enable Threshold vs Temperature

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Typical Characteristics (continued)

7 1
VDD = 12 V VDD = 12 V

Output Pull−down Resistance (Ω)

IOUT = −10 mA IOUT = 10 mA
Output Pull−up Resistance (Ω)

6 0.8

5 0.6

4 0.4

3 0.2
−50 0 50 100 150 −50 0 50 100 150
Temperature (°C) G006
Temperature (°C) G007

Figure 11. Output Pullup Resistance vs Temperature Figure 12. Output Pulldown Resistance vs Temperature
10 9
VDD = 12 V VDD = 12 V
CLOAD = 1.8 nF CLOAD = 1.8 nF
9
8
Rise Time (ns)

Fall Time (ns)

8
7
7

6
6

5 5
−50 0 50 100 150 −50 0 50 100 150
Temperature (°C) G008
Temperature (°C) G009

Figure 13. Rise Time vs Temperature Figure 14. Fall Time vs Temperature
18 18
Input to Output Propagation Delay (ns)

Turn−on EN to Output High

EN to Output Propagation Delay (ns)

Turn−off EN to Output Low

16 16

14 14

12 12

10 10
VDD = 12 V VDD = 12 V
CLOAD = 1.8 nF CLOAD = 1.8 nF
8 8
−50 0 50 100 150 −50 0 50 100 150
Temperature (°C) G010
Temperature (°C) G011

Figure 15. Input to Output Propagation Delay vs Figure 16. EN to Output Propagation Delay vs Temperature
Temperature

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Typical Characteristics (continued)

60 22
VDD = 4.5 V Input to Output On delay
VDD = 12 V Input to Ouptut Off Delay
Operating Supply Current (mA)

50
VDD = 15 V EN to Output On Delay

Propagation Delays (ns)

18 EN to Output Off Delay
40
CLOAD = 1.8 nF
Both channels switching
30 14

20
10
10
CLOAD = 1.8 nF

0 6
0 100 200 300 400 500 600 700 800 900 1000 4 8 12 16 20
Frequency (kHz) G013 Supply Voltage (V) G014

Figure 17. Operating Supply Current vs Frequency Figure 18. Propagation Delays vs Supply Voltage
18 10
CLOAD = 1.8 nF CLOAD = 1.8 nF

14 8
Rise Time (ns)

Fall Time (ns)

10 6

6 4
4 8 12 16 20 4 8 12 16 20
Supply Voltage (V) G015 Supply Voltage (V) G016

Figure 19. Rise Time vs Supply Voltage Figure 20. Fall Time vs Supply Voltage
2.5
Enable High Threshold VDD = 4.5 V
Enable Low Threshold

2
Enable Threshold (V)

1.5

0.5
−50 0 50 100 150
Temperature (°C) G017

Figure 21. Enable Threshold vs Temperature

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8 Detailed Description

8.1 Overview
The UCC2752x family of products represent TI’s latest generation of dual-channel, low-side, high-speed gate-
driver devices featuring 5-A source and sink current capability, industry best-in-class switching characteristics
and a host of other features listed in Table 1 all of which combine to ensure efficient, robust and reliable
operation in high-frequency switching power circuits.

Table 1. UCC2752x Family of Features and Benefits

FEATURE BENEFIT
Best-in-class 13-ns (typ) propagation delay Extremely low-pulse transmission distortion
1-ns (typ) delay matching between channels Ease of paralleling outputs for higher (2 times) current capability,
ease of driving parallel-power switches
Expanded VDD Operating range of 4.5 to 18 V Flexibility in system design
Expanded operating temperature range of –40°C to 140°C
(See Electrical Characteristics)
VDD UVLO Protection Outputs are held Low in UVLO condition, which ensures predictable,
glitch-free operation at power-up and power-down
Outputs held Low when input pins (INx) in floating condition Safety feature, especially useful in passing abnormal condition tests
during safety certification
Outputs enable when enable pins (ENx) in floating condition Pin-to-pin compatibility with UCC2732X family of products from TI, in
designs where pin 1 and 8 are in floating condition
CMOS/TTL compatible input and enable threshold with wide Enhanced noise immunity, while retaining compatibility with
hysteresis microcontroller logic level input signals (3.3 V, 5 V) optimized for
digital power
Ability of input and enable pins to handle voltage levels not restricted System simplification, especially related to auxiliary bias supply
by VDD pin bias voltage architecture

8.2 Functional Block Diagrams

VDD VDD VDD VDD

200 kW 200 kW 200 kW 200 kW

ENA 1 8 ENB ENA 1 8 ENB

VDD
VDD VDD
200 kW
INA OUTA
INA 2 7 OUTA 2 7

VDD 400 kW VDD

GND 3 VDD VDD
VDD
VDD UVLO UVLO
6 VDD GND 3 6
VDD VDD
200 kW
INB OUTB
INB 4 5 OUTB 4 5

400 kW

UDG-11221

Figure 22. UCC27523 Block Diagram Figure 23. UCC27524 Block Diagram

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Functional Block Diagrams (continued)

VDD VDD
INA+ 8 VDD
200 kW 200 kW
400 kW 5 VDD
ENA 1 8 ENB
VDD
VDD
VDD
VDD 200 kW
200 kW
INA- 1 6 OUTA
INA 2 7 OUTA
VDD
VDD
GND 3
VDD
UVLO
UVLO VDD
GND 3 6 VDD
VDD
INB+ 7 4 OUTB

INB 4 5 OUTB
VDD 400 kW
400 kW

200 kW
UDG-11223 INB- 2

UDG-11222

Figure 24. UCC27525 Block Diagram Figure 25. UCC27526 Block Diagram

8.3 Feature Description

8.3.1 VDD and Undervoltage Lockout
The UCC2752x devices have internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply
circuit blocks. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output LOW,
regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis
prevents chatter when low VDD supply voltages have noise from the power supply and also when there are
droops in the VDD bias voltage when the system commences switching and there is a sudden increase in IDD.
The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching
characteristics, is especially suited for driving emerging GaN power semiconductor devices.
For example, at power up, the UCC2752x driver-device output remains LOW until the VDD voltage reaches the
UVLO threshold if Enable pin is active or floating. The magnitude of the OUT signal rises with VDD until steady-
state VDD is reached. The non-inverting operation in Figure 26 shows that the output remains LOW until the
UVLO threshold is reached, and then the output is in-phase with the input. The inverting operation in Figure 27
shows that the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with
the input. With UCC27526 the output turns to high-state only if INX+ is high and INX– is low after the UVLO
threshold is reached.
Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, TI recommends two VDD bypass capacitors to prevent noise problems. TI highly recommends using
surface-mount components. A 0.1-μF ceramic capacitor must be located as close as possible to the VDD to GND
pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low ESR must be
connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load.
The parallel combination of capacitors presents a low impedance characteristic for the expected current levels
and switching frequencies in the application.

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Feature Description (continued)

VDD Threshold VDD Threshold

VDD VDD

EN EN

IN IN

OUT OUT

UDG-11228 UDG-11229

Figure 26. Power up Non-Inverting Driver Figure 27. Power up Inverting Driver

8.3.2 Operating Supply Current

The UCC2752x products feature very low quiescent IDD currents. The typical operating-supply current in UVLO
state and fully on state (under static and switching conditions) are summarized in Figure 5, Figure 6 and
Figure 7. The IDD current when the device is fully on and outputs are in a static state (DC high or DC low, refer
Figure 6) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully
operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current due to
switching and finally any current related to pullup resistors on the enable pins and inverting input pins. For
example when the inverting Input pins are pulled low additional current is drawn from VDD supply through the
pullup resistors (refer to Figure 22 though Figure 25). Knowing the operating frequency (fSW) and the MOSFET
gate (QG) charge at the drive voltage being used, the average IOUT current can be calculated as product of QG
and fSW.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages
under 1.8-nF switching load in both channels is provided in Figure 17. The strikingly linear variation and close
correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device
attesting to its high-speed characteristics.

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Feature Description (continued)

8.3.3 Input Stage
The input pins of UCC2752x gate-driver devices are based on a TTL and CMOS compatible input-threshold logic
that is independent of the VDD supply voltage. With typically high threshold = 2.1 V and typically low threshold =
1.2 V, the logic level thresholds are conveniently driven with PWM control signals derived from 3.3-V and 5-V
digital power-controller devices. Wider hysteresis (typ 0.9 V) offers enhanced noise immunity compared to
traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. UCC2752x devices also
feature tight control of the input pin threshold voltage levels which eases system design considerations and
ensures stable operation across temperature (refer to Figure 9). The very low input capacitance on these pins
reduces loading and increases switching speed.
The UCC2752x devices feature an important safety feature wherein, whenever any of the input pins is in a
floating condition, the output of the respective channel is held in the low state. This is achieved using VDD pullup
resistors on all the Inverting inputs (INA, INB in UCC27523, INA in UCC27525 and INA–, INB– in UCC27526) or
GND pulldown resistors on all the non-inverting input pins (INA, INB in UCC27524, INB in UCC27525 and INA+,
INB+ in UCC27526), as shown in the device block diagrams.
While UCC27523/4/5 devices feature one input pin per channel, the UCC27526 features a dual input
configuration with two input pins available to control the output state of each channel. With the UCC27526 device
the user has the flexibility to drive each channel using either a non-inverting input pin (INx+) or an inverting input
pin (INx–). The state of the output pin is dependent on the bias on both the INx+ and INx– pins (where x = A, B).
Once an Input pin is chosen to drive a channel, the other input pin of that channel (the unused input pin) must be
properly biased in order to enable the output of the channel. The unused input pin cannot remain in a floating
condition because, as mentioned earlier, whenever any input pin is left in a floating condition, the output of that
channel is disabled using the internal pullup or pulldown resistors for safety purposes. Alternatively, the unused
input pin is used effectively to implement an enable/disable function, as explained below.
• In order to drive the channel x (x = A or B) in a non-inverting configuration, apply the PWM control input
signal to INx+ pin. In this case, the unused input pin, INx-, must be biased low (for example, tied to GND) in
order to enable the output of this channel.
– Alternately, the INx– pin can be used to implement the enable/disable function using an external logic
signal. OUTx is disabled when INx- is biased High and OUTx is enabled when INX– is biased low.
• In order to drive the channel x (x = A or B) in an Inverting configuration, apply the PWM control input signal to
INX– pin. In this case, the unused input pin, INX+, must be biased high (for example, tied to VDD) in order to
enable the output of the channel.
– Alternately, the INX+ pin can be used to implement the enable/disable function using an external logic
signal. OUTX is disabled when INX+ is biased low and OUTX is enabled when INX+ is biased high.
• Finally, it is worth noting that the UCC27526 output pin can be driven into high state only when INx+ pin is
biased high and INx- input is biased low.
Refer to the input/output logic truth table and typical application diagrams, (Figure 34, Figure 35, and Figure 35),
for additional clarification.
The input stage of each driver is driven by a signal with a short rise or fall time. This condition is satisfied in
typical power supply applications, where the input signals are provided by a PWM controller or logic gates with
fast transition times (< 200 ns) with a slow changing input voltage, the output of the driver may switch repeatedly
at a high frequency. While the wide hysteresis offered in UCC2752x definitely alleviates this concern over most
other TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or fall
times to the power device is the primary goal, then TI highly recommends an external resistance between the
output of the driver and the power device. This external resistor has the additional benefit of reducing part of the
gate-charge related power dissipation in the gate-driver device package and transferring it into the external
resistor itself.

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Feature Description (continued)

8.3.4 Enable Function
The enable function is an extremely beneficial feature in gate-driver devices especially for certain applications
such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative
current circulation and to improve light-load efficiency.
UCC27523/4/5 devices are provided with independent enable pins ENx for exclusive control of each driver-
channel operation. The enable pins are based on a non-inverting configuration (active-high operation). Thus
when ENx pins are driven high the drivers are enabled and when ENx pins are driven low the drivers are
disabled. Like the input pins, the enable pins are also based on a TTL and CMOS compatible input-threshold
logic that is independent of the supply voltage and are effectively controlled using logic signals from 3.3-V and 5-
V microcontrollers. The UCC2752X devices also feature tight control of the Enable-function threshold-voltage
levels which eases system design considerations and ensures stable operation across temperature (refer to
Figure 10). The ENx pins are internally pulled up to VDD using pullup resistors as a result of which the outputs of
the device are enabled in the default state. Hence the ENx pins are left floating or Not Connected (N/C) for
standard operation, where the enable feature is not needed. Essentially, this floating allows the UCC27523/4/5
devices to be pin-to-pin compatible with TI’s previous generation drivers UCC27323/4/5 respectively, where pins
1, 8 are N/C pins. If the Channel A and Channel B inputs and outputs are connected in parallel to increase the
driver current capacity, ENA and ENB are connected and driven together.
The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an
enable/disable function is easily implemented in UCC27526 using the unused input pin. When INx+ is pulled
down to GND or INx– is pulled down to VDD, the output is disabled. Thus INx+ pin is used like an enable pin that
is based on active high logic, while INx– is used like an enable pin that is based on active low logic. Note that
while the ENA, ENB pins in UCC27523/4/5 are allowed to be in floating condition during standard operation and
the outputs will be enabled, the INx+, INx– pins in UCC27526 are not allowed to be floating because this will
disable the outputs.

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Feature Description (continued)

8.3.5 Output Stage
The UCC2752x device output stage features a unique architecture on the pullup structure which delivers the
highest peak-source current when it is most needed during the Miller plateau region of the power-switch turnon
transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pullup structure
features a P-channel MOSFET and an additional N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a brief boost in the peak sourcing current enabling fast turnon. This is accomplished by
briefly turning-on the N-channel MOSFET during a narrow instant when the output is changing state from Low to
High.
VCC

ROH

RNMOS, Pull Up

Gate
Voltage OUT
Input Signal Anti Shoot-
Boost
Through
Circuitry Narrow Pulse at
each Turn On
R OL

Figure 28. UCC2752x Gate Driver Output Structure

The ROH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the on-
resistance of the P-Channel device only. This is because the N-Channel device is held in the off state in DC
condition and is turned-on only for a narrow instant when output changes state from low to high. Note that
effective resistance of UCC2752x pullup stage during the turnon instant is much lower than what is represented
by ROH parameter.
The pulldown structure in UCC2752x is simply composed of a N-Channel MOSFET. The ROL parameter (see
Electrical Characteristics), which is also a DC measurement, is representative of the impedance of the pulldown
stage in the device. In UCC2752x, the effective resistance of the hybrid pullup structure during turnon is
estimated to be approximately 1.5 × ROL, estimated based on design considerations.
Each output stage in UCC2752x can supply 5-A peak source and 5-A peak sink current pulses. The output
voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS-output stage which
delivers very low drop-out. The presence of the MOSFET-body diodes also offers low impedance to switching
overshoots and undershoots which means that in many cases, external Schottky-diode clamps may be
eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either
damage to the device or logic malfunction.
The UCC2752x devices are particularly suited for dual-polarity, symmetrical drive-gate transformer applications
where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being driven
complementary to each other. This situation is due to the extremely low drop-out offered by the MOS output
stage of these devices, both during high (VOH) and low (VOL) states along with the low impedance of the driver
output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance.
The low propagation delays also ensure accurate reset for high-frequency applications.

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Feature Description (continued)

For applications that have zero voltage switching during power MOSFET turnon or turnoff interval, the driver
supplies high-peak current for fast switching even though the miller plateau is not present. This situation often
occurs in synchronous rectifier applications because the body diode is generally conducting before power
MOSFET is switched on.

8.3.6 Low Propagation Delays and Tightly Matched Outputs

The UCC2752x driver devices feature a best in class, 13-ns (typical) propagation delay between input and output
which goes to offer the lowest level of pulse-transmission distortion available in the industry for high frequency
switching applications. For example in synchronous rectifier applications, the SR MOSFETs are driven with very
low distortion when one driver device is used to drive both the SR MOSFETs. Further, the driver devices also
feature an extremely accurate, 1-ns (typ) matched internal-propagation delays between the two channels which
is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC application, a
pair of paralleled MOSFETs may be driven independently using each output channel, which the inputs of both
channels are driven by a common control signal from the PFC controller device. In this case the 1ns delay
matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum of turnon
delay difference. Yet another benefit of the tight matching between the two channels is that the two channels are
connected together to effectively increase current drive capability, for example A and B channels may be
combined into one driver by connecting the INA and INB inputs together and the OUTA and OUTB outputs
together. Then, one signal controls the paralleled combination.
Caution must be exercised when directly connecting OUTA and OUTB pins together because there is the
possibility that any delay between the two channels during turnon or turnoff may result in shoot-through current
conduction as shown in Figure 29. While the two channels are inherently very well matched (4-ns Max
propagation delay), note that there may be differences in the input threshold voltage level between the two
channels which causes the delay between the two outputs especially when slow dV/dt input signals are
employed. TI recommends the following guidelines whenever the two driver channels are paralleled using direct
connections between OUTA and OUTB along with INA and INB:
• Use very fast dV/dt input signals (20 V/µs or greater) on INA and INB pins to minimize impact of differences
in input thresholds causing delays between the channels.
• INA and INB connections must be made as close to the device pins as possible.
Wherever possible, a safe practice would be to add an option in the design to have gate resistors in series with
OUTA and OUTB. This allows the option to use 0-Ω resistors for paralleling outputs directly or to add appropriate
series resistances to limit shoot-through current, should it become necessary.

VDD VDD

200 kW 200 kW

ENA 1 8 ENB

VDD ISHOOT-THROUGH

Slow Input Signal INA OUTA

2 7
VIN_H
(Channel B)
400 kW VDD
VIN_H
(Channel A) VDD
VDD
UVLO
GND 3 6
VDD

INB OUTB
4 5

400 kW

Figure 29. Slow Input Signal May Cause Shoot-Through Between Channels During Paralleling
(Recommended dV/dT is 20 V/Μs or Higher)

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Feature Description (continued)

Figure 30. Turnon Propagation Delay Figure 31. Turnon Rise Time
(CL = 1.8 nF, VDD = 12 V) (CL = 1.8 nF, VDD = 12 V)

Figure 32. Turnoff Propagation Delay Figure 33. Turnoff Fall Time
(CL = 1.8 nF, VDD = 12 V) (CL = 1.8 nF, VDD = 12 V)

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8.4 Device Functional Modes

Table 2. Device Logic Table (UCC27523/4/5)
UCC27523/4/5 UCC27523 UCC27524 UCC27525
ENA ENB INA INB OUTA OUTB OUTA OUTB OUTA OUTB
H H L L H H L L H L
H H L H H L L H H H
H H H L L H H L L L
H H H H L L H H L H
L L Any Any L L L L L L
(1) (1)
Any Any x x L L L L L L
x (1) x (1) L L H H L L H L
x (1) x (1) L H H L L H H H
x (1) x (1) H L L H H L L L
(1)
x x (1) H H L L H H L H

(1) Floating condition.

Table 3. Device Logic Table (UCC27526)

INx+ (x = A or B) INx- (x = A or B) OUTx (x = A or B)
L L L
L H L
H L H
H H L
x (1) Any L
Any x (1) L

(1) x = Floating condition.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to
effect fast switching of power devices and reduce associated switching-power losses, a powerful gate-driver
device employs between the PWM output of control devices and the gates of the power semiconductor devices.
Further, gate-driver devices are indispensable when having the PWM controller device directly drive the gates of
the switching devices is sometimes not feasible. With advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a
power switch. A level-shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V)
in order to fully turn on the power device and minimize conduction losses. Traditional buffer-drive circuits based
on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter-follower configurations, prove
inadequate with digital power because they lack level-shifting capability. Gate-driver devices effectively combine
both the level-shifting and buffer-drive functions. Gate-driver devices also find other needs such as minimizing
the effect of high-frequency switching noise by locating the high-current driver physically close to the power
switch, driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation
and thermal stress in controller devices by moving gate-charge power losses into the controller.
Finally, emerging wide band-gap power-device technologies such as GaN based switches, which can support
very high switching frequency operation, are driving special requirements in terms of gate-drive capability. These
requirements include operation at low VDD voltages (5 V or lower), low propagation delays, tight delay matching
and availability in compact, low-inductance packages with good thermal capability.
In summary gate-driver devices are extremely important components in switching power combining benefits of
high-performance, low-cost, component-count, board-space reduction, and simplified system design.

9.2 Typical Application

ENB

UCC2752x

ENA 1 ENA ENB 8

INA 2 INA OUTA 7

3 GND VDD 6 V+

GND
INB 4 INB OUTB 5

GND

GND UDG-11225

Figure 34. UCC2752x Typical Application Diagram (x = 3, 4, or 5)

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Typical Application (continued)

UCC27526

INA- 1 INA- INA+ 8

2 INB- INB+ 7 INB+

3 GND OUTA 6
V+
GND
GND 4 OUTB VDD 5

GND UDG-11226

Figure 35. UCC27526 Channel A in Inverting and Channel B in Non-Inverting Configuration (Enable
Function Not Used)

OUTA is
UCC27526 ENABLED when
ENA is HIGH
INA- 1 INA- INA+ 8 ENA

ENB 2 INB- INB+ 7 INB+

OUTB is
ENABLED when
3 GND OUTA 6
ENB is LOW
V+
GND
GND 4 OUTB VDD 5

GND UDG-11227

Figure 36. UCC27526 Channel A in Inverting and Channel B in Non-Inverting Configuration (Enable
Function Implemented)

9.2.1 Design Requirements

When selecting the proper gate-driver device for an end application, some design considerations must be
evaluated first in order to make the most appropriate selection. Among these considerations are input-to-output
logic, VDD, UVLO, Drive current and power dissipation.

9.2.2 Detailed Design Procedure

9.2.2.1 Input-to-Output Logic

The design should specify which type of input-to-output configuration should be used. The UCC27523 device can
provide dual inverting input to output with enable control. The UCC27524 device can provide dual non-inverting
input to output with enable control. The UCC27525 device can provide one inverting and one non-inverting input
to output control. If turning on the power MOSFET or IGBT when the input signal is in high state is preferred,
then the non-inverting configuration must be selected. If turning off the power MOSFET or IGBT when the input

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Typical Application (continued)

signal is in high state is preferred, the inverting configuration must be chosen. UCC27526 has dual configuration
channel. Each Channel of UCC27526 device can be configured in either an inverting or non-inverting input-to-
output configuration using the INx– or INx+ pins respectively like in Figure 35 and Figure 36. To configure the
channel for use in inverting mode, tie the INx+ pin to VDD and apply the input signal to the INx– pin. For the non-
inverting configuration, tie the INx– pin to GND and apply the input signal to the INx+ pin.

9.2.2.2 Enable and Disable Function

Certain applications demand independent control of the output state of the driver. The UCC27523/4/5 device
offers two independent enable pins ENx for exclusive control of each driver channels as listed in Table 2.
The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an
enable/disable function can be easily implemented in UCC27526 using the unused input pin. When INx+ is
pulled-down to GND or INx– is pulled-down to VDD, the output is disabled as listed in Table 3. Thus INx+ pin can
be used like an enable pin that is based on active high logic, while INx– can be used like an enable pin that is
based on active low logic. It is important to note that while the ENA, ENB pins in the UCC27523/4/5 are allowed
to be in floating condition during standard operation and the outputs will be enabled, the INx+, INx– pins in
UCC27526 are not allowed to be floating because this will disable the outputs.

9.2.2.3 VDD Bias Supply Voltage

The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the
Recommended Operating Conditions. However, different power switches demand different voltage levels to be
applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate voltage
may be required for turnon and a negative gate voltage may be required for turnoff, in which case the VDD bias
supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC2752x device can
be used to drive a variety of power switches, such as Si MOSFETs (for example, VGS = 4.5 V, 10 V, 12 V),
IGBTs (VGE = 15 V, 18 V).

9.2.2.4 Propagation Delay

The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is
used and the acceptable level of pulse distortion to the system. The UCC2752x device features fast 13-ns
(typical) propagation delays which ensures very little pulse distortion and allows operation at very high-
frequencies. See the Switching Characteristics for the propagation and switching characteristics of the
UCC2752x device.

9.2.2.5 Drive Current and Power Dissipation

The UCC27523/4/5/6 family of drivers are capable of delivering 5-A of current to a MOSFET gate for a period of
several-hundred nanoseconds at VDD = 12 V. High peak current is required to turn the device ON quickly. Then,
to turn the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the
operating frequency of the power device. The power dissipated in the gate-driver device package depends on the
following factors:
• Gate charge required of the power MOSFET (usually a function of the drive voltage VGS, which is very close
to input bias supply voltage VDD due to low VOH drop-out)
• Switching frequency
• Use of external gate resistors
Because UCC2752x features very low quiescent currents and internal logic to eliminate any shoot-through in the
output driver stage, their effect on the power dissipation within the gate driver can be safely assumed to be
negligible.
When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias
supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given
by Equation 1.

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SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015 www.ti.com

Typical Application (continued)

1
EG = CLOAD VDD2
2
where
• CLOAD is load capacitor
• VDD is bias voltage feeding the driver. (1)
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss
given by Equation 2.
PG = CLOAD VDD2 fSW

where
• fSW is the switching frequency (2)
With VDD = 12 V, CLOAD = 10 nF and ƒSW = 300 kHz the power loss is calculated as (see Equation 3):
PG = 10nF ´ 12 V 2 ´ 300kHz = 0.432 W (3)
The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the
gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the
added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to
switch the device under specified conditions. Using the gate charge Qg, the power that must be dissipated when
charging a capacitor is determined which by using the equivalence Qg = CLOADVDD to provide Equation 4 for
power:
PG = CLOAD VDD2 fSW = Qg VDD fSW
(4)
Assuming that UCC2752x is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at VDD = 12 V) on
each output, the gate charge related power loss is calculated as (see Equation 5):
PG = 2 x 60nC ´ 12 V ´ 300kHz = 0.432 W (5)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half
of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated
when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the
driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external
gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate
resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component).
Based on this simplified analysis, the driver power dissipation during switching is calculated as follows (see
Equation 6):
æ ROFF RON ö
PSW = 0.5 ´ QG ´ VDD ´ fSW ´ ç + ÷
è ROFF + RGATE RON + RGATE ø
where
• ROFF = ROL
• RON (effective resistance of pullup structure) = 1.5 x ROL (6)
In addition to the above gate-charge related power dissipation, additional dissipation in the driver is related to the
power associated with the quiescent bias current consumed by the device to bias all internal circuits such as
input stage (with pullup and pulldown resistors), enable, and UVLO sections. As shown in Figure 6, the quiescent
current is less than 0.6 mA even in the highest case. The quiescent power dissipation is calculated easily with
Equation 7.
PQ = IDD VDD (7)
Assuming , IDD = 6 mA, the power loss is:
PQ = 0.6 mA ´ 12 V = 7.2mW (8)
Clearly, this power loss is insignificant compared to gate charge related power dissipation calculated earlier.

24 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: UCC27523 UCC27524 UCC27525 UCC27526

 UCC27523, UCC27524, UCC27525, UCC27526
www.ti.com SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015

Typical Application (continued)

With a 12-V supply, the bias current is estimated as follows, with an additional 0.6-mA overhead for the
quiescent consumption:
P 0.432 W
IDD ~ G = = 0.036 A
VDD 12 V (9)

9.2.3 Application Curves

Figure 37 and Figure 38 show the typical switching characteristics of the non-inverting input driver operation for
UCC27523/4/5/6 device. CL = 1.8 nF, VDD = 12 V

Figure 37. Typical Turnon Waveform Figure 38. Typical Turnoff Waveform

Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: UCC27523 UCC27524 UCC27525 UCC27526
UCC27523, UCC27524, UCC27525, UCC27526
SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015 www.ti.com

10 Power Supply Recommendations

The bias supply voltage range for which the UCC2752X device is rated to operate is from 4.5 V to 18 V. The
lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD
pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VON
supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of
this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress
rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for the
VDD pin is 18 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage, device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD_H.
Therefore, ensuring that, while operating at or near the 4.2-V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below
the VOFF threshold which must be accounted for while evaluating system shutdown timing design requirements.
Likewise, at system startup, the device does not begin operation until the VDD pin voltage has exceeded above
the VON threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied
through the VDD pin. It is important to recognize that the charge for source current pulses delivered by the
OUTA/B pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the
output pins, a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that
local bypass capacitors are provided between the VDD and GND pins and located as close to the device as
possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI
recommends having two capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged very close
to the pins of the device and another surface-mount capacitor of few microfarads added in parallel.

11 Layout

11.1 Layout Guidelines

Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device
operation and design robustness. The UCC27523/4/5/6 family of gate drivers incorporates short propagation
delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at
the gate of power MOSFET to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current
capability is even higher (5-A peak current is at VDD = 12 V). Very high di/dt causes unacceptable ringing if the
trace lengths and impedances are not well controlled. TI strongly recommends the following circuit layout
guidelines when designing with these high-speed drivers.
• Locate the driver device as close as possible to power device in order to minimize the length of high-current
traces between the Output pins and the Gate of the power device.
• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal trace
length to improve the noise filtering. These capacitors support high peak current being drawn from VDD during
turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and chip
capacitors is highly recommended.
• The turnon and turnoff current loop paths (driver device, power MOSFET and VDD bypass capacitor) should
be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is
established in these loops at 2 instances during turnon and turnoff transients, which will induce significant
voltage transients on the output pin of the driver device and Gate of the power MOSFET.
• Wherever possible, parallel the source and return traces, taking advantage of flux cancellation
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM
controller at one, single point. The connected paths must be as short as possible to reduce inductance and
be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well
26 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: UCC27523 UCC27524 UCC27525 UCC27526

 UCC27523, UCC27524, UCC27525, UCC27526
www.ti.com SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015

Layout Guidelines (continued)

• In noisy environments, tying inputs of an unused channel of UCC27526 to VDD (in case of INx+) or GND (in
case of INX–) using short traces in order to ensure that the output is enabled and to prevent noise from
causing malfunction in the output may be necessary.
• Exercise caution when replacing the UCC2732x/UCC2742x devices with the UCC2752x:
– UCC2752x is a much stronger gate driver (5-A peak current versus 4-A peak current).
– UCC2752x is a much faster gate driver (13-ns/13-ns rise/fall propagation delay versus 25-ns/35-ns rise/fall
propagation delay).

11.2 Layout Example

Figure 39. Layout Example for UCC27523/4/5 (D, DGN)

11.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the device package. In order for a gate-driver device to be useful over a particular temperature
range the package must allow for the efficient removal of the heat produced while keeping the junction
temperature within rated limits. The UCC27523/4/5/6 family of drivers is available in four different packages to
cover a range of application requirements. The thermal metrics for each of these packages are summarized in
Thermal Information. For detailed information regarding the thermal information table, refer to Application Note
from Texas Instruments entitled, IC Package Thermal Metrics (SPRA953).

Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: UCC27523 UCC27524 UCC27525 UCC27526
UCC27523, UCC27524, UCC27525, UCC27526
SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015 www.ti.com

Thermal Considerations (continued)

Among the different package options available in the UCC2752x family, of particular mention are the DSD and
DGN packages when it comes to power dissipation capability. The MSOP PowerPAD-8 (DGN) package and 3-
mm × 3-mm WSON (DSD) package offer a means of removing the heat from the semiconductor junction through
the bottom of the package. Both these packages offer an exposed thermal pad at the base of the package. This
pad is soldered to the copper on the printed-circuit-board directly underneath the device package, reducing the
thermal resistance to a very low value. This allows a significant improvement in heat-sinking over that available in
the D or P packages. The printed-circuit-board must be designed with thermal lands and thermal vias to
complete the heat removal subsystem. Note that the exposed pads in the MSOP-8 (PowerPAD) and WSON-8
packages are not directly connected to any leads of the package, however, it is electrically and thermally
connected to the substrate of the device which is the ground of the device. TI recommends to externally connect
the exposed pads to GND in PCB layout for better EMI immunity.

28 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: UCC27523 UCC27524 UCC27525 UCC27526

 UCC27523, UCC27524, UCC27525, UCC27526
www.ti.com SLUSAQ3G – NOVEMBER 2011 – REVISED APRIL 2015

12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 4. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
UCC27523 Click here Click here Click here Click here Click here
UCC27524 Click here Click here Click here Click here Click here
UCC27525 Click here Click here Click here Click here Click here
UCC27526 Click here Click here Click here Click here Click here

12.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Links: UCC27523 UCC27524 UCC27525 UCC27526
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UCC27523D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27523

UCC27523DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27523

UCC27523DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27523

UCC27523DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27523

UCC27523DSDR ACTIVE SON DSD 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 27523

UCC27523DSDT ACTIVE SON DSD 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 27523

UCC27524D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27524

UCC27524DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27524

UCC27524DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27524

UCC27524DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27524

UCC27524DSDR ACTIVE SON DSD 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 SBA

UCC27524DSDT ACTIVE SON DSD 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 SBA

UCC27524P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 140 27524

UCC27525D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27525

UCC27525DGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27525

UCC27525DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 140 27525

UCC27525DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 140 27525

UCC27525DSDR ACTIVE SON DSD 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 27525

UCC27525DSDT ACTIVE SON DSD 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 27525

UCC27526DSDR ACTIVE SON DSD 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 SCB

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UCC27526DSDT ACTIVE SON DSD 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 140 SCB

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27523DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27523DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27523DSDR SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27523DSDT SON DSD 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27524DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27524DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27524DSDR SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27524DSDT SON DSD 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27525DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27525DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27525DSDR SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27525DSDT SON DSD 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27526DSDR SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27523DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
UCC27523DR SOIC D 8 2500 356.0 356.0 35.0
UCC27523DSDR SON DSD 8 3000 367.0 367.0 35.0
UCC27523DSDT SON DSD 8 250 210.0 185.0 35.0
UCC27524DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
UCC27524DR SOIC D 8 2500 356.0 356.0 35.0
UCC27524DSDR SON DSD 8 3000 367.0 367.0 35.0
UCC27524DSDT SON DSD 8 250 210.0 185.0 35.0
UCC27525DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
UCC27525DR SOIC D 8 2500 356.0 356.0 35.0
UCC27525DSDR SON DSD 8 3000 367.0 367.0 35.0
UCC27525DSDT SON DSD 8 250 210.0 185.0 35.0
UCC27526DSDR SON DSD 8 3000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UCC27523D D SOIC 8 75 506.6 8 3940 4.32
UCC27523DGN DGN HVSSOP 8 80 330 6.55 500 2.88
UCC27524D D SOIC 8 75 506.6 8 3940 4.32
UCC27524DGN DGN HVSSOP 8 80 330 6.55 500 2.88
UCC27524P P PDIP 8 50 506 13.97 11230 4.32
UCC27525D D SOIC 8 75 506.6 8 3940 4.32
UCC27525DGN DGN HVSSOP 8 80 330 6.55 500 2.88

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DSD 8 WSON - 0.8 mm max height
3 X 3, 0.8 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4227007/A

www.ti.com
 GENERIC PACKAGE VIEW
DGN 8 PowerPAD VSSOP - 1.1 mm max height
3 x 3, 0.65 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225482/A

www.ti.com
 PACKAGE OUTLINE
TM
DGN0008G SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
2.15
1.95 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.846
TYPICAL
1.646

4225480/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.846)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(2.15)
6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225480/A 11/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.846)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(2.15)
SYMM BASED ON
0.125 THICK
STENCIL

6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.06 X 2.40
0.125 1.846 X 2.15 (SHOWN)
0.15 1.69 X 1.96
0.175 1.56 X 1.82

4225480/A 11/2019
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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